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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xA2 byte (0x0)
mem_usage : registers
protection :

Registers

I2C_CON_REG

I2C_DATA_CMD_REG

I2C_SS_SCL_HCNT_REG

I2C_SS_SCL_LCNT_REG

I2C_FS_SCL_HCNT_REG

I2C_FS_SCL_LCNT_REG

I2C_INTR_STAT_REG

I2C_INTR_MASK_REG

I2C_RAW_INTR_STAT_REG

I2C_RX_TL_REG

I2C_TX_TL_REG

I2C_TAR_REG

I2C_CLR_INTR_REG

I2C_CLR_RX_UNDER_REG

I2C_CLR_RX_OVER_REG

I2C_CLR_TX_OVER_REG

I2C_CLR_RD_REQ_REG

I2C_CLR_TX_ABRT_REG

I2C_CLR_RX_DONE_REG

I2C_CLR_ACTIVITY_REG

I2C_CLR_STOP_DET_REG

I2C_CLR_START_DET_REG

I2C_CLR_GEN_CALL_REG

I2C_ENABLE_REG

I2C_STATUS_REG

I2C_TXFLR_REG

I2C_RXFLR_REG

I2C_SDA_HOLD_REG

I2C_SAR_REG

I2C_TX_ABRT_SOURCE_REG

I2C_SDA_SETUP_REG

I2C_ACK_GENERAL_CALL_REG

I2C_ENABLE_STATUS_REG

I2C_IC_FS_SPKLEN_REG


I2C_CON_REG

I2C Control Register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CON_REG I2C_CON_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_MASTER_MODE I2C_SPEED I2C_10BITADDR_SLAVE I2C_10BITADDR_MASTER I2C_RESTART_EN I2C_SLAVE_DISABLE

I2C_MASTER_MODE : This bit controls whether the controller master is enabled. 0= master disabled 1= master enabled Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.
bits : 0 - 0 (1 bit)
access : read-write

I2C_SPEED : These bits control at which speed the controller operates. 1= standard mode (100 kbit/s) 2= fast mode (400 kbit/s)
bits : 1 - 3 (3 bit)
access : read-write

I2C_10BITADDR_SLAVE : When acting as a slave, this bit controls whether the controller responds to 7- or 10-bit addresses. 0= 7-bit addressing 1= 10-bit addressing
bits : 3 - 6 (4 bit)
access : read-write

I2C_10BITADDR_MASTER : Controls whether the controller starts its transfers in 7- or 10-bit addressing mode when acting as a master. 0= 7-bit addressing 1= 10-bit addressing
bits : 4 - 8 (5 bit)
access : read-write

I2C_RESTART_EN : Determines whether RESTART conditions may be sent when acting as a master 0= disable 1=enable
bits : 5 - 10 (6 bit)
access : read-write

I2C_SLAVE_DISABLE : Slave enabled or disabled after reset is applied, which means software does not have to configure the slave. 0=slave is enabled 1=slave is disabled Software should ensure that if this bit is written with '0', then bit 0 should also be written with a '0'.
bits : 6 - 12 (7 bit)
access : read-write


I2C_DATA_CMD_REG

I2C Rx/Tx Data Buffer and Command Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_DATA_CMD_REG I2C_DATA_CMD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAT CMD

DAT : This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the controller. However, when you read this register, these bits return the value of data received on the controller's interface.
bits : 0 - 7 (8 bit)
access : read-write

CMD : This bit controls whether a read or a write is performed. This bit does not control the direction when the I2C Ctrl acts as a slave. It controls only the direction when it acts as a master. 1 = Read 0 = Write When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that CPU data is to be transmitted and as DAT or IC_DATA_CMD[7:0]. When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the I2C_RAW_INTR_STAT_REG), unless bit 11 (SPECIAL) in the I2C_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs. NOTE: It is possible that while attempting a master I2C read transfer on the controller, a RD_REQ interrupt may have occurred simultaneously due to a remote I2C master addressing the controller. In this type of scenario, it ignores the I2C_DATA_CMD write, generates a TX_ABRT interrupt, and waits to service the RD_REQ interrupt
bits : 8 - 16 (9 bit)
access : read-write


I2C_SS_SCL_HCNT_REG

Standard Speed I2C Clock SCL High Count Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_SS_SCL_HCNT_REG I2C_SS_SCL_HCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_SS_SCL_HCNT

IC_SS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set. NOTE: This register must not be programmed to a value higher than 65525, because the controller uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
bits : 0 - 15 (16 bit)
access : read-write


I2C_SS_SCL_LCNT_REG

Standard Speed I2C Clock SCL Low Count Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_SS_SCL_LCNT_REG I2C_SS_SCL_LCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_SS_SCL_LCNT

IC_SS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. This register can be written only when the I2C interface is disabled which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted, results in 8 being set.
bits : 0 - 15 (16 bit)
access : read-write


I2C_FS_SCL_HCNT_REG

Fast Speed I2C Clock SCL High Count Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_FS_SCL_HCNT_REG I2C_FS_SCL_HCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_FS_SCL_HCNT

IC_FS_SCL_HCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 6 hardware prevents values less than this being written, and if attempted results in 6 being set.
bits : 0 - 15 (16 bit)
access : read-write


I2C_FS_SCL_LCNT_REG

Fast Speed I2C Clock SCL Low Count Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_FS_SCL_LCNT_REG I2C_FS_SCL_LCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_FS_SCL_LCNT

IC_FS_SCL_LCNT : This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low-period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. This register can be written only when the I2C interface is disabled, which corresponds to the I2C_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 8 hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the controller. The lower byte must be programmed first. Then the upper byte is programmed.
bits : 0 - 15 (16 bit)
access : read-write


I2C_INTR_STAT_REG

I2C Interrupt Status Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_INTR_STAT_REG I2C_INTR_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R_RX_UNDER R_RX_OVER R_RX_FULL R_TX_OVER R_TX_EMPTY R_RD_REQ R_TX_ABRT R_RX_DONE R_ACTIVITY R_STOP_DET R_START_DET R_GEN_CALL

R_RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
bits : 0 - 0 (1 bit)
access : read-only

R_RX_OVER : Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
bits : 1 - 2 (2 bit)
access : read-only

R_RX_FULL : Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
bits : 2 - 4 (3 bit)
access : read-only

R_TX_OVER : Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared
bits : 3 - 6 (4 bit)
access : read-only

R_TX_EMPTY : This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0.
bits : 4 - 8 (5 bit)
access : read-only

R_RD_REQ : This bit is set to 1 when the controller is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register
bits : 5 - 10 (6 bit)
access : read-only

R_TX_ABRT : This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.
bits : 6 - 12 (7 bit)
access : read-only

R_RX_DONE : When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
bits : 7 - 14 (8 bit)
access : read-only

R_ACTIVITY : This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
bits : 8 - 16 (9 bit)
access : read-only

R_STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
bits : 9 - 18 (10 bit)
access : read-only

R_START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
bits : 10 - 20 (11 bit)
access : read-only

R_GEN_CALL : Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. The controller stores the received data in the Rx buffer.
bits : 11 - 22 (12 bit)
access : read-only


I2C_INTR_MASK_REG

I2C Interrupt Mask Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_INTR_MASK_REG I2C_INTR_MASK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M_RX_UNDER M_RX_OVER M_RX_FULL M_TX_OVER M_TX_EMPTY M_RD_REQ M_TX_ABRT M_RX_DONE M_ACTIVITY M_STOP_DET M_START_DET M_GEN_CALL

M_RX_UNDER : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-write

M_RX_OVER : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 1 - 2 (2 bit)
access : read-write

M_RX_FULL : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 2 - 4 (3 bit)
access : read-write

M_TX_OVER : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 3 - 6 (4 bit)
access : read-write

M_TX_EMPTY : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 4 - 8 (5 bit)
access : read-write

M_RD_REQ : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 5 - 10 (6 bit)
access : read-write

M_TX_ABRT : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 6 - 12 (7 bit)
access : read-write

M_RX_DONE : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 7 - 14 (8 bit)
access : read-write

M_ACTIVITY : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 8 - 16 (9 bit)
access : read-write

M_STOP_DET : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 9 - 18 (10 bit)
access : read-write

M_START_DET : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 10 - 20 (11 bit)
access : read-write

M_GEN_CALL : These bits mask their corresponding interrupt status bits in the I2C_INTR_STAT register.
bits : 11 - 22 (12 bit)
access : read-write


I2C_RAW_INTR_STAT_REG

I2C Raw Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_RAW_INTR_STAT_REG I2C_RAW_INTR_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_UNDER RX_OVER RX_FULL TX_OVER TX_EMPTY RD_REQ TX_ABRT RX_DONE ACTIVITY STOP_DET START_DET GEN_CALL

RX_UNDER : Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
bits : 0 - 0 (1 bit)
access : read-only

RX_OVER : Set if the receive buffer is completely filled to 32 and an additional byte is received from an external I2C device. The controller acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (I2C_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
bits : 1 - 2 (2 bit)
access : read-only

RX_FULL : Set when the receive buffer reaches or goes above the RX_TL threshold in the I2C_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (I2C_ENABLE[0]=0), the RX FIFO is flushed and held in reset therefore the RX FIFO is not full. So this bit is cleared once the I2C_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
bits : 2 - 4 (3 bit)
access : read-only

TX_OVER : Set during transmit if the transmit buffer is filled to 32 and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared
bits : 3 - 6 (4 bit)
access : read-only

TX_EMPTY : This bit is set to 1 when the transmit buffer is at or below the threshold value set in the I2C_TX_TL register. It is automatically cleared by hardware when the buffer level goes above the threshold. When the IC_ENABLE bit 0 is 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer activity, then with ic_en=0, this bit is set to 0.
bits : 4 - 8 (5 bit)
access : read-only

RD_REQ : This bit is set to 1 when I2C Ctrl is acting as a slave and another I2C master is attempting to read data from the controller. The controller holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the I2C_DATA_CMD register. This bit is set to 0 just after the processor reads the I2C_CLR_RD_REQ register
bits : 5 - 10 (6 bit)
access : read-only

TX_ABRT : This bit indicates if the controller, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the I2C_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places. NOTE: The controller flushes/resets/empties the TX FIFO whenever this bit is set. The TX FIFO remains in this flushed state until the register I2C_CLR_TX_ABRT is read. Once this read is performed, the TX FIFO is then ready to accept more data bytes from the APB interface.
bits : 6 - 12 (7 bit)
access : read-only

RX_DONE : When the controller is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
bits : 7 - 14 (8 bit)
access : read-only

ACTIVITY : This bit captures I2C Ctrl activity and stays set until it is cleared. There are four ways to clear it: => Disabling the I2C Ctrl => Reading the IC_CLR_ACTIVITY register => Reading the IC_CLR_INTR register => System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the controller module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
bits : 8 - 16 (9 bit)
access : read-only

STOP_DET : Indicates whether a STOP condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
bits : 9 - 18 (10 bit)
access : read-only

START_DET : Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether controller is operating in slave or master mode.
bits : 10 - 20 (11 bit)
access : read-only

GEN_CALL : Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling controller or when the CPU reads bit 0 of the I2C_CLR_GEN_CALL register. I2C Ctrl stores the received data in the Rx buffer.
bits : 11 - 22 (12 bit)
access : read-only


I2C_RX_TL_REG

I2C Receive FIFO Threshold Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_RX_TL_REG I2C_RX_TL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_TL

RX_TL : Receive FIFO Threshold Level Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 31 sets the threshold for 32 entries.
bits : 0 - 4 (5 bit)
access : read-write


I2C_TX_TL_REG

I2C Transmit FIFO Threshold Register
address_offset : 0x3C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TX_TL_REG I2C_TX_TL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RX_TL

RX_TL : Transmit FIFO Threshold Level Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in I2C_RAW_INTR_STAT register). The valid range is 0-31, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 31 sets the threshold for 32 entries..
bits : 0 - 4 (5 bit)
access : read-write


I2C_TAR_REG

I2C Target Address Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TAR_REG I2C_TAR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_TAR GC_OR_START SPECIAL

IC_TAR : This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits. Note: If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself it can transmit to only a slave
bits : 0 - 9 (10 bit)
access : read-write

GC_OR_START : If bit 11 (SPECIAL) is set to 1, then this bit indicates whether a General Call or START byte command is to be performed by the controller. 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The controller remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. 1: START BYTE
bits : 10 - 20 (11 bit)
access : read-write

SPECIAL : This bit indicates whether software performs a General Call or START BYTE command. 0: ignore bit 10 GC_OR_START and use IC_TAR normally 1: perform special I2C command as specified in GC_OR_START bit
bits : 11 - 22 (12 bit)
access : read-write


I2C_CLR_INTR_REG

Clear Combined and Individual Interrupt Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_INTR_REG I2C_CLR_INTR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_INTR

CLR_INTR : Read this register to clear the combined interrupt, all individual interrupts, and the I2C_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing I2C_TX_ABRT_SOURCE
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_RX_UNDER_REG

Clear RX_UNDER Interrupt Register
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_RX_UNDER_REG I2C_CLR_RX_UNDER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_RX_UNDER

CLR_RX_UNDER : Read this register to clear the RX_UNDER interrupt (bit 0) of the I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_RX_OVER_REG

Clear RX_OVER Interrupt Register
address_offset : 0x48 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_RX_OVER_REG I2C_CLR_RX_OVER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_RX_OVER

CLR_RX_OVER : Read this register to clear the RX_OVER interrupt (bit 1) of the I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_TX_OVER_REG

Clear TX_OVER Interrupt Register
address_offset : 0x4C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_TX_OVER_REG I2C_CLR_TX_OVER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_TX_OVER

CLR_TX_OVER : Read this register to clear the TX_OVER interrupt (bit 3) of the I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_RD_REQ_REG

Clear RD_REQ Interrupt Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_RD_REQ_REG I2C_CLR_RD_REQ_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_RD_REQ

CLR_RD_REQ : Read this register to clear the RD_REQ interrupt (bit 5) of the I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_TX_ABRT_REG

Clear TX_ABRT Interrupt Register
address_offset : 0x54 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_TX_ABRT_REG I2C_CLR_TX_ABRT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_TX_ABRT

CLR_TX_ABRT : Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the I2C_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the I2C_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_RX_DONE_REG

Clear RX_DONE Interrupt Register
address_offset : 0x58 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_RX_DONE_REG I2C_CLR_RX_DONE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_RX_DONE

CLR_RX_DONE : Read this register to clear the RX_DONE interrupt (bit 7) of the I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_ACTIVITY_REG

Clear ACTIVITY Interrupt Register
address_offset : 0x5C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_ACTIVITY_REG I2C_CLR_ACTIVITY_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_ACTIVITY

CLR_ACTIVITY : Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_STOP_DET_REG

Clear STOP_DET Interrupt Register
address_offset : 0x60 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_STOP_DET_REG I2C_CLR_STOP_DET_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_ACTIVITY

CLR_ACTIVITY : Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_START_DET_REG

Clear START_DET Interrupt Register
address_offset : 0x64 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_START_DET_REG I2C_CLR_START_DET_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_START_DET

CLR_START_DET : Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_CLR_GEN_CALL_REG

Clear GEN_CALL Interrupt Register
address_offset : 0x68 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_CLR_GEN_CALL_REG I2C_CLR_GEN_CALL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR_GEN_CALL

CLR_GEN_CALL : Read this register to clear the GEN_CALL interrupt (bit 11) of I2C_RAW_INTR_STAT register.
bits : 0 - 0 (1 bit)
access : read-only


I2C_ENABLE_REG

I2C Enable Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_ENABLE_REG I2C_ENABLE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTRL_ENABLE

CTRL_ENABLE : Controls whether the controller is enabled. 0: Disables the controller (TX and RX FIFOs are held in an erased state) 1: Enables the controller Software can disable the controller while it is active. However, it is important that care be taken to ensure that the controller is disabled properly. When the controller is disabled, the following occurs: * The TX FIFO and RX FIFO get flushed. * Status bits in the IC_INTR_STAT register are still active until the controller goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the controller stops the current transfer at the end of the current byte and does not acknowledge the transfer. There is a two ic_clk delay when enabling or disabling the controller
bits : 0 - 0 (1 bit)
access : read-write


I2C_STATUS_REG

I2C Status Register
address_offset : 0x70 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_STATUS_REG I2C_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 I2C_ACTIVITY TFNF TFE RFNE RFF MST_ACTIVITY SLV_ACTIVITY

I2C_ACTIVITY : I2C Activity Status.
bits : 0 - 0 (1 bit)
access : read-only

TFNF : Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. 0: Transmit FIFO is full 1: Transmit FIFO is not full
bits : 1 - 2 (2 bit)
access : read-only

TFE : Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. 0: Transmit FIFO is not empty 1: Transmit FIFO is empty
bits : 2 - 4 (3 bit)
access : read-only

RFNE : Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries it is cleared when the receive FIFO is empty. 0: Receive FIFO is empty 1: Receive FIFO is not empty
bits : 3 - 6 (4 bit)
access : read-only

RFF : Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. 0: Receive FIFO is not full 1: Receive FIFO is full
bits : 4 - 8 (5 bit)
access : read-only

MST_ACTIVITY : Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Master FSM is in IDLE state so the Master part of the controller is not Active 1: Master FSM is not in IDLE state so the Master part of the controller is Active
bits : 5 - 10 (6 bit)
access : read-only

SLV_ACTIVITY : Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. 0: Slave FSM is in IDLE state so the Slave part of the controller is not Active 1: Slave FSM is not in IDLE state so the Slave part of the controller is Active
bits : 6 - 12 (7 bit)
access : read-only


I2C_TXFLR_REG

I2C Transmit FIFO Level Register
address_offset : 0x74 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TXFLR_REG I2C_TXFLR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TXFLR

TXFLR : Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Size is constrained by the TXFLR value
bits : 0 - 5 (6 bit)
access : read-only


I2C_RXFLR_REG

I2C Receive FIFO Level Register
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_RXFLR_REG I2C_RXFLR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RXFLR

RXFLR : Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Size is constrained by the RXFLR value
bits : 0 - 5 (6 bit)
access : read-only


I2C_SDA_HOLD_REG

I2C SDA Hold Time Length Register
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_SDA_HOLD_REG I2C_SDA_HOLD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_SDA_HOLD

IC_SDA_HOLD : SDA Hold time
bits : 0 - 15 (16 bit)
access : read-write


I2C_SAR_REG

I2C Slave Address Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_SAR_REG I2C_SAR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_SAR

IC_SAR : The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.
bits : 0 - 9 (10 bit)
access : read-write


I2C_TX_ABRT_SOURCE_REG

I2C Transmit Abort Source Register
address_offset : 0x80 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_TX_ABRT_SOURCE_REG I2C_TX_ABRT_SOURCE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ABRT_7B_ADDR_NOACK ABRT_10ADDR1_NOACK ABRT_10ADDR2_NOACK ABRT_TXDATA_NOACK ABRT_GCALL_NOACK ABRT_GCALL_READ ABRT_HS_ACKDET ABRT_SBYTE_ACKDET ABRT_HS_NORSTRT ABRT_SBYTE_NORSTRT ABRT_10B_RD_NORSTRT ABRT_MASTER_DIS ARB_LOST ABRT_SLVFLUSH_TXFIFO ABRT_SLV_ARBLOST ABRT_SLVRD_INTX

ABRT_7B_ADDR_NOACK : 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
bits : 0 - 0 (1 bit)
access : read-only

ABRT_10ADDR1_NOACK : 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
bits : 1 - 2 (2 bit)
access : read-only

ABRT_10ADDR2_NOACK : 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any slave.
bits : 2 - 4 (3 bit)
access : read-only

ABRT_TXDATA_NOACK : 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
bits : 3 - 6 (4 bit)
access : read-only

ABRT_GCALL_NOACK : 1: the controller in master mode sent a General Call and no slave on the bus acknowledged the General Call.
bits : 4 - 8 (5 bit)
access : read-only

ABRT_GCALL_READ : 1: the controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
bits : 5 - 10 (6 bit)
access : read-only

ABRT_HS_ACKDET : 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
bits : 6 - 12 (7 bit)
access : read-only

ABRT_SBYTE_ACKDET : 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
bits : 7 - 14 (8 bit)
access : read-only

ABRT_HS_NORSTRT : 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode
bits : 8 - 16 (9 bit)
access : read-only

ABRT_SBYTE_NORSTRT : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first restart must be enabled (I2C_CON[5]=1), the SPECIAL bit must be cleared (I2C_TAR[11]), or the GC_OR_START bit must be cleared (I2C_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted. 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the user is trying to send a START Byte.
bits : 9 - 18 (10 bit)
access : read-only

ABRT_10B_RD_NORSTRT : 1: The restart is disabled (IC_RESTART_EN bit (I2C_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode.
bits : 10 - 20 (11 bit)
access : read-only

ABRT_MASTER_DIS : 1: User tries to initiate a Master operation with the Master mode disabled.
bits : 11 - 22 (12 bit)
access : read-only

ARB_LOST : 1: Master has lost arbitration, or if I2C_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration. Note: I2C can be both master and slave at the same time.
bits : 12 - 24 (13 bit)
access : read-only

ABRT_SLVFLUSH_TXFIFO : 1: Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
bits : 13 - 26 (14 bit)
access : read-only

ABRT_SLV_ARBLOST : 1: Slave lost the bus while transmitting data to a remote master. I2C_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then the controller no longer own the bus.
bits : 14 - 28 (15 bit)
access : read-only

ABRT_SLVRD_INTX : 1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of 2IC_DATA_CMD register
bits : 15 - 30 (16 bit)
access : read-only


I2C_SDA_SETUP_REG

I2C SDA Setup Register
address_offset : 0x94 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_SDA_SETUP_REG I2C_SDA_SETUP_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDA_SETUP

SDA_SETUP : SDA Setup. This register controls the amount of time delay (number of I2C clock periods) between the rising edge of SCL and SDA changing by holding SCL low when I2C block services a read request while operating as a slave-transmitter. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2. It is recommended that if the required delay is 1000ns, then for an I2C frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.Writes to this register succeed only when IC_ENABLE[0] = 0.
bits : 0 - 7 (8 bit)
access : read-write


I2C_ACK_GENERAL_CALL_REG

I2C ACK General Call Register
address_offset : 0x98 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_ACK_GENERAL_CALL_REG I2C_ACK_GENERAL_CALL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACK_GEN_CALL

ACK_GEN_CALL : ACK General Call. When set to 1, I2C Ctrl responds with a ACK (by asserting ic_data_oe) when it receives a General Call. When set to 0, the controller does not generate General Call interrupts.
bits : 0 - 0 (1 bit)
access : read-write


I2C_ENABLE_STATUS_REG

I2C Enable Status Register
address_offset : 0x9C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_ENABLE_STATUS_REG I2C_ENABLE_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_EN SLV_DISABLED_WHILE_BUSY SLV_RX_DATA_LOST

IC_EN : ic_en Status. This bit always reflects the value driven on the output port ic_en. When read as 1, the controller is deemed to be in an enabled state. When read as 0, the controller is deemed completely inactive. NOTE: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
bits : 0 - 0 (1 bit)
access : read-only

SLV_DISABLED_WHILE_BUSY : Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while: (a) I2C Ctrl is receiving the address byte of the Slave-Transmitter operation from a remote master OR, (b) address and data bytes of the Slave-Receiver operation from a remote master. When read as 1, the controller is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in I2C Ctrl (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit will also be set to 1. When read as 0, the controller is deemed to have been disabled when there is master activity, or when the I2C bus is idle. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
bits : 1 - 2 (2 bit)
access : read-only

SLV_RX_DATA_LOST : Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting of IC_ENABLE from 1 to 0. When read as 1, the controller is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK. NOTE: If the remote I2C master terminates the transfer with a STOP condition before the controller has a chance to NACK a transfer, and IC_ENABLE has been set to 0, then this bit is also set to 1. When read as 0, the controller is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer. NOTE: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
bits : 2 - 4 (3 bit)
access : read-only


I2C_IC_FS_SPKLEN_REG

I2C SS and FS spike suppression limit Size
address_offset : 0xA0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

I2C_IC_FS_SPKLEN_REG I2C_IC_FS_SPKLEN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IC_FS_SPKLEN

IC_FS_SPKLEN : This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1 hardware prevents values less than this being written, and if attempted results in 1 being set.
bits : 0 - 7 (8 bit)
access : read-write



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