\n
address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection :
GPIO interrupt selection for GPIO_IRQ0
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_IRQ0_SEL : input selection that can generate a GPIO interrupt 0: no input selected 1: P0[0] is selected 2: P0[1] is selected 3: P0[2] is selected 4: P0[3] is selected 5: P0[4] is selected 6: P0[5] is selected 7: P0[6] is selected 8: P0[7] is selected 9: P1[0] is selected 10: P1[1] is selected 11: P1[2] is selected 12: P1[3] is selected 13: P1[4] is selected 14: P1[5] is selected 15: P2[0] is selected 16: P2[1] is selected 17: P2[2] is selected 18: P2[3] is selected 19: P2[4] is selected 20: P2[5] is selected 21: P2[6] is selected 22: P2[7] is selected 23: P2[8] is selected 24: P2[9] is selected 25: P3[0] is selected 26: P3[1] is selected 27: P3[2] is selected 28: P3[3] is selected 29: P3[4] is selected 30: P3[5] is selected 31: P3[6] is selected 32: P3[7] is selected all others: no input selected
bits : 0 - 5 (6 bit)
access : read-write
high or low level select for GPIO interrupts
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INPUT_LEVEL0 : 0 = selected input will generate GPIO IRQ0 if that input is high. 1 = selected input will generate GPIO IRQ0 if that input is low.
bits : 0 - 0 (1 bit)
access : read-write
INPUT_LEVEL1 : see INPUT_LEVEL0, but for GPIO IRQ1
bits : 1 - 2 (2 bit)
access : read-write
INPUT_LEVEL2 : see INPUT_LEVEL0, but for GPIO IRQ2
bits : 2 - 4 (3 bit)
access : read-write
INPUT_LEVEL3 : see INPUT_LEVEL0, but for GPIO IRQ3
bits : 3 - 6 (4 bit)
access : read-write
INPUT_LEVEL4 : see INPUT_LEVEL0, but for GPIO IRQ4
bits : 4 - 8 (5 bit)
access : read-write
EDGE_LEVELn0 : 0: do not wait for key release after interrupt was reset for GPIO IRQ0, so a new interrupt can be initiated immediately 1: wait for key release after interrupt was reset for IRQ0
bits : 8 - 16 (9 bit)
access : read-write
EDGE_LEVELn1 : see EDGE_LEVELn0, but for GPIO IRQ1
bits : 9 - 18 (10 bit)
access : read-write
EDGE_LEVELn2 : see EDGE_LEVELn0, but for GPIO IRQ2
bits : 10 - 20 (11 bit)
access : read-write
EDGE_LEVELn3 : see EDGE_LEVELn0, but for GPIO IRQ3
bits : 11 - 22 (12 bit)
access : read-write
EDGE_LEVELn4 : see EDGE_LEVELn0, but for GPIO IRQ4
bits : 12 - 24 (13 bit)
access : read-write
GPIO interrupt selection for KBRD_IRQ for P0
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_P00_EN : enable P0[0] for the keyboard interrupt
bits : 0 - 0 (1 bit)
access : read-write
KBRD_P01_EN : enable P0[1] for the keyboard interrupt
bits : 1 - 2 (2 bit)
access : read-write
KBRD_P02_EN : enable P0[2] for the keyboard interrupt
bits : 2 - 4 (3 bit)
access : read-write
KBRD_P03_EN : enable P0[3] for the keyboard interrupt
bits : 3 - 6 (4 bit)
access : read-write
KBRD_P04_EN : enable P0[4] for the keyboard interrupt
bits : 4 - 8 (5 bit)
access : read-write
KBRD_P05_EN : enable P0[5] for the keyboard interrupt
bits : 5 - 10 (6 bit)
access : read-write
KBRD_P06_EN : enable P0[6] for the keyboard interrupt
bits : 6 - 12 (7 bit)
access : read-write
KBRD_P07_EN : enable P0[7] for the keyboard interrupt
bits : 7 - 14 (8 bit)
access : read-write
KEY_REPEAT : While key is pressed, automatically generate repeating KEYB_INT after specified time unequal to 0. Repeat time: N*1 ms. N =1..63, N=0 disables the timer.
bits : 8 - 21 (14 bit)
access : read-write
KBRD_LEVEL : 0 = enabled input will generate KBRD IRQ if that input is high. 1 = enabled input will generate KBRD IRQ if that input is low.
bits : 14 - 28 (15 bit)
access : read-write
KBRD_REL : 0 = No interrupt on key release 1 = Interrupt also on key release (also debouncing if enabled)
bits : 15 - 30 (16 bit)
access : read-write
GPIO interrupt selection for KBRD_IRQ for P1 and P2
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_P20_EN : enable P2[0] for the keyboard interrupt
bits : 0 - 0 (1 bit)
access : read-write
KBRD_P21_EN : enable P2[1] for the keyboard interrupt
bits : 1 - 2 (2 bit)
access : read-write
KBRD_P22_EN : enable P2[2] for the keyboard interrupt
bits : 2 - 4 (3 bit)
access : read-write
KBRD_P23_EN : enable P2[3] for the keyboard interrupt
bits : 3 - 6 (4 bit)
access : read-write
KBRD_P24_EN : enable P2[4] for the keyboard interrupt
bits : 4 - 8 (5 bit)
access : read-write
KBRD_P25_EN : enable P2[5] for the keyboard interrupt
bits : 5 - 10 (6 bit)
access : read-write
KBRD_P26_EN : enable P2[6] for the keyboard interrupt
bits : 6 - 12 (7 bit)
access : read-write
KBRD_P27_EN : enable P2[7] for the keyboard interrupt
bits : 7 - 14 (8 bit)
access : read-write
KBRD_P28_EN : enable P2[8] for the keyboard interrupt
bits : 8 - 16 (9 bit)
access : read-write
KBRD_P29_EN : enable P2[9] for the keyboard interrupt
bits : 9 - 18 (10 bit)
access : read-write
KBRD_P10_EN : enable P1[0] for the keyboard interrupt
bits : 10 - 20 (11 bit)
access : read-write
KBRD_P11_EN : enable P1[1] for the keyboard interrupt
bits : 11 - 22 (12 bit)
access : read-write
KBRD_P12_EN : enable P1[2] for the keyboard interrupt
bits : 12 - 24 (13 bit)
access : read-write
KBRD_P13_EN : enable P1[3] for the keyboard interrupt
bits : 13 - 26 (14 bit)
access : read-write
KBRD_P14_EN : enable P1[4] for the keyboard interrupt
bits : 14 - 28 (15 bit)
access : read-write
KBRD_P15_EN : enable P1[5] for the keyboard interrupt
bits : 15 - 30 (16 bit)
access : read-write
GPIO interrupt selection for KBRD_IRQ for P3
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_P30_EN : enable P3[0] for the keyboard interrupt
bits : 0 - 0 (1 bit)
access : read-write
KBRD_P31_EN : enable P3[1] for the keyboard interrupt
bits : 1 - 2 (2 bit)
access : read-write
KBRD_P32_EN : enable P3[2] for the keyboard interrupt
bits : 2 - 4 (3 bit)
access : read-write
KBRD_P33_EN : enable P3[3] for the keyboard interrupt
bits : 3 - 6 (4 bit)
access : read-write
KBRD_P34_EN : enable P3[4] for the keyboard interrupt
bits : 4 - 8 (5 bit)
access : read-write
KBRD_P35_EN : enable P3[5] for the keyboard interrupt
bits : 5 - 10 (6 bit)
access : read-write
KBRD_P36_EN : enable P3[6] for the keyboard interrupt
bits : 6 - 12 (7 bit)
access : read-write
KBRD_P37_EN : enable P3[7] for the keyboard interrupt
bits : 7 - 14 (8 bit)
access : read-write
GPIO interrupt selection for GPIO_IRQ1
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_IRQ1_SEL : see KBRD_IRQ0_SEL
bits : 0 - 5 (6 bit)
access : read-write
GPIO interrupt selection for GPIO_IRQ2
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_IRQ2_SEL : see KBRD_IRQ0_SEL
bits : 0 - 5 (6 bit)
access : read-write
GPIO interrupt selection for GPIO_IRQ3
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_IRQ3_SEL : see KBRD_IRQ0_SEL
bits : 0 - 5 (6 bit)
access : read-write
GPIO interrupt selection for GPIO_IRQ4
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
KBRD_IRQ4_SEL : see KBRD_IRQ0_SEL
bits : 0 - 5 (6 bit)
access : read-write
debounce counter value for GPIO inputs
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DEB_VALUE : Keyboard debounce time if enabled. Generate KEYB_INT after specified time. Debounce time: N*1 ms. N =0..63
bits : 0 - 5 (6 bit)
access : read-write
DEB_ENABLE0 : enables the debounce counter for GPIO IRQ0
bits : 8 - 16 (9 bit)
access : read-write
DEB_ENABLE1 : enables the debounce counter for GPIO IRQ1
bits : 9 - 18 (10 bit)
access : read-write
DEB_ENABLE2 : enables the debounce counter for GPIO IRQ2
bits : 10 - 20 (11 bit)
access : read-write
DEB_ENABLE3 : enables the debounce counter for GPIO IRQ3
bits : 11 - 22 (12 bit)
access : read-write
DEB_ENABLE4 : enables the debounce counter for GPIO IRQ4
bits : 12 - 24 (13 bit)
access : read-write
DEB_ENABLE_KBRD : enables the debounce counter for the KBRD interface
bits : 13 - 26 (14 bit)
access : read-write
GPIO interrupt reset register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESET_GPIO0_IRQ : writing a 1 to this bit will reset the GPIO0 IRQ. Reading returns 0.
bits : 0 - 0 (1 bit)
access : write-only
RESET_GPIO1_IRQ : writing a 1 to this bit will reset the GPIO1 IRQ. Reading returns 0.
bits : 1 - 2 (2 bit)
access : write-only
RESET_GPIO2_IRQ : writing a 1 to this bit will reset the GPIO2 IRQ. Reading returns 0.
bits : 2 - 4 (3 bit)
access : write-only
RESET_GPIO3_IRQ : writing a 1 to this bit will reset the GPIO3 IRQ. Reading returns 0.
bits : 3 - 6 (4 bit)
access : write-only
RESET_GPIO4_IRQ : writing a 1 to this bit will reset the GPIO4 IRQ. Reading returns 0.
bits : 4 - 8 (5 bit)
access : write-only
RESET_KBRD_IRQ : writing a 1 to this bit will reset the KBRD IRQ. Reading returns 0.
bits : 5 - 10 (6 bit)
access : write-only
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