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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :

Registers

QDEC_CTRL_REG

QDEC_XCNT_REG

QDEC_YCNT_REG

QDEC_CLOCKDIV_REG

QDEC_CTRL2_REG

QDEC_ZCNT_REG


QDEC_CTRL_REG

Quad Decoder control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_CTRL_REG QDEC_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 QD_IRQ_MASK QD_IRQ_CLR QD_IRQ_STATUS QD_IRQ_THRES

QD_IRQ_MASK : 0: interrupt is masked 1: interrupt is enabled
bits : 0 - 0 (1 bit)
access : read-write

QD_IRQ_CLR : Writing 1 to this bit clears the interrupt. This bit is autocleared
bits : 1 - 2 (2 bit)
access : read-write

QD_IRQ_STATUS : Interrupt Status. If 1 an interrupt has occured.
bits : 2 - 4 (3 bit)
access : read-only

QD_IRQ_THRES : The number of events on either counter (X or Y) that need to be reached before an interrupt is generated. If 0 is written, then threshold is considered to be 1.
bits : 3 - 12 (10 bit)
access : read-write


QDEC_XCNT_REG

Counter value of the X Axis
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_XCNT_REG QDEC_XCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X_counter

X_counter : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only


QDEC_YCNT_REG

Counter value of the Y Axis
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_YCNT_REG QDEC_YCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Y_counter

Y_counter : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only


QDEC_CLOCKDIV_REG

Clock divider register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_CLOCKDIV_REG QDEC_CLOCKDIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 clock_divider

clock_divider : Contains the number of the input clock cycles minus one, that are required to generate one logic clock cycle.
bits : 0 - 9 (10 bit)
access : read-write


QDEC_CTRL2_REG

Quad Decoder control register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_CTRL2_REG QDEC_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHX_PORT_SEL CHY_PORT_SEL CHZ_PORT_SEL

CHX_PORT_SEL : Defines which GPIOs are mapped on Channel X 0: none 1: P0[0] -> CHX_A, P0[1] -> CHX_B 2: P0[2] -> CHX_A, P0[3] -> CHX_B 3: P0[4] -> CHX_A, P0[5] -> CHX_B 4: P0[6] -> CHX_A, P0[7] -> CHX_B 5: P1[0] -> CHX_A, P1[1] -> CHX_B 6: P1[2] -> CHX_A, P1[3] -> CHX_B 7: P2[3] -> CHX_A, P2[4] -> CHX_B 8: P2[5] -> CHX_A, P2[6] -> CHX_B 9: P2[7] -> CHX_A, P2[8] -> CHX_B 10: P2[9] -> CHX_A, P2[0] -> CHX_B 11..15: None
bits : 0 - 3 (4 bit)
access : read-write

CHY_PORT_SEL : Defines which GPIOs are mapped on Channel Y 0: none 1: P0[0] -> CHY_A, P0[1] -> CHY_B 2: P0[2] -> CHY_A, P0[3] -> CHY_B 3: P0[4] -> CHY_A, P0[5] -> CHY_B 4: P0[6] -> CHY_A, P0[7] -> CHY_B 5: P1[0] -> CHY_A, P1[1] -> CHY_B 6: P1[2] -> CHY_A, P1[3] -> CHY_B 7: P2[3] -> CHY_A, P2[4] -> CHY_B 8: P2[5] -> CHY_A, P2[6] -> CHY_B 9: P2[7] -> CHY_A, P2[8] -> CHY_B 10: P2[9] -> CHY_A, P2[0] -> CHY_B 11..15: None
bits : 4 - 11 (8 bit)
access : read-write

CHZ_PORT_SEL : Defines which GPIOs are mapped on Channel Z 0: none 1: P0[0] -> CHZ_A, P0[1] -> CHZ_B 2: P0[2] -> CHZ_A, P0[3] -> CHZ_B 3: P0[4] -> CHZ_A, P0[5] -> CHZ_B 4: P0[6] -> CHZ_A, P0[7] -> CHZ_B 5: P1[0] -> CHZ_A, P1[1] -> CHZ_B 6: P1[2] -> CHZ_A, P1[3] -> CHZ_B 7: P2[3] -> CHZ_A, P2[4] -> CHZ_B 8: P2[5] -> CHZ_A, P2[6] -> CHZ_B 9: P2[7] -> CHZ_A, P2[8] -> CHZ_B 10: P2[9] -> CHZ_A, P2[0] -> CHZ_B 11..15: None
bits : 8 - 19 (12 bit)
access : read-write


QDEC_ZCNT_REG

Z_counter
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QDEC_ZCNT_REG QDEC_ZCNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Z_counter

Z_counter : Contains a signed value of the events. Zero when channel is disabled
bits : 0 - 15 (16 bit)
access : read-only



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