RF_BMCW_REG

RF_OVERRULE_REG

RF_CAL_CTRL_REG

RF_REF_OSC_REG

RF_IRQ_CTRL_REG

RF_IFF_RESULT_REG

RF_ADCI_DC_OFFSET_REG

RF_ADCQ_DC_OFFSET_REG

RF_DC_OFFSET_RESULT_REG

RF_SYNTH_RESULT_REG

RF_SYNTH_RESULT2_REG

RF_SYNTH_RESULT3_REG

RF_CALSTATE_REG

RF_ENABLE_CONFIG1_REG

RF_ENABLE_CONFIG2_REG

RF_ENABLE_CONFIG3_REG

RF_ENABLE_CONFIG4_REG

RF_ENABLE_CONFIG5_REG

RF_ENABLE_CONFIG6_REG

RF_ENABLE_CONFIG7_REG

RF_ENABLE_CONFIG8_REG

RF_ENABLE_CONFIG9_REG

RF_ENABLE_CONFIG10_REG

RF_ENABLE_CONFIG11_REG

RF_ENABLE_CONFIG12_REG

RF_ENABLE_CONFIG13_REG

RF_ENABLE_CONFIG14_REG

RF_ENABLE_CONFIG15_REG

RF_ENABLE_CONFIG16_REG

RF_ENABLE_CONFIG17_REG

RF_ENABLE_CONFIG18_REG

RF_ENABLE_CONFIG19_REG

RF_ENABLE_CONFIG20_REG

RF_ENABLE_CONFIG21_REG

RF_ENABLE_CONFIG22_REG

RF_ENABLE_CONFIG23_REG

RF_CNTRL_TIMER_1_REG

RF_CNTRL_TIMER_2_REG

RF_CNTRL_TIMER_3_REG

RF_CNTRL_TIMER_4_REG

RF_CNTRL_TIMER_5_REG

RF_CNTRL_TIMER_6_REG

RF_CNTRL_TIMER_7_REG

RF_CNTRL_TIMER_8_REG

RF_CNTRL_TIMER_9_REG

RF_CNTRL_TIMER_10_REG

RF_CNTRL_TIMER_11_REG

RF_CNTRL_TIMER_12_REG

RF_CNTRL_TIMER_13_REG

RF_CNTRL_TIMER_14_REG

RF_CALCAP1_REG

BIAS_CTRL1_REG

RF_SPARE1_REG

RF_CALCAP2_REG

RF_SCAN_FEEDBACK_REG

RF_MIXER_CTRL1_REG

RF_MIXER_CTRL2_REG

RF_IFF_CTRL1_REG

RF_ADC_CTRL1_REG

RF_ADC_CTRL2_REG

RF_ADC_CTRL3_REG

RF_DEM_CTRL_REG

RF_AGC_LUT_01_REG

RF_AGC_LUT_23_REG

RF_AGC_LUT_45_REG

RF_AGC_LUT_67_REG

RF_AGC_LUT_89_REG

RF_AGC_CTRL1_REG

RF_AGC_CTRL2_REG

RF_AFC_CTRL_REG

RF_DC_OFFSET_CTRL1_REG

RF_DC_OFFSET_CTRL2_REG

RF_DC_OFFSET_CTRL3_REG

RF_DC_OFFSET_CTRL4_REG

RF_RADIG_SPARE_REG

RF_AGC_RESULT_REG

RF_RSSI_RESULT_REG

RF_PA_CTRL_REG

RF_SYNTH_CTRL1_REG

RF_SYNTH_CTRL2_REG

RF_SYNTH_CTRL3_REG

RF_VCOCAL_CTRL_REG

RF_MGAIN_CTRL_REG

RF_MGAIN_CTRL2_REG

RF_MGC_CTRL_REG

RF_VCOVAR_CTRL_REG

RF_VCO_CALCAP_BIT14_REG

RF_VCO_CALCAP_BIT15_REG

RF_PFD_CTRL_REG

RF_CP_CTRL_REG

RF_LF_RES_CTRL_REG

RF_LF_CTRL_REG

RF_TDC_CTRL_REG

CN_WR : [7:6] = offset to RFCAL_CAP_WR, coarse calibraton LUT [5:0] = channel number
bits : 0 - 7 (8 bit)
access : read-write

CN_SEL : Select between: 1 = use CN_WR as channel number 0 = use BLE Frequency word (normal function).
bits : 8 - 16 (9 bit)
access : read-write

TX_DIS_WR : Disable tx_en
bits : 0 - 0 (1 bit)
access : read-write

TX_EN_WR : Enable tx_en
bits : 1 - 2 (2 bit)
access : read-write

RX_DIS_WR : Disable rx_en
bits : 2 - 4 (3 bit)
access : read-write

RX_EN_WR : Enable rx_en
bits : 3 - 6 (4 bit)
access : read-write

SO_CAL : Start of calibration trigger.Writing a 1 starts calibration.1Reading returns the calibration status (1 = busy calibrating).
bits : 0 - 0 (1 bit)
access : read-write

EO_CAL : End of calibration trigger. Reading returns the eo_cal status signal which can be cleared by writing to RF_IRQ_CTRL_REG.EO_CAL_CLEAR
bits : 1 - 2 (2 bit)
access : read-only

MGAIN_CAL_DIS : Do not calibrate the VCO and Modulation Gain during Cal cycle
bits : 2 - 4 (3 bit)
access : read-write

IFF_CAL_DIS : Do not calibrate the IFF center frequency during Cal cycle
bits : 3 - 6 (4 bit)
access : read-write

DC_OFFSET_CAL_DIS : Do not calibrate the VGA2 Offset during Cal cycle
bits : 4 - 8 (5 bit)
access : read-write

VCO_CAL_DIS : Do not calibrate the VCO during Cal cycle
bits : 5 - 10 (6 bit)
access : read-write

CNT_RO : number of reference oscillator periods that need to be counted
bits : 0 - 5 (6 bit)
access : read-write

CNT_CLK : number of clock pulses corresponding to the value of CNT_RO
bits : 6 - 20 (15 bit)
access : read-write

EO_CAL_CLEAR : Writing any value to this bit clears eo_cal interrupt.
bits : 0 - 0 (1 bit)
access : read-only

IF_CAL_CAP_RD : IF calibration result capacitance.
bits : 0 - 4 (5 bit)
access : read-only

ADC_OFFP_I_RD : DC offset compensation in the I path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
bits : 0 - 7 (8 bit)
access : read-only

ADC_OFFN_I_RD : DC offset compensation in the I path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
bits : 8 - 23 (16 bit)
access : read-only

ADC_OFFP_Q_RD : DC offset compensation in the Q path (non-inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
bits : 0 - 7 (8 bit)
access : read-only

ADC_OFFN_Q_RD : DC offset compensation in the Q path (inverting input) in sign-magnitude notarion (i.e. -31 : 1 : 31 mV)
bits : 8 - 23 (16 bit)
access : read-only

DCOFFSET_I_RD : DC offset compensation value in I channel valid when DCOFFSET_SEL = 0.
bits : 0 - 7 (8 bit)
access : read-only

DCOFFSET_Q_RD : DC offset compensation value in Q channel valid when DCOFFSET_SEL = 0
bits : 8 - 23 (16 bit)
access : read-only

GAUSS_GAIN_CAL_RD : Result of the modulation gain calibration (Retained)
bits : 0 - 7 (8 bit)
access : read-only

VCO_FREQTRIM_RD : Result of the VCO calibration (Not Retained)
bits : 8 - 19 (12 bit)
access : read-only

GAUSS_GAIN_RD : Modulation gain after trimming (Not Retained)
bits : 0 - 7 (8 bit)
access : read-only

CN_CAL_RD : Result of the modulation gain calibration (Retained)
bits : 8 - 22 (15 bit)
access : read-only

MDSTATE_RD : Content of the calibration counter
bits : 0 - 15 (16 bit)
access : read-only

CALSTATE : Value of the calstate state machine
bits : 0 - 3 (4 bit)
access : read-only

lna_core_en : Timing configuration for enable of the lna core
bits : 0 - 7 (8 bit)
access : read-write

lna_ldo_en : Timing configuration for enable of the lna ldo
bits : 8 - 23 (16 bit)
access : read-write

mix_ldo_en : Timing configuration for enable of the mix ldo
bits : 0 - 7 (8 bit)
access : read-write

lna_cgm_en : Timing configuration for enable of the lna cgm
bits : 8 - 23 (16 bit)
access : read-write

ifadc_ldo_en : Timing configuration for enable of the ifadc ldo
bits : 0 - 7 (8 bit)
access : read-write

iff_ldo_en : Timing configuration for enable of the iff ldo
bits : 8 - 23 (16 bit)
access : read-write

md_ldo_en : Timing configuration for enable of the md ldo
bits : 0 - 7 (8 bit)
access : read-write

vco_ldo_en : Timing configuration for enable of the vco ldo
bits : 8 - 23 (16 bit)
access : read-write

pa_ldo_en : Timing configuration for enable of the pa ldo
bits : 0 - 7 (8 bit)
access : read-write

pfd_ldo_en : Timing configuration for enable of the pfd ldo
bits : 8 - 23 (16 bit)
access : read-write

vco_bias_en : Timing configuration for the VCO bias
bits : 0 - 7 (8 bit)
access : read-write

cp_switch_en : Timing configuration for the dynamic CP current switching
bits : 8 - 23 (16 bit)
access : read-write

lna_ldo_zero : autozero control signal of the lna ldo
bits : 0 - 7 (8 bit)
access : read-write

cp_bias_en : Timing configuration for enable of the CP bias
bits : 8 - 23 (16 bit)
access : read-write

pa_en : Timing configuration for enable of the PA
bits : 0 - 7 (8 bit)
access : read-write

pa_ramp_en : Timing configuration for enable of the PA ramp
bits : 8 - 23 (16 bit)
access : read-write

iff_en : Timing configuration for enable of the iff
bits : 0 - 7 (8 bit)
access : read-write

mix_en : Timing configuration for enable of the mixer
bits : 8 - 23 (16 bit)
access : read-write

vco_en : Timing configuration for enable of the VCO
bits : 0 - 7 (8 bit)
access : read-write

adc_en : Timing configuration for enable of the ADC
bits : 8 - 23 (16 bit)
access : read-write

cp_en : Timing configuration for enable of CP
bits : 0 - 7 (8 bit)
access : read-write

md_lobuf_en : Timing configuration for enable of main divider of the LO buffer
bits : 8 - 23 (16 bit)
access : read-write

gauss_en : Timing configuration for the gauss module
bits : 0 - 7 (8 bit)
access : read-write

pfd_en : Timing configuration for the phase frequency detector
bits : 8 - 23 (16 bit)
access : read-write

lobuf_pa_en : Timing configuration for the PA lobuffer
bits : 0 - 7 (8 bit)
access : read-write

rfio_en : Timing configuration for the rfio
bits : 8 - 23 (16 bit)
access : read-write

div2_en : Timing configuration for the 2 divider
bits : 0 - 7 (8 bit)
access : read-write

lobuf_rxiq_en : Timing configuration for the rxi lobuffer
bits : 8 - 23 (16 bit)
access : read-write

vco_bias_sh_open_en : Timing configuration for the VCO bias S/H switch
bits : 0 - 7 (8 bit)
access : read-write

cp_bias_sh_open : Timing configuration for the CP bias S/H switch
bits : 8 - 23 (16 bit)
access : read-write

gauss_bias_sh_open_en : Timing configuration for gauss bias S/H switch
bits : 0 - 7 (8 bit)
access : read-write

iff_bias_sh_open_en : Timing configuration for iffmix bias S/H switch
bits : 8 - 23 (16 bit)
access : read-write

plldig_en : Timing configuration for the plldig
bits : 0 - 7 (8 bit)
access : read-write

mix_bias_sh_open_en : Timing configuration for pa bias S/H switch
bits : 8 - 23 (16 bit)
access : read-write

dem_en : Timing configuration for demodulator
bits : 0 - 7 (8 bit)
access : read-write

pllclosed_en : Timing configuration for pllclosed
bits : 8 - 23 (16 bit)
access : read-write

cal_en : Timing configuration for calibration slot
bits : 0 - 7 (8 bit)
access : read-write

ldo_zero_en : Timing configuration for radio LDO auto zero enable
bits : 8 - 23 (16 bit)
access : read-write

ldo_rfio_en : Timing configuration for RFIO LDO
bits : 0 - 7 (8 bit)
access : read-write

tdc_en : Timing configuration for time to digital converter
bits : 8 - 23 (16 bit)
access : read-write

rfio_bias_sh_open : Timing configuration for S/H switch of bias block for RFIO/RFPA
bits : 0 - 7 (8 bit)
access : read-write

rfio_bias_en : Timing configuration for bias block for RFIO and RFPA
bits : 8 - 23 (16 bit)
access : read-write

adc_clk_en : Timing configuration for the enable of the ADC clock
bits : 0 - 7 (8 bit)
access : read-write

ldo_radio_en : Timing configuration for LDO for the radio IO buffer
bits : 8 - 23 (16 bit)
access : read-write

spare_en_3 : Timing configuration for spare_en_3
bits : 0 - 7 (8 bit)
access : read-write

tr_pwm_off_en : Timing configuration for tr_pwm_off_en
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/so_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/so_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/so_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_tx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_tx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_tx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_tx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

SET_OFFSET : Offset w.r.t. start switch instant so_rx/eo_tx.
bits : 0 - 7 (8 bit)
access : read-write

RESET_OFFSET : Offset w.r.t. end switch instant eo_rx/eo_tx.
bits : 8 - 23 (16 bit)
access : read-write

VCO_CALCAP_LOW : Lowest 16 bits of vco_calcap
bits : 0 - 15 (16 bit)
access : read-only

MIX_BIAS_SET : Tuning of the mixer bias current
bits : 0 - 3 (4 bit)
access : read-write

CP_BIAS_SET : Tuning of the charge pump bias current
bits : 4 - 11 (8 bit)
access : read-write

VCO_BIAS_SET : Tuning of the VCO bias current
bits : 8 - 19 (12 bit)
access : read-write

IFF_BIAS_SET : Tuning of the IF filter bias current
bits : 12 - 27 (16 bit)
access : read-write

IFF_REAL_MODE : Choose the transfer function mode of the IFF 0: Normal operation (complex) 1: Test mode (real, approx. 16 dB less gain at 1 MHz than in complex mode)
bits : 0 - 0 (1 bit)
access : read-write

RF_SPARE1 : Spare bits for radio
bits : 1 - 16 (16 bit)
access : read-write

VCO_CALCAP_HIGH : Highest 2 bits of vco_calcap.
bits : 0 - 1 (2 bit)
access : read-only

LF_RES : Lf_res value during scan.
bits : 0 - 3 (4 bit)
access : read-only

CP_CUR : Cp_cur value during scan.
bits : 4 - 11 (8 bit)
access : read-only

MIX_TRIM_GMBIAS : Trim the Mixer bias resistor for optimum transcunductance 0: Minimum transconductance 8: Nominal transconductance F: Maximal transconductance
bits : 0 - 3 (4 bit)
access : read-write

MIX_TRIM_IBIAS : Trim the bias current of the TIA 0: Minimum bias current 8: Nominal bias current F: Maximal bias current
bits : 4 - 11 (8 bit)
access : read-write

MIX_TRIM_VCM : Trim the common mode voltage at the input of the TIA 0: Minimum voltage 8: Nominal voltage F: Maximal voltage
bits : 8 - 19 (12 bit)
access : read-write

MIX_SPARE : Spare registers for mixer control
bits : 12 - 27 (16 bit)
access : read-write

MIX_CAL_CAP_WR : External value for calibration of mixer pole capacitance
bits : 0 - 4 (5 bit)
access : read-write

MIX_CAL_CAP_SEL : '0': Normal operation: use IF_CAL_CAP_RD (as determined by IF calibration) for the loop filter capacitance '1': use the value written to MIX_CAL_CAP_WR
bits : 5 - 10 (6 bit)
access : read-write

IF_CAL_CAP_WR : External value for IF calibration capacitance
bits : 0 - 4 (5 bit)
access : read-write

IF_CAL_CAP_SEL : '0': use value as determined by IF calibration for IF filter '1': use the value written to IF_CAL_CAP for IF filter.
bits : 5 - 10 (6 bit)
access : read-write

IF_MUTE : '0': normal operation '1': Mute IFF by short circuit of VGA1 input. Note: set TGATE_MIXER_IF to '0' for isolation from the IRM
bits : 6 - 12 (7 bit)
access : read-write

RO_TO_PINS : '0': normal operation '1': Enable reference oscillator.
bits : 7 - 14 (8 bit)
access : read-write

IFF_DCOC_DAC_DIS : Disable the DC offset current DAC
bits : 8 - 16 (9 bit)
access : read-write

ADC_DC_OFFSET_SEL : 0: Normal operation (i.e. Use automatically calibrated value) 1: Use ADC_OFFx_y_WR to set the DC offset compensation values in the ADC (x = N or P, y = I or Q
bits : 0 - 0 (1 bit)
access : read-write

ADC_MUTE : 0: Normal operation 1: Short the inputs of the ADC (used for DC offset cal)
bits : 13 - 26 (14 bit)
access : read-write

ADC_SIGN : Change polarity of ADC input.
bits : 14 - 28 (15 bit)
access : read-write

ADC_OFFP_I_WR : External value for the DC offset compensation in the I path positive side.
bits : 0 - 7 (8 bit)
access : read-write

ADC_OFFN_I_WR : External value for the DC offset compensation in the I path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR.
bits : 8 - 23 (16 bit)
access : read-write

ADC_OFFP_Q_WR : External value for the DC offset compensation in the Q path positive side.
bits : 0 - 7 (8 bit)
access : read-write

ADC_OFFN_Q_WR : External value for the DC offset compensation in the Q path negative side. With common mode input voltage at Vpwrp/2, this value is 512-ADC_OFFP_Q_WR.
bits : 8 - 23 (16 bit)
access : read-write

RXDATA_INV : '0': Normal operation '1': Invert the polarity of the received bits
bits : 0 - 0 (1 bit)
access : read-write

DEM_HSI_POL : Invert 'frequency' polarity of the demodulator
bits : 1 - 2 (2 bit)
access : read-write

MATCH0101_TH : Threshold for the 0101 pattern matching
bits : 2 - 7 (6 bit)
access : read-write

EQUAL_EN : Enable the equalizer in the demodulator
bits : 6 - 12 (7 bit)
access : read-write

VGA2_GAIN0 : VGA2 gain setting while in AGC setting 0
bits : 0 - 2 (3 bit)
access : read-write

VGA1_GAIN0 : VGA1 gain setting while in AGC setting 0
bits : 3 - 8 (6 bit)
access : read-write

LNA_GAIN0 : LNA gain setting while in AGC setting 0
bits : 6 - 13 (8 bit)
access : read-write

VGA2_GAIN1 : VGA2 gain setting while in AGC setting 1
bits : 8 - 18 (11 bit)
access : read-write

VGA1_GAIN1 : VGA1 gain setting while in AGC setting 1
bits : 11 - 24 (14 bit)
access : read-write

LNA_GAIN1 : LNA gain setting while in AGC setting 0
bits : 14 - 29 (16 bit)
access : read-write

VGA2_GAIN2 : VGA2 gain setting while in AGC setting 2
bits : 0 - 2 (3 bit)
access : read-write

VGA1_GAIN2 : VGA1 gain setting while in AGC setting 2
bits : 3 - 8 (6 bit)
access : read-write

VGA2_GAIN3 : VGA2 gain setting while in AGC setting 3
bits : 8 - 18 (11 bit)
access : read-write

VGA1_GAIN3 : VGA1 gain setting while in AGC setting 3
bits : 11 - 24 (14 bit)
access : read-write

VGA2_GAIN4 : VGA2 gain setting while in AGC setting 4
bits : 0 - 2 (3 bit)
access : read-write

VGA1_GAIN4 : VGA1 gain setting while in AGC setting 4
bits : 3 - 8 (6 bit)
access : read-write

LNA_GAIN4 : LNA gain setting while in AGC setting 4
bits : 6 - 13 (8 bit)
access : read-write

VGA2_GAIN5 : VGA2 gain setting while in AGC setting 5
bits : 8 - 18 (11 bit)
access : read-write

VGA1_GAIN5 : VGA1 gain setting while in AGC setting 5
bits : 11 - 24 (14 bit)
access : read-write

LNA_GAIN5 : LNA gain setting while in AGC setting 5
bits : 14 - 29 (16 bit)
access : read-write

VGA2_GAIN6 : VGA2 gain setting while in AGC setting 6
bits : 0 - 2 (3 bit)
access : read-write

VGA1_GAIN6 : VGA1 gain setting while in AGC setting 6
bits : 3 - 8 (6 bit)
access : read-write

LNA_GAIN6 : LNA gain setting while in AGC setting 6
bits : 6 - 13 (8 bit)
access : read-write

VGA2_GAIN7 : VGA2 gain setting while in AGC setting 7
bits : 8 - 18 (11 bit)
access : read-write

VGA1_GAIN7 : VGA1 gain setting while in AGC setting 7
bits : 11 - 24 (14 bit)
access : read-write

LNA_GAIN7 : LNA gain setting while in AGC setting 7
bits : 14 - 29 (16 bit)
access : read-write

VGA2_GAIN8 : VGA2 gain setting while in AGC setting 8
bits : 0 - 2 (3 bit)
access : read-write

VGA1_GAIN8 : VGA1 gain setting while in AGC setting 8
bits : 3 - 8 (6 bit)
access : read-write

LNA_GAIN8 : LNA gain setting while in AGC setting 8
bits : 6 - 13 (8 bit)
access : read-write

VGA2_GAIN9 : VGA2 gain setting while in AGC setting 9
bits : 8 - 18 (11 bit)
access : read-write

VGA1_GAIN9 : VGA1 gain setting while in AGC setting 9
bits : 11 - 24 (14 bit)
access : read-write

LNA_GAIN9 : LNA gain setting while in AGC setting 9
bits : 14 - 29 (16 bit)
access : read-write

AGC_TH_LOW : AGC hysteresis low threshold (switch down one AGC_SETTING_R step when dropping below this level)
bits : 0 - 6 (7 bit)
access : read-write

AGC_TH_HIGH : AGC hysteresis high threshold (switch up one AGC_SETTING_R step when exceeding this level)
bits : 7 - 20 (14 bit)
access : read-write

AGC_MODE : Choose the method to use for AGC evaluation Description TBD
bits : 14 - 29 (16 bit)
access : read-write

RSSI_TH : RSSI threshold for the packet detection
bits : 0 - 5 (6 bit)
access : read-write

EN_FRZ_GAIN : '0': AGC always active'1': Freeze gain after Access Address detection
bits : 6 - 12 (7 bit)
access : read-write

AGCSETTING_SEL : LNA, VGA1 and VGA2 gains '0': controlled by AGC'1': provided manually through AGCSETTING_WR
bits : 7 - 14 (8 bit)
access : read-write

AGCSETTING_WR : Fixed AGC setting to be used to configure LNA, VGA1 and VGA2 when AGCSETTING_SEL = 1 0: Highest gain as configured in RF_AGC_LUT_01_REG 1: Lower gain as configured in RF_AGC_LUT_01_REG 2: Still lower gain as configured in RF_AGC_LUT_23_REG ... 9-F: Lowest gain as configured in RF_AGC_LUT_89_REG
bits : 8 - 19 (12 bit)
access : read-write

SLOW_AGC : Enable the slow AGC mode (no consecutive AGC setting switches)
bits : 12 - 24 (13 bit)
access : read-write

AFC_MODE : Choose the method to use for AFC tracking during the slot Description TBD
bits : 0 - 3 (4 bit)
access : read-write

POLE1 : Choose the method to use for AFC tracking during the slot Description TBD
bits : 4 - 9 (6 bit)
access : read-write

POLE2 : Choose the method to use for AFC tracking during the slot Description TBD
bits : 6 - 13 (8 bit)
access : read-write

DCOFFSET_I_WR : DC offset compensation value in I channel valid when DCOFFSET_SEL = 1
bits : 0 - 7 (8 bit)
access : read-write

DCOFFSET_Q_WR : DC offset compensation value in Q channel valid when DCOFFSET_SEL = 1
bits : 8 - 23 (16 bit)
access : read-write

DCOFFSET_SEL : '0': Normal operation '1': Use the manual DC offset compensation values from RF_DC_OFFSET_CTRL1_REG
bits : 0 - 0 (1 bit)
access : read-write

DCPARCAL_EN : Enable flag for the partial DC offset calibration (executed when the demodulator is enabled).
bits : 1 - 2 (2 bit)
access : read-write

DCPOLE : Selects the pole of the digital high pass fitlers Encoding: TBD
bits : 2 - 5 (4 bit)
access : read-write

DCNSTEP : Number of the steps per.gain setting for the full or partial DC offset calibrations
bits : 4 - 10 (7 bit)
access : read-write

DCNGAIN : Number of gain settings for the full DC offset calibration
bits : 7 - 15 (9 bit)
access : read-write

DCBETA_I : Inphase feedback gain for the DC offset calibration
bits : 0 - 7 (8 bit)
access : read-write

DCBETA_Q : Quadrature feedback gain for the DC offset calibration
bits : 8 - 23 (16 bit)
access : read-write

DCAGCSETTING_FULL0 : AGC setting for last the gain step for the full DC offset calibration
bits : 0 - 3 (4 bit)
access : read-write

DCAGCSETTING_FULL1 : AGC setting for second last the gain step for the full DC offset calibration
bits : 4 - 11 (8 bit)
access : read-write

DCAGCSETTING_FULL2 : AGC setting for third last the gain step for the full DC offset calibration
bits : 8 - 19 (12 bit)
access : read-write

DCAGCSETTING_FULL3 : AGC setting for forth last the gain step for the full DC offset calibration
bits : 12 - 27 (16 bit)
access : read-write

RADIG_SPARE : Spare bits to be defined later
bits : 3 - 18 (16 bit)
access : read-write

AFC_RD : Frequency offset estimation (in 2s complement) with a resolution of approximately 5 kHz.
bits : 0 - 7 (8 bit)
access : read-only

AGCSETTING_RD : AGC setting as automatically selected in receive mode to configure LNA, VGA1 and VGA2 0: Highest gain as configured in RF_AGC_LUT_01_REG 1: Lower gain as configured in RF_AGC_LUT_01_REG 2: Still lower gain as configured in RF_AGC_LUT_23_REG ... 9-F: Lowest gain as configured in RF_AGC_LUT_89_REG
bits : 8 - 19 (12 bit)
access : read-only

RSSI_PH_RD : RSSI value measured in peak-hold mode during the preamble and Access Addres detection
bits : 0 - 5 (6 bit)
access : read-only

RSSI_AVG_RD : RSSI value measured in averaging mode in continuous RX mode (used for LNA selectivity calibration)
bits : 6 - 21 (16 bit)
access : read-only

PA_GAIN : Sets gain/DC Current setting of the differential to single ended converter '0': smallest current setting (60 uA) '1': current setting 1 (80 uA) '2': default (100 uA) '3': largest current setting (120 uA)
bits : 0 - 1 (2 bit)
access : read-write

PA_PW : Pulse width setting to control HD2 '0': not active '1': 48.8 percent duty cycle '2': 49.4 percent duty cycle '3': 49.7 percent duty cycle '4': 50 percent duty cycle (default) '5': 50.3 percent duty cycle '6': 50.6 percent duty cycle '7': 51.2 percent duty cycle
bits : 2 - 6 (5 bit)
access : read-write

PA_RAMPSPEED : Ramping speed setting of the driver stage: '0x0': slowest (1.25 uA) '0x1': 2x faster (2.5 uA) '0x2': default ramping speed '0x3': fastest
bits : 5 - 11 (7 bit)
access : read-write

LEVEL_LDO_RFPA : Control for PA supply voltage (output power)
bits : 11 - 25 (15 bit)
access : read-write

CHANNEL_ZERO : Channel 0 frequency in MHz
bits : 0 - 11 (12 bit)
access : read-write

SGN : Sign bit for the channel step 0: positive 1: negative
bits : 12 - 24 (13 bit)
access : read-write

CS : Channel Spacing 0: 1MHz 1: 2MHz
bits : 13 - 26 (14 bit)
access : read-write

PLL_HSI_POL : High Side Injection polarity 0: LO frequency is lower than the wanted RF frequency 1: LO frequency is higher than the wanted RF frequency
bits : 14 - 28 (15 bit)
access : read-write

SD_ORDER_RX : Order of the sigma-delta modulator in RX mode
bits : 0 - 1 (2 bit)
access : read-write

SD_ORDER_TX : Order of the sigma-delta modulator in TX mode
bits : 2 - 5 (4 bit)
access : read-write

MODINDEX : Modulation Index selection 0:h = 1/2 (Δf = 250 kHz) 1: h = 1/4 (Δf = 125 kHz) 2: h = 17/32 (Δf = 266 kHz) 3: h = 35/64 (Δf = 273 kHz)
bits : 4 - 9 (6 bit)
access : read-write

DELAY : Additional delay in analog signal path in RCLK cycles
bits : 6 - 13 (8 bit)
access : read-write

GAUSS_INV : Select polarity of the analog modulation path 0: Normal operation 1: Invert the signal in the analog signal path
bits : 8 - 16 (9 bit)
access : read-write

GAUSS_86 : Select the output resolution in the analog signal path 0: 8 bit resolution for the shaping signal 1: 6 bit resolution for the shaping signal
bits : 9 - 18 (10 bit)
access : read-write

TXDATA_INV : Select polarity of the modulation prior to the pulse shaping 0: Normal operation 1: Invert the modulation signal
bits : 10 - 20 (11 bit)
access : read-write

EO_PACKET_DIS : Disable the end of packet detection 0: End of packet detection enabled 1: End of pakcet detection disabled
bits : 11 - 22 (12 bit)
access : read-write

BT_SEL : 0: BT = 0.5 1: BT = 0.6
bits : 12 - 24 (13 bit)
access : read-write

MODVAL_WR : Externally provided modulation value in 2s complement Δf = 16 MHz x MODVAL_WR/16348
bits : 0 - 13 (14 bit)
access : read-write

MODVAL_SEL : 0: Normal operation 1: Use the externally provided value for the modulation
bits : 14 - 28 (15 bit)
access : read-write

VCO_FREQTRIM_WR : Externally provided VCO calibration value
bits : 0 - 3 (4 bit)
access : read-write

VCO_FREQTRIM_SEL : 0: Normal operation 1: Use VCO_FREQTRIM_WR for the VCO calibration
bits : 4 - 8 (5 bit)
access : read-write

VCOCAL_PERIOD : Length of a VCO calibration step 0: 1 us 1: 2 us 2: 3 us 3: 4 us
bits : 5 - 11 (7 bit)
access : read-write

GAUSS_GAIN_SEL : 0: Normal operation 1: Use GAUSS_GAIN_WR for the modulation gain
bits : 8 - 16 (9 bit)
access : read-write

MGAIN_DBL_TRANSMIT : Length of a modulation gain calibration step 0: 4 symbol periods 1: 8 symbol periods
bits : 9 - 18 (10 bit)
access : read-write

MGAIN_CMP_INV : Invert the output of the modulation gain comparator before usage.
bits : 10 - 20 (11 bit)
access : read-write

MGAIN_AVER : Average over a number of comparator output values 0: 1 value 1: 3 values 2: 5 values 3: 7 values
bits : 11 - 23 (13 bit)
access : read-write

KMOD_ALPHA : Kmod channel dependent trimming constant. 0: No trimming is activated >0: The modulation gain in the direct path is modified with a factor: 1-SGNx(KMOD_ALPHA+2)x(CN-CN_CAL_RD)/2048
bits : 13 - 28 (16 bit)
access : read-write

MGAIN_TRANSMIT_LENGTH : Number of symbols for transmit0 and transmit1 length during mgain calibration.
bits : 0 - 6 (7 bit)
access : read-write

MGC_GAIN_SET : Set the desired gain for the mgc calibration amplifier. '0': gain= 15x '1': gain= 10x
bits : 0 - 0 (1 bit)
access : read-write

MGC_POLE_SW : Switch in an aditional pole on the mgc amplifer to have extra filtering of the loopfilter voltage. '0': no pole (bandwidth limited by the opamp) '1': switch in pole to reduce amplifier bandwidth
bits : 1 - 2 (2 bit)
access : read-write

GAUSS_DAC_CTRL : Reserved bits for Gauss DAC settings
bits : 2 - 5 (4 bit)
access : read-write

TUNE_VAR_V0 : Bias voltage of the VCO Tuning varactor (low Vtune) Coding identical to TUNE_VAR_V3
bits : 0 - 2 (3 bit)
access : read-write

TUNE_VAR_V1 : Bias voltage of the VCO Tuning varactor (low-mid Vtune) Coding identical to TUNE_VAR_V3
bits : 3 - 8 (6 bit)
access : read-write

TUNE_VAR_V2 : Bias voltage of the VCO Tuning varactor (high-mid Vtune) Coding identical to TUNE_VAR_V3
bits : 6 - 14 (9 bit)
access : read-write

TUNE_VAR_V3 : Bias voltage of the VCO Tuning varactor (high Vtune) 001: low 010: nominal 100: high others: not allowed
bits : 9 - 20 (12 bit)
access : read-write

MOD_VAR_V0 : Bias voltage of the VCO Modulation varactor (low Vmod) 0: low 1: mid 2: nominal 3: high
bits : 12 - 25 (14 bit)
access : read-write

MOD_VAR_V1 : Bias voltage of the VCO Modulation varactor (high Vmod) 0: low 1: mid 2: nominal 3: high
bits : 14 - 29 (16 bit)
access : read-write

VCO_CALCAP_BIT14 : LUT entry for bit 14 of the VCO calibration capacitance
bits : 0 - 15 (16 bit)
access : read-write

VCO_CALCAP_BIT15 : LUT entry for bit 15 of the VCO calibration capacitance
bits : 0 - 15 (16 bit)
access : read-write

FIXED_CUR_SET : Set the PFD output in a fixed position such that the CP output current is constant'0': UP = 0, DN = 0 '1': UP = 0, DN = 1 '2': UP = 1, DN = 0 '3': UP = 1, DN = 1
bits : 0 - 1 (2 bit)
access : read-write

FIXED_CUR_EN : Enable manual override of PFD output '0': Normal operation '1': PFD ouput given by FIXED_CUR_SET
bits : 2 - 4 (3 bit)
access : read-write

PFD_POLARITY : '0': Normal operation (UP: implies RCLK leads NCLK) '1': Inverted operation (UP: implies NCLK leads RCLK)
bits : 3 - 6 (4 bit)
access : read-write

CP_CUR_SET_RX : Chargepump current setting during PLL settling in RX mode. same coding as for CP_CUR_TX
bits : 0 - 3 (4 bit)
access : read-write

CP_CUR_SET_TX : Chargepump current setting during PLL settling in TX mode same coding as for CP_CUR_TX
bits : 4 - 11 (8 bit)
access : read-write

CP_CUR_RX : CP current setting during PLL - lock in RX mode same coding as for CP_CUR_TX
bits : 8 - 19 (12 bit)
access : read-write

CP_CUR_TX : CP current setting during PLL - Lock in TX mode 1111: 45 µA (fastest, setting 0) 0111: 15 µA (setting 1) 0011: 7.5 µA (setting 2) 0001: 3.75 µA (slowest, setting 3) Intermediate values are possible (but not recommended). Calculate the effective value with: bit 0: 3.75 µA bit 1: 3.75 µA bit 2: 7.5 µA bit 3: 30 µA
bits : 12 - 27 (16 bit)
access : read-write

LF_RES_SET_RX : Loopfilter resistor setting during PLL settling in RX mode same coding as for LF_RES_TX
bits : 0 - 3 (4 bit)
access : read-write

LF_RES_SET_TX : Loopfilter resistor setting during PLL settling in TX mode same coding as for LF_RES_TX
bits : 4 - 11 (8 bit)
access : read-write

LF_RES_RX : Loopfilter resistor setting during PLL - Lock in RX mode same coding as for LF_RES_TX
bits : 8 - 19 (12 bit)
access : read-write

LF_RES_TX : Loopfilter resistor setting during PLL - Lock in TX mode 1xxx: 72 k (fastest, setting 0) 01xx: 120 k (setting 1) 001x: 168 k (setting2) 000x: 240 k (slowest, setting 3)
bits : 12 - 27 (16 bit)
access : read-write