CTRL_REG

DCDC_ENABLE : Enables hardware control of the DCDC converter. 0: DCDC converter disabled 1: DCDC converter under hardware control
bits : 0 - 0 (1 bit)
access : read-write

DCDC_CLK_DIV : Idle clock divider, sets rate at which the output is monitored when the converter is idle. 0x0: Divide by 4 0x1: Divide by 8 (default) 0x2: Divide by 16 0x3: Divide by 32
bits : 1 - 3 (3 bit)
access : read-write

DCDC_TIMEOUT : Switch timeout, go to next state if either switch is active for longer than this setting. 0x0: Disabled 0x1: 0.25 ms 0x2: 0.50 ms 0x3: 0.75 ms 0x4: 1.00 ms (default) 0x5: 1.25 ms 0x6: 1.50 ms 0x7: 1.75 ms
bits : 3 - 8 (6 bit)
access : read-write

DCDC_OK_CLR_CNT : Number of subsequent V_NOK events needed to reset VDCD_OK. 0x0: 2 0x1: 4 0x2: 8 (deafult) 0x3: 15
bits : 6 - 13 (8 bit)
access : read-write

DCDC_ILIM_MIN : Minimum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA (default) 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA
bits : 8 - 19 (12 bit)
access : read-write

DCDC_ILIM_MAX : Maximum value for automatic inductor peak current limit control. 0x0: 6 mA 0x1: 12 mA 0x2: 18 mA 0x3: 24 mA 0x4: 30 mA 0x5: 36 mA 0x6: 42 mA 0x7: 48 mA 0x8: 54 mA (default, limits inrush current) 0x9: 60 mA 0xA: 66 mA 0xB: 72 mA 0xC: 78 mA 0xD: 84 mA 0xE: 90 mA 0xF: 96 mA (set as default for low-ohmic batteries)
bits : 12 - 27 (16 bit)
access : read-write