DMA0_A_STARTL_REG

DMA1_A_STARTL_REG

DMA1_A_STARTH_REG

DMA1_B_STARTL_REG

DMA1_B_STARTH_REG

DMA1_INT_REG

DMA1_LEN_REG

DMA1_CTRL_REG

DMA1_IDX_REG

DMA0_A_STARTH_REG

DMA2_A_STARTL_REG

DMA2_A_STARTH_REG

DMA2_B_STARTL_REG

DMA2_B_STARTH_REG

DMA2_INT_REG

DMA2_LEN_REG

DMA2_CTRL_REG

DMA2_IDX_REG

DMA3_A_STARTL_REG

DMA3_A_STARTH_REG

DMA3_B_STARTL_REG

DMA3_B_STARTH_REG

DMA3_INT_REG

DMA3_LEN_REG

DMA3_CTRL_REG

DMA3_IDX_REG

DMA0_B_STARTL_REG

DMA0_B_STARTH_REG

DMA0_INT_REG

REQ_MUX_REG

INT_STATUS_REG

CLEAR_INT_REG

DMA0_LEN_REG

DMA0_CTRL_REG

DMA0_IDX_REG

DMA0_A_STARTL : Source start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA1_A_STARTL : Source start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA1_A_STARTH : Source start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA1_B_STARTL : Destination start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA1_B_STARTH : Destination start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA1_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write

DMA1_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write

DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set.
bits : 0 - 0 (1 bit)
access : read-write

BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write

IRQ_ENABLE : 0 = disable interrupt on this channel 1 = enable interrupt on this channel
bits : 3 - 6 (4 bit)
access : read-write

DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 4 - 8 (5 bit)
access : read-write

BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write

AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 6 - 12 (7 bit)
access : read-write

CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 7 - 14 (8 bit)
access : read-write

DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 8 - 18 (11 bit)
access : read-write

DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 11 - 22 (12 bit)
access : read-write

DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 12 - 24 (13 bit)
access : read-write

REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 13 - 26 (14 bit)
access : read-write

DMA1_IDX : This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW.
bits : 0 - 15 (16 bit)
access : read-only

DMA0_A_STARTH : Source start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA2_A_STARTL : Source start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA2_A_STARTH : Source start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA2_B_STARTL : Destination start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA2_B_STARTH : Destination start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA2_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write

DMA2_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write

DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set.
bits : 0 - 0 (1 bit)
access : read-write

BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write

IRQ_ENABLE : 0 = disable interrupt on this channel 1 = enable interrupt on this channel
bits : 3 - 6 (4 bit)
access : read-write

DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 4 - 8 (5 bit)
access : read-write

BINC : Enable increment of destination address 0 = do not increment 1 = increment according value of BW
bits : 5 - 10 (6 bit)
access : read-write

AINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 6 - 12 (7 bit)
access : read-write

CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 7 - 14 (8 bit)
access : read-write

DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 8 - 18 (11 bit)
access : read-write

DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 11 - 22 (12 bit)
access : read-write

DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 12 - 24 (13 bit)
access : read-write

REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 13 - 26 (14 bit)
access : read-write

DMA2_IDX : This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW.
bits : 0 - 15 (16 bit)
access : read-only

DMA3_A_STARTL : Source start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA3_A_STARTH : Source start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA3_B_STARTL : Destination start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA3_B_STARTH : Destination start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA3_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write

DMA3_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write

DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set.
bits : 0 - 0 (1 bit)
access : read-write

BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write

IRQ_ENABLE : 0 = disable interrupt on this channel 1 = enable interrupt on this channel
bits : 3 - 6 (4 bit)
access : read-write

DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 4 - 8 (5 bit)
access : read-write

BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write

AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 6 - 12 (7 bit)
access : read-write

CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 7 - 14 (8 bit)
access : read-write

DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 8 - 18 (11 bit)
access : read-write

DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 11 - 22 (12 bit)
access : read-write

DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 12 - 24 (13 bit)
access : read-write

REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 13 - 26 (14 bit)
access : read-write

DMA3_IDX : This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW.
bits : 0 - 15 (16 bit)
access : read-only

DMA0_B_STARTL : Destination start address, lower 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA0_B_STARTH : Destination start address, upper 16 bits
bits : 0 - 15 (16 bit)
access : read-write

DMA0_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write

DMA01_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 0 and the second on channel 1. 0x0: SPI_rx / SPI_tx 0x1: Reserved 0x2: UART_rx / UART_tx 0x3: UART2_rx / UART2_tx 0x4: I2C_rx / I2C_tx 0x5: GP_ADC (Rx only) 0x6-0xE: Reserved 0xF: None Note: If any of the two available peripheral selector fields (DMA01_SEL, DMA23_SEL) have the same value, the lesser significant selector has higher priority and will control the dma acknowledge. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will generate the DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field.
bits : 0 - 3 (4 bit)
access : read-write

DMA23_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 2 and the second on channel 3. See DMA01_SEL for the peripherals' mapping.
bits : 4 - 11 (8 bit)
access : read-write

DMA_IRQ_CH0 : 0: IRQ on channel 0 is not set 1: IRQ on channel 0 is set
bits : 0 - 0 (1 bit)
access : read-only

DMA_IRQ_CH1 : 0: IRQ on channel 1 is not set 1: IRQ on channel 1 is set
bits : 1 - 2 (2 bit)
access : read-only

DMA_IRQ_CH2 : 0: IRQ on channel 2 is not set 1: IRQ on channel 2 is set
bits : 2 - 4 (3 bit)
access : read-only

DMA_IRQ_CH3 : 0: IRQ on channel 3 is not set 1: IRQ on channel 3 is set
bits : 3 - 6 (4 bit)
access : read-only

DMA_RST_IRQ_CH0 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect
bits : 0 - 0 (1 bit)
access : write-only

DMA_RST_IRQ_CH1 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect
bits : 1 - 2 (2 bit)
access : write-only

DMA_RST_IRQ_CH2 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect
bits : 2 - 4 (3 bit)
access : write-only

DMA_RST_IRQ_CH3 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect
bits : 3 - 6 (4 bit)
access : write-only

DMA0_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write

DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set.
bits : 0 - 0 (1 bit)
access : read-write

BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write

IRQ_ENABLE : 0 = disable interrupt on this channel 1 = enable interrupt on this channel
bits : 3 - 6 (4 bit)
access : read-write

DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 4 - 8 (5 bit)
access : read-write

BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write

AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 6 - 12 (7 bit)
access : read-write

CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 7 - 14 (8 bit)
access : read-write

DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 8 - 18 (11 bit)
access : read-write

DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 11 - 22 (12 bit)
access : read-write

DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 12 - 24 (13 bit)
access : read-write

REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 13 - 26 (14 bit)
access : read-write

DMA0_IDX : This (read-only) register determines the data items currently fetched by the DMA channel, during an on-going transfer. When the transfer is completed, the register is automatically reset to 0. The DMA channel uses this register to form the source/destination address of the next DMA cycle, considering also AINC/BINC and BW.
bits : 0 - 15 (16 bit)
access : read-only