CTRL1_REG

CTRL2_REG

MRM_HITS_REG

MRM_MISSES_REG

MRM_CTRL_REG

MRM_TINT_REG

MRM_THRES_REG

LNSIZECFG_REG

SWD_RESET_REG

ASSOCCFG_REG

CACHE_FLUSH : Writing a '1' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory. The read of this bit is always '0'. Note: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB.
bits : 0 - 0 (1 bit)
access : write-only

CACHE_RES1 : Reserved. Always keep 0.
bits : 1 - 2 (2 bit)
access : read-write

CACHE_LEN : Length of QSPI FLASH cacheable memory. (N+1)*64kbyte. N=1 to 512 (Max of 32 Mbyte). Setting CACHE_LEN=0 disables the cache. Note 1: The OTP memory is completely cacheable (when enabled). Note 2: The max. size/length of QSPI FLASH cacheable memory is 16 Mbyte when also OTP is cached.
bits : 0 - 8 (9 bit)
access : read-write

CACHE_WEN : 0: Cache Data and TAG memory read only. 1: Cache Data and TAG memory read/write. The TAG and Data memory are only updated by the cache controller. There is no HW protection to prevent unauthorized access by the ARM. Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory.
bits : 9 - 18 (10 bit)
access : read-write

CACHE_CGEN : 0: Cache controller clock gating is not enabled. 1: Cache controller clock gating is enabled (enabling power saving). Note: This bit must be set to '0' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached or OTP cached, e.g. from Booter or SYSRAM.
bits : 10 - 20 (11 bit)
access : read-write

ENABLE_ALSO_OTP_CACHED : Enable also the OTP cacheability when remapped to QSPI FLASH (cached). See also the notes at CACHE_LEN .
bits : 11 - 22 (12 bit)
access : read-write

ENABLE_ALSO_QSPIFLASH_CACHED : Enable also the QSPI FLASH cacheability when remapped to OTP (cached). See also the notes at CACHE_LEN .
bits : 12 - 24 (13 bit)
access : read-write

MRM_HITS : Contains the amount of cache hits.
bits : 0 - 18 (19 bit)
access : read-write

MRM_MISSES : Contains the amount of cache misses.
bits : 0 - 17 (18 bit)
access : read-write

MRM_START : 0: Freeze the misses/hits counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG. 1: Enables the counters. Note: In case CACHE_MRM_CTRL_REG[MRM_START] is set to '1' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it's '0'. At that time CACHE_MRM_CTRL_REG[MRM_START] will be reset automatically to '0' by the MRM hardware and the MRM interrupt will be generated.
bits : 0 - 0 (1 bit)
access : read-write

MRM_IRQ_MASK : 0: Disables interrupt generation. 1: Enables interrupt generation. Note: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,
bits : 1 - 2 (2 bit)
access : read-write

MRM_IRQ_TINT_STATUS : 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0).
bits : 2 - 4 (3 bit)
access : read-write

MRM_IRQ_THRES_STATUS : 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0).
bits : 3 - 6 (4 bit)
access : read-write

MRM_TINT : Defines the time interval for the monitoring in 16 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_TINT_STATUS]. Note: When MRM_TINT=0 (unrealistic value), no interrupt will be generated.
bits : 0 - 17 (18 bit)
access : read-write

MRM_THRES : Defines the threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_THRES_STATUS]. Note: When MRM_THRES=0 (unrealistic value), no interrupt will be generated.
bits : 0 - 17 (18 bit)
access : read-write

CACHE_LINE : Cache line size: 0: 8 bytes, 1: 16 bytes, 2: 32 bytes, 3: reserved. Note: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value 01 into the cache control register CACHE_CTRL1_REG just after the write of the value 00 into the cache line size configuration register CACHE_LNSIZECFG_REG.
bits : 0 - 1 (2 bit)
access : read-write

SWD_HW_RESET_REQ : 0: default. 1: HW reset request without resetting the SWD and DAP controller. The register is automatically reset with a HW_RESET. This bit can only be accessed by the debugger software and not by the application.
bits : 0 - 0 (1 bit)
access : write-only

CACHE_ASSOC : Cache associativity: 0: 1-way (direct mapped) 1: 2-way 2: 4-way 3: reserved. Note: Flush the cache controller before dynamically decreasing the associativity.
bits : 0 - 1 (2 bit)
access : read-write