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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1A byte (0x0)
mem_usage : registers
protection :

Registers

SET_FREEZE_REG

PLL_SYS_CTRL1_REG

PLL_SYS_CTRL2_REG

PLL_SYS_CTRL3_REG

PLL_SYS_STATUS_REG

PLL_SYS_TEST_REG

RESET_FREEZE_REG

DEBUG_REG

GP_STATUS_REG

GP_CONTROL_REG

ECC_BASE_ADDR_REG

LED_CONTROL_REG


SET_FREEZE_REG

Controls freezing of various timers/counters (incl. DMA and USB).
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_FREEZE_REG SET_FREEZE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZ_WKUPTIM FRZ_SWTIM0 FRZ_BLETIM FRZ_WDOG FRZ_USB FRZ_DMA FRZ_SWTIM1 FRZ_SWTIM2

FRZ_WKUPTIM : If '1', the Wake Up Timer is frozen, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM0 : If '1', the SW Timer (TIMER0) is frozen, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_BLETIM : If '1', the BLE master clock is frozen, '0' is discarded.
bits : 2 - 4 (3 bit)
access : read-write

FRZ_WDOG : If '1', the watchdog timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_USB : If '1', the USB is frozen, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

FRZ_DMA : If '1', the DMA is frozen, '0' is discarded.
bits : 5 - 10 (6 bit)
access : read-write

FRZ_SWTIM1 : If '1', the SW Timer (TIMER1) is frozen, '0' is discarded.
bits : 6 - 12 (7 bit)
access : read-write

FRZ_SWTIM2 : If '1', the SW Timer (TIMER2) is frozen, '0' is discarded.
bits : 7 - 14 (8 bit)
access : read-write


PLL_SYS_CTRL1_REG

System PLL control register 1.
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_CTRL1_REG PLL_SYS_CTRL1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_EN LDO_PLL_ENABLE LDO_PLL_VREF_HOLD PLL_R_DIV

PLL_EN : 0: Power down 1: PLL on
bits : 0 - 0 (1 bit)
access : read-write

LDO_PLL_ENABLE : 0: LDO PLL off, 1: LDO PLL on.
bits : 1 - 2 (2 bit)
access : read-write

LDO_PLL_VREF_HOLD : 0: indicates that the reference input is tracked, 1: indicates that the reference input is sampled.
bits : 2 - 4 (3 bit)
access : read-write

PLL_R_DIV : PLL Output dvider R (x means divide by x, 0 means divide by 1)
bits : 8 - 22 (15 bit)
access : read-write


PLL_SYS_CTRL2_REG

System PLL control register 2.
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_CTRL2_REG PLL_SYS_CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_N_DIV PLL_DEL_SEL PLL_SEL_MIN_CUR_INT

PLL_N_DIV : PLL Loop divider N (x means divide by x, 0 means divide by 1)
bits : 0 - 6 (7 bit)
access : read-write

PLL_DEL_SEL : PLL manual delay value for Phase Frequency Detector. 0: 0.493 1: 0.814 2: 1.13 ns <- default 3: 1.44 ns
bits : 12 - 25 (14 bit)
access : read-write

PLL_SEL_MIN_CUR_INT : 0: VCO current read from min_current <5:0>, 1: VCO current is internally determined with a calibration algoritm.
bits : 14 - 28 (15 bit)
access : read-write


PLL_SYS_CTRL3_REG

System PLL control register 3.
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_CTRL3_REG PLL_SYS_CTRL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_ICP_SEL PLL_START_DEL PLL_RECALIB

PLL_ICP_SEL : PLL charge pump current select One LSB is 5uA.
bits : 0 - 4 (5 bit)
access : read-write

PLL_START_DEL : Programmable delay time for the loop filter voltage preset value. After PLL_EN is set, the loopfilter precharge resistors are disabled after this delay time. One LSB is 48 ns
bits : 10 - 24 (15 bit)
access : read-write

PLL_RECALIB : Recalibrate
bits : 15 - 30 (16 bit)
access : read-write


PLL_SYS_STATUS_REG

System PLL status register.
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_STATUS_REG PLL_SYS_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_LOCK_FINE LDO_PLL_OK PLL_PLL_BEST_MIN_CUR PLL_CALIBR_END

PLL_LOCK_FINE : 1: PLL locked
bits : 0 - 0 (1 bit)
access : read-only

LDO_PLL_OK : 1: Indicates that LDO PLL is in regulation.
bits : 1 - 2 (2 bit)
access : read-only

PLL_PLL_BEST_MIN_CUR : Calibrated VCO frequency band.
bits : 5 - 15 (11 bit)
access : read-only

PLL_CALIBR_END : Indicates that calibration has finished.
bits : 11 - 22 (12 bit)
access : read-only


PLL_SYS_TEST_REG

System PLL test register.
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_TEST_REG PLL_SYS_TEST_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_DIS_LOOPFILT PLL_MIN_CURRENT PLL_TEST_VCTR PLL_OPEN_LOOP PLL_CHANGE PLL_SEL_N_DIV_TEST PLL_SEL_R_DIV_TEST PLL_LOCK_DET_RES_CNT

PLL_DIS_LOOPFILT : 1: disable PLL internal loop filter
bits : 0 - 0 (1 bit)
access : read-write

PLL_MIN_CURRENT : VCO current trimming.
bits : 1 - 7 (7 bit)
access : read-write

PLL_TEST_VCTR : 1: map loopfilter voltage on external pin
bits : 7 - 14 (8 bit)
access : read-write

PLL_OPEN_LOOP : 1: set to open loop to termine max frequency
bits : 8 - 16 (9 bit)
access : read-write

PLL_CHANGE : 0: normal value 1: reverse charge pump up/down signals
bits : 9 - 18 (10 bit)
access : read-write

PLL_SEL_N_DIV_TEST : Select test mode for loop divider N. Maps PLL_N_DIV input on pins and divider output on pin
bits : 10 - 20 (11 bit)
access : read-write

PLL_SEL_R_DIV_TEST : Select test mode for output divider R Maps PLL_R_DIV input on pins and divider output on pin
bits : 11 - 22 (12 bit)
access : read-write

PLL_LOCK_DET_RES_CNT : Lock measurement time in clock cycle of xx usec. After this period PLL_LOCK_FINE is calculated based on the difference of the M and N counted pulses in that period. If PLL_LOCK_FINE is still 0, the lock state machine restarts until PLL_LOCK_FINE gets 1 0: usec 7: usec
bits : 13 - 28 (16 bit)
access : read-write


RESET_FREEZE_REG

Controls unfreezing of various timers/counters (incl. DMA and USB).
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_FREEZE_REG RESET_FREEZE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRZ_WKUPTIM FRZ_SWTIM0 FRZ_BLETIM FRZ_WDOG FRZ_USB FRZ_DMA FRZ_SWTIM1 FRZ_SWTIM2

FRZ_WKUPTIM : If '1', the Wake Up Timer continues, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM0 : If '1', the SW Timer (TIMER0) continues, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_BLETIM : If '1', the BLE master clock continues, '0' is discarded.
bits : 2 - 4 (3 bit)
access : read-write

FRZ_WDOG : If '1', the watchdog timer continues, '0' is discarded.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_USB : If '1', the USB continues, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

FRZ_DMA : If '1', the DMA continues, '0' is discarded.
bits : 5 - 10 (6 bit)
access : read-write

FRZ_SWTIM1 : If '1', the SW Timer (TIMER1) continues, '0' is discarded.
bits : 6 - 12 (7 bit)
access : read-write

FRZ_SWTIM2 : If '1', the SW Timer (TIMER2) continues, '0' is discarded.
bits : 7 - 14 (8 bit)
access : read-write


DEBUG_REG

Various debug information register.
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DEBUG_REG DEBUG_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEBUGS_FREEZE_EN

DEBUGS_FREEZE_EN : Default '1', freezing of the on-chip timers is enabled when the Cortex-M0 is halted in DEBUG State. If '0', freezing of the on-chip timers is depending on FREEZE_REG when the Cortex-M0 is halted in DEBUG State except the watchdog timer. The watchdog timer is always frozen when the Cortex-M0 is halted in DEBUG State. Note: This bit is retained.
bits : 0 - 0 (1 bit)
access : read-write


GP_STATUS_REG

General purpose system status register.
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_STATUS_REG GP_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAL_PHASE

CAL_PHASE : If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured.
bits : 0 - 0 (1 bit)
access : read-write


GP_CONTROL_REG

General purpose system control register.
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GP_CONTROL_REG GP_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLE_WAKEUP_REQ BLE_H2H_BRIDGE_BYPASS BLE_WAKEUP_LP_IRQ BLE_DEEPSLDUR_MONITOR

BLE_WAKEUP_REQ : If '1', the BLE wakes up. Must be kept high at least for 1 low power clock period. If the BLE is in deep sleep state, then by setting this bit it will cause the wakeup LP IRQ to be asserted with a delay of 3 to 4 low power cycles.
bits : 0 - 0 (1 bit)
access : read-write

BLE_H2H_BRIDGE_BYPASS : If '1', the AHB-to-AHB bridge is bypassed, needed to access the BLE Register file, only when the system clock source is the XTAL and both hclk and ble_hclk are running at 16MHz, i.e. at the XTAL clock rate.
bits : 1 - 2 (2 bit)
access : read-write

BLE_WAKEUP_LP_IRQ : The current value of the BLE_WAKEUP_LP_IRQ interrupt request.
bits : 2 - 4 (3 bit)
access : read-only

BLE_DEEPSLDUR_MONITOR : The 8 LSBs of the current value of the BLE Timer DEEPSLDUR. The value has been sampled by using the CPU clock.
bits : 8 - 23 (16 bit)
access : read-only


ECC_BASE_ADDR_REG

Base address of the ECC Crypto memory register.
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECC_BASE_ADDR_REG ECC_BASE_ADDR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ECC_BASE_ADDR

ECC_BASE_ADDR : Contains the base address of the ECC Crypto memory. Memory allocation is in pages of 1KB and up to 127KB. Since the ECC has an address range of 2KB and the total addressable memory range is 128KB, the maximum value of 0x7F (127KB offset) will result in 1KB at the top of the memory range and the other 1KB at the bottom of the memory range.
bits : 0 - 6 (7 bit)
access : read-write


LED_CONTROL_REG

Controls muxing and enabling of the LEDs.
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LED_CONTROL_REG LED_CONTROL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LED1_SRC_SEL LED2_SRC_SEL LED3_SRC_SEL LED1_EN LED2_EN LED3_EN

LED1_SRC_SEL : 0: LED1 = PWM2, 1: LED1 = Breathing Timer. Note: The PWM2/3/4 can also be routed to GPIOs using PID 25/26/27 respectively.
bits : 0 - 0 (1 bit)
access : read-write

LED2_SRC_SEL : 0: LED2 = PWM3, 1: LED2 = Breathing Timer.
bits : 1 - 2 (2 bit)
access : read-write

LED3_SRC_SEL : 0: LED3 = PWM4, 1: LED3 = Breathing Timer.
bits : 2 - 4 (3 bit)
access : read-write

LED1_EN : 0: LED1 disabled, 1: LED1 enabled.
bits : 3 - 6 (4 bit)
access : read-write

LED2_EN : 0: LED2 disabled, 1: LED2 enabled.
bits : 4 - 8 (5 bit)
access : read-write

LED3_EN : 0: LED3 disabled, 1: LED3 enabled.
bits : 5 - 10 (6 bit)
access : read-write



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