SOC_CTRL1_REG

SOC_CTRL2_REG

SOC_CTRL3_REG

SOC_ADD2CH_REG

SOC_CHARGE_CNTR1_REG

SOC_CHARGE_CNTR2_REG

SOC_CHARGE_CNTR3_REG

SOC_CHARGE_AVG_REG

SOC_STATUS_REG

SOC_EXT_IN_REG

SOC_EXT_OUT_REG

CLK_REF_SEL_REG

CLK_REF_CNT_REG

CLK_REF_VAL_L_REG

CLK_REF_VAL_H_REG

CHARGER_CTRL1_REG

CHARGER_CTRL2_REG

CHARGER_STATUS_REG

SOC_ENABLE : 0: SOC analog circuits off. CHARGE_CNTRx_REG can still be written for a manual update. See SOC_ADD2CH_REG 1: SOC analog circuits enabled
bits : 0 - 0 (1 bit)
access : read-write

SOC_RESET_CHARGE : 1: Reset CHARGE_CNTR_REG
bits : 1 - 2 (2 bit)
access : read-write

SOC_RESET_AVG : 1: Reset the SOC_CHARGE_AVG_REG to the last value of SOC_CHARGE_CNTRx_REG
bits : 2 - 4 (3 bit)
access : read-write

SOC_MUTE : 0: Normal operation 1: Connect the input voltage to 0V
bits : 3 - 6 (4 bit)
access : read-write

SOC_GPIO : Reserved (not yet implemented): switches the SOC-inputs to the GPIO pins
bits : 4 - 8 (5 bit)
access : read-write

SOC_SIGN : Defines the sign of the charge converter input and output to perform a chopper function to eliminate offset voltage (see also SOC_CHOP and 'sign' on output pin) 0: non-inverted inputs and outputs 1: inverted inputs and outputs
bits : 5 - 10 (6 bit)
access : read-write

SOC_IDAC : Scales the current DAC (Ibias: default=1uA) 0: Idac=0.25*Ibias 1: Idac=0.5*Ibias 2: Idac=Ibias (=default) 3: Idac=2*Ibias
bits : 6 - 13 (8 bit)
access : read-write

SOC_LPF : 0: low-pass filter at integrator inputs disabled 1: Enables a low-pass filter at the integrator inputs
bits : 8 - 16 (9 bit)
access : read-write

SOC_CLK : SOC Sample frequency 0: automatic mode (tbd) 1: fs = 18 kHz 2: fs = 36 kHz 3: fs = 72 kHz 4: fs = 144 kHz (=default) 5: fs = 288 kHz 6: fs = 576 kHz 7: fs = 1152 kHz
bits : 9 - 20 (12 bit)
access : read-write

SOC_BIAS : Current DAC scaler 0: Ibias = 2 uA 1: Ibias = 1 uA (=default) 2: Ibias = 0.5 uA 3: Ibias = 0.25 uA
bits : 12 - 25 (14 bit)
access : read-write

SOC_CINT : Integrator capacitor scaler 0: Cint = 1 pF 1: Cint = 2 pF 2: Cint = 4 pF 3: Cint = 8 pF (=default)
bits : 14 - 29 (16 bit)
access : read-write

SOC_RVI : Voltage-to-current resistor scaler 0: Rvi = 25 k 1: Rvi = 50 k 2: Rvi = 100 k (= default) 3: Rvi = 200 k
bits : 0 - 1 (2 bit)
access : read-write

SOC_SCYCLE : Cycle current segments (8 segments) of Idac 0: no cycling 1: cycle each fs-period 2: cycle each 2 fs-periods .. 7: cycle each 7 fs-periods
bits : 2 - 6 (5 bit)
access : read-write

SOC_DCYCLE : Cycle the current divider segments of Idac 0: no cycling 1: cycle each scycle fs-periods
bits : 5 - 10 (6 bit)
access : read-write

SOC_ICM : adds a common-mode current to Idac to increase the common-mode input-level of the integrator. The common-mode input level is equal to (Idac+Icm)*Rvi 0: Icm=0 1: Icm=1*Ibias (=default) 2: Icm=2*Ibias 3: Icm=4*Ibias
bits : 6 - 13 (8 bit)
access : read-write

SOC_CHOP : Chopping control 0: 'external' chopping control with 'soc_sign'-input 1: chop each 2^1*scycle fs-periods 2: chop each 2^2*scycle fs-periods .. 7: chop each 2^7*scycle fs-periods.
bits : 8 - 18 (11 bit)
access : read-write

SOC_CMIREG_ENABLE : SOC_CMIREG enable
bits : 11 - 22 (12 bit)
access : read-write

SOC_MAW : Moving Average Weight factor charge_avg(n) = (weight*charge_avg(n-1) + charge(n) ) / (weight+1) where:weight = 2^(soc_maw)
bits : 12 - 26 (15 bit)
access : read-write

SOC_DYNAVG : if HIGH then 'weight' of Moving Average is forced to 1 if the converter detects significant input change (if dcharge > 4*delta_c, or high_limit, or low_limit)
bits : 15 - 30 (16 bit)
access : read-write

SOC_VSAT : Trigger level of the high-limit and low-limit comparators. 0: low_limit = -50mV high_limit = +50mV 1: low_limit = -100mV high_limit = +100mV (=default) 2: low_limit = -200mV high_limit = +200mV 3: low_limit = -400mV high_limit = +400mV
bits : 0 - 1 (2 bit)
access : read-write

SOC_DYNTARG : Reserved. (To be implemented) 0: Vint_target = 0V 1: Vint_target tracks the 2 MSB's of the charge register)
bits : 2 - 4 (3 bit)
access : read-write

SOC_DYNHYS : Reserved. (To be implemented) Hysteresis of the comparator which detects if the integrator voltage is rising or falling
bits : 3 - 6 (4 bit)
access : read-write

SOC_VCMI : Common Input Voltage target of regulator (see SOC_CMIREG_ENABLE) 0: 50 mV 1: 100 mV 2: 150 mV 3: 200 mV
bits : 4 - 9 (6 bit)
access : read-write

SOC_ADD2CH : Extra charge to be added to the SOC_CHARGE_CNTRx_REG per sample period (9-bit + sign + 6 fractional bits
bits : 0 - 15 (16 bit)
access : read-write

CHARGE_CNT1 : Sum of the charge-values per sampling period (bits15:0) The absolute full-scale charge value is 6-bits, At full scale charge current it takes 2^26 sampling periods until overflow of the charge_cnt register after a reset_charge event. At fs=144kHz (=default) this will happen after 33 hours At fs=1.152MHz After 10 hours
bits : 0 - 15 (16 bit)
access : read-only

CHARGE_CNT2 : Sum of the charge-values per sampling period (bits23:16)
bits : 0 - 15 (16 bit)
access : read-only

CHARGE_CNT3 : Sum of the charge-values per sampling period (bits39:24)
bits : 0 - 7 (8 bit)
access : read-only

CHARGE_AVG : Average of 'charge' current (9-bit + sign and 6 fractional bits
bits : 0 - 15 (16 bit)
access : read-only

SOC_INT_OVERLOAD : 0: Normal Operation 1: Integrator exceeds high or low limit with full-scale IDAC (charge) for more than 3 sequential sampling periods
bits : 0 - 0 (1 bit)
access : read-only

SOC_INT_LOCKED : 0: Normal Operation 1: Integrator is pushed over high or low limit. Returns to '0' if the converter runs for more than 2 sequential sampling periods in a 'safe' region (dcharge < 2*delta_c)
bits : 1 - 2 (2 bit)
access : read-only

SOC_IDAC_VAL : Controls the current for the DAC. 0: 0/512*SOC_IDAC N: N/512*SOC_IDAC
bits : 0 - 8 (9 bit)
access : read-write

SOC_IDAC_SIGN : 0: SOC_IDAC_VAL is positive 1: SOC_IDAC_VAL is negative
bits : 9 - 18 (10 bit)
access : read-write

SOC_RDAC_DIS : 0: Disables the resistor divider DAC. The Idac has 6-bits (plus sign) 1: Enables the resistor divider DAC. The Idac has 9-bits (plus sign)
bits : 10 - 20 (11 bit)
access : read-write

SOC_NR_SCYCLE : Number of the scycle
bits : 11 - 24 (14 bit)
access : read-write

SOC_EXT_SCYCLE_EN : 1: Enable 'external' control of scycle
bits : 14 - 28 (15 bit)
access : read-write

SOC_EXT_IDAC_EN : 1: Enable 'external' control of Idac
bits : 15 - 30 (16 bit)
access : read-write

SOC_HIGH_LIM : High_limit comparator output
bits : 0 - 0 (1 bit)
access : read-only

SOC_LOWLIM_COMP : Low_limit comparator output
bits : 1 - 2 (2 bit)
access : read-only

SOC_POS_COMP : Positive comparator output
bits : 2 - 4 (3 bit)
access : read-only

SOC_RISING_COMP : Rising comparator output
bits : 3 - 6 (4 bit)
access : read-only

SOC_STATE : Controller state
bits : 4 - 11 (8 bit)
access : read-only

SOC_CTRL_EVENT : Controller event
bits : 8 - 16 (9 bit)
access : read-only

REF_CLK_SEL : Select clock input for calibration: 0x0 : RC32K oscillator 0x1 : RC16M oscillator 0x2 : XTAL32K oscillator 0x3 : RCX oscillator
bits : 0 - 1 (2 bit)
access : read-write

REF_CAL_START : Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready.
bits : 2 - 4 (3 bit)
access : read-write

REF_CNT_VAL : Indicates the calibration time, with a decrement counter to 1.
bits : 0 - 15 (16 bit)
access : read-write

XTAL_CNT_VAL : Returns the lower 16 bits of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL
bits : 0 - 15 (16 bit)
access : read-only

XTAL_CNT_VAL : Returns the upper 16 bits of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL
bits : 0 - 15 (16 bit)
access : read-only

CHARGE_LEVEL : Constant Voltage Levels 00000: 3.00V (reset) 00001: 3.40V (e.g. 2xNiMH) 00010: 3.50V 00011: 3.60V (e.g. Li-phosphate) 00100: 3.74V 00101: 3.86V 00110: 4.00V 00111: 4.05V 01000: 4.10V 01001: 4.15V 01010: 4.20V (e.g. Li-Co, Li-Mn, NMC) 01011: 4.25V 01100: 4.30V 01101: 4.35V 01110: 4.40V 01111: 4.50V 10000: 4.60V 10001: 4.90V e.g. 3xNiMH 10010: 5.00V
bits : 0 - 4 (5 bit)
access : read-write

CHARGE_ON : 0: Charger in powerdown 1: Charger enabled
bits : 5 - 10 (6 bit)
access : read-write

NTC_DISABLE : 0: Charger NTC protection enabled 1: Charger NTC protection disable
bits : 6 - 12 (7 bit)
access : read-write

NTC_LOW_DISABLE : 0: Normal operation: voltage level higher than 7/8 VDD_USB will disable the charger 1: NTC low temp limit disabled: use if trickle charging below the minimum temperature is required
bits : 7 - 14 (8 bit)
access : read-write

CHARGE_CUR : Constant Current levels (typical values) 0000: 5 mA 0001: 10 mA 0010: 30 mA 0011: 45 mA 0100: 60 mA 0101: 90 mA 0110: 120 mA 0111: 150 mA 1000: 180 mA 1001: 210 mA 1010: 270 mA 1011: 300 mA 1100: 350 mA 1101: 400 mA
bits : 8 - 19 (12 bit)
access : read-write

DIE_TEMP_SET : Die temperature protection level. Charging will be automatically disabled if set level is exceeded and resumed when temperature has dropped few degrees below set level. 00: 0oC (do not use, for test only) 01: 50oC (do not use, for test only) 10: 80oC (default) 11: 100oC
bits : 12 - 25 (14 bit)
access : read-write

DIE_TEMP_DISABLE : 0: Die temperature protection enabled: charger will be disabled when die temp exceeds value set in DIE_TEMP_SET 1: Die temperature protection disabled: testmode, use only in agreement with Dialog
bits : 14 - 28 (15 bit)
access : read-write

CURRENT_GAIN_TRIM : do not change, for test purpose only
bits : 0 - 3 (4 bit)
access : read-write

CHARGER_VFLOAT_ADJ : Independent adjustment for the charge level. Adjust range is +/- 1.8 percent. The 4 bits adjustment is in two's complement.
bits : 4 - 11 (8 bit)
access : read-write

CURRENT_OFFSET_TRIM : do not change, for test purpose only
bits : 8 - 20 (13 bit)
access : read-write

CHARGER_TEST : Signals are mapped on SPDIF pin. Also set ANA_TEST_REG[ANA_TESTBUS_TO_ADCPIN] = 1 000: normal mode (no test selected) 001: Vptat (temperature sensor) [1.4V max] 010: Vbat_sense after divider [1.2V] 011: Current loop output [0 to vsupply] 100: Voltage loop output [0 to vsupply] 101: Imeas or Iref/10 110: Icharge reduced by 26.6 111: reserved
bits : 13 - 28 (16 bit)
access : read-write

CHARGER_CC_MODE : 0: current loop not in regulation (or charger is off) 1: constant current mode active, current loop in regulation.
bits : 0 - 0 (1 bit)
access : read-only

CHARGER_CV_MODE : 0: voltage loop not in regulation (or charger is off) 1: constant voltage mode active, voltage loop in regulation.
bits : 1 - 2 (2 bit)
access : read-only

END_OF_CHARGE : 0: Actual charge current is between 10...100 percent of set CHARGE_CUR (or CHARGE_ON=0) 1: Actual charge current <10 percent of set CHARGE_CUR
bits : 2 - 4 (3 bit)
access : read-only

CHARGER_BATTEMP_LOW : 0: Battery pack temperature 'ok' or 'too high' (voltage level on NTC pin below 7/8 VDD_USB) 1: Battery pack temperature 'too low' (voltage level on NTC pin above than 7/8 VDD_USB)
bits : 3 - 6 (4 bit)
access : read-only

CHARGER_BATTEMP_OK : 0: Battery pack temperature 'too low' or 'too high' (voltage level on NTC pin below 1/2 or above 7/8 VDD_USB) 1: Battery pack temperature 'ok' (voltage level on NTC pin between 1/2 and 7/8 VDD_USB)
bits : 4 - 8 (5 bit)
access : read-only

CHARGER_BATTEMP_HIGH : 0: Battery pack temperature 'ok' or 'too low' (voltage level on NTC pin above 1/2 VDD_USB) 1: Battery pack temperature 'too high' (voltage level on NTC pin below 1/2 VDD_USB)
bits : 5 - 10 (6 bit)
access : read-only

CHARGER_TMODE_PROT : 0: Dietemp below DIE_TEMP_SET level. Normal operation 1: Dietemp above DIE_TEMP_SET level. Charging is disabled
bits : 6 - 12 (7 bit)
access : read-only