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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x114 byte (0x0)
mem_usage : registers
protection :

Registers

SRC1_CTRL_REG

SRC1_IN2_REG

PCM1_CTRL_REG

PCM1_IN1_REG

PCM1_IN2_REG

PCM1_OUT1_REG

PCM1_OUT2_REG

SRC1_OUT1_REG

SRC1_OUT2_REG

MUX_REG

COEF10_SET1_REG

COEF32_SET1_REG

COEF54_SET1_REG

COEF76_SET1_REG

COEF98_SET1_REG

COEF0A_SET1_REG

SRC1_IN_FS_REG

SRC1_OUT_FS_REG

SRC1_IN1_REG


SRC1_CTRL_REG

SRC1 control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_CTRL_REG SRC1_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_EN SRC_IN_AMODE SRC_IN_CAL_BYPASS SRC_IN_DS SRC_IN_OK SRC_DITHER_DISABLE SRC_OUT_AMODE SRC_OUT_CAL_BYPASS SRC_OUT_US SRC_OUT_OK SRC_IN_OVFLOW SRC_IN_UNFLOW SRC_OUT_OVFLOW SRC_OUT_UNFLOW SRC_IN_FLOWCLR SRC_OUT_FLOWCLR SRC_PDM_MODE

SRC_EN : SRC1_IN and SRC1_OUT enable 0: disabled 1: enabled
bits : 0 - 0 (1 bit)
access : read-write

SRC_IN_AMODE : SRC1_IN Automatic conversion mode 0: Manual mode 1: Automatic mode
bits : 1 - 2 (2 bit)
access : read-write

SRC_IN_CAL_BYPASS : SRC1_IN upsampeling filter bypass 0: Do not bypass 1: Bypass filter
bits : 2 - 4 (3 bit)
access : read-write

SRC_IN_DS : SRC1_IN UpSampling IIR filters setting 00: for sample rates up-to 48kHz 01: for sample rates of 96kHz 10: reserved 11: for sample rates of 192kHz
bits : 4 - 9 (6 bit)
access : read-write

SRC_IN_OK : SRC1_IN status 0: Acquisition in progress 1: Acquisition ready
bits : 6 - 12 (7 bit)
access : read-only

SRC_DITHER_DISABLE : Dithering feature 0: Enable 1: Disable
bits : 7 - 14 (8 bit)
access : read-write

SRC_OUT_AMODE : SRC1_OUT1 Automatic Conversion mode 0:Manual mode 1:Automatic mode
bits : 13 - 26 (14 bit)
access : read-write

SRC_OUT_CAL_BYPASS : SRC1_OUT1 upsampiling filter bypass 0:Do not bypass 1:Bypass filter
bits : 14 - 28 (15 bit)
access : read-write

SRC_OUT_US : SRC1_OUT UpSampling IIR filters setting 00: for sample rates up-to 48kHz 01: for sample rates of 96kHz 10: reserved 11: for sample rates of 192kHz
bits : 16 - 33 (18 bit)
access : read-write

SRC_OUT_OK : SRC1_OUT Status 0: acquisition in progress 1: acquisition ready (In manual mode this bit is always 1)
bits : 18 - 36 (19 bit)
access : read-only

SRC_IN_OVFLOW : 1 = SRC1_IN Overflow occurred
bits : 20 - 40 (21 bit)
access : read-only

SRC_IN_UNFLOW : 1 = SRC1_IN Underflow occurred
bits : 21 - 42 (22 bit)
access : read-only

SRC_OUT_OVFLOW : 1 = SRC1_OUT Overflow occurred
bits : 22 - 44 (23 bit)
access : read-only

SRC_OUT_UNFLOW : 1 = SRC1_OUT Underflow occurred
bits : 23 - 46 (24 bit)
access : read-only

SRC_IN_FLOWCLR : Writing a 1 clears the SRC1_IN Overflow/underflow bits 21-20. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared
bits : 24 - 48 (25 bit)
access : write-only

SRC_OUT_FLOWCLR : Writing a 1 clears the SRC1_OUT Overflow/underflow bits 23-22. No more over/underflow indications while bit is 1. Keep 1 until the over/under flow bit is cleared
bits : 25 - 50 (26 bit)
access : write-only

SRC_PDM_MODE : PDM Output mode selection on PDM_DO1 00: No output 01: Right channel (falling edge of PDM_CLK) 10: Left channel (rising edge of PDM_CLK) 11: Left and Right channel
bits : 28 - 57 (30 bit)
access : read-write


SRC1_IN2_REG

SRC1 data in 2
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_IN2_REG SRC1_IN2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_IN

SRC_IN : SRC1_IN2
bits : 8 - 39 (32 bit)
access : read-write


PCM1_CTRL_REG

PCM1 Control register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM1_CTRL_REG PCM1_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_EN PCM_MASTER PCM_FSCLEN PCM_FSCDEL PCM_PPOD PCM_CLKINV PCM_FSCINV PCM_CLK_BIT PCM_CH_DEL PCM_FSC_EDGE PCM_FSC_DIV

PCM_EN : 0:PCM interface disabled 1:PCM interface enabled
bits : 0 - 0 (1 bit)
access : read-write

PCM_MASTER : 0:PCM interface in slave mode 1:PCM interface in master mode
bits : 1 - 2 (2 bit)
access : read-write

PCM_FSCLEN : 0:PCM FSC length equal to 1 data bit N:PCM FSC length equal to N*8
bits : 2 - 7 (6 bit)
access : read-write

PCM_FSCDEL : 0:PCM FSC starts one cycle before MSB bit 1:PCM FSC starts at the same time as MSB bit
bits : 6 - 12 (7 bit)
access : read-write

PCM_PPOD : 0:PCM DO push pull 1:PCM DO open drain
bits : 7 - 14 (8 bit)
access : read-write

PCM_CLKINV : 0:PCM CLK 1:PCM CLK inverted
bits : 8 - 16 (9 bit)
access : read-write

PCM_FSCINV : 0: PCM FSC 1: PCM FSC inverted
bits : 9 - 18 (10 bit)
access : read-write

PCM_CLK_BIT : 0:One clock cycle per data bit 1:Two cloc cycles per data bit
bits : 10 - 20 (11 bit)
access : read-write

PCM_CH_DEL : Channel delay in multiples of 8 bits
bits : 11 - 26 (16 bit)
access : read-write

PCM_FSC_EDGE : 0: shift channels 1, 2, 3, 4, 5, 6, 7, 8 after PCM_FSC edge 1: shift channels 1, 2, 3, 4 after PCM_FSC edge shift channels 5, 6, 7, 8 after opposite PCM_FSC edge
bits : 16 - 32 (17 bit)
access : read-write

PCM_FSC_DIV : PCM Framesync divider, Values 7-0xFFF. To divide by N, write N-1. (Minimum value N-1=7 for 8 bits PCM_FSC) Note if PCM_CLK_BIT=1, N must always be even
bits : 20 - 51 (32 bit)
access : read-write


PCM1_IN1_REG

PCM1 data in 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM1_IN1_REG PCM1_IN1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_IN

PCM_IN : PCM1_IN1 bits 31-0
bits : 0 - 31 (32 bit)
access : read-only


PCM1_IN2_REG

PCM1 data in 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM1_IN2_REG PCM1_IN2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_IN

PCM_IN : PCM1_IN2 bits 31-0
bits : 0 - 31 (32 bit)
access : read-only


PCM1_OUT1_REG

PCM1 data out 1
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM1_OUT1_REG PCM1_OUT1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_OUT

PCM_OUT : PCM1_OUT1 bits 31-0
bits : 0 - 31 (32 bit)
access : read-write


PCM1_OUT2_REG

PCM1 data out 2
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM1_OUT2_REG PCM1_OUT2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_OUT

PCM_OUT : PCM1_OUT2 bits 31-0
bits : 0 - 31 (32 bit)
access : read-write


SRC1_OUT1_REG

SRC1 data out 1
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_OUT1_REG SRC1_OUT1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_OUT

SRC_OUT : SRC1_OUT1
bits : 8 - 39 (32 bit)
access : read-only


SRC1_OUT2_REG

SRC1 data out 2
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_OUT2_REG SRC1_OUT2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_OUT

SRC_OUT : SRC1_OUT2
bits : 8 - 39 (32 bit)
access : read-only


MUX_REG

APU mux register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MUX_REG MUX_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC1_MUX_IN PCM1_MUX_IN PDM1_MUX_IN

SRC1_MUX_IN : SRC1 input mux 0 = off 1 = PCM output 2 = SRC1 input registers
bits : 0 - 2 (3 bit)
access : read-write

PCM1_MUX_IN : PCM1 input mux 0 = off 1 = SRC1 output 2 = PCM output registers
bits : 3 - 8 (6 bit)
access : read-write

PDM1_MUX_IN : PDM1 input mux 0 = SRC1_MUX_IN 1 = PDM input
bits : 6 - 12 (7 bit)
access : read-write


COEF10_SET1_REG

SRC coefficient 1,0 set 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF10_SET1_REG COEF10_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF0 SRC_COEF1

SRC_COEF0 : coefficient 0
bits : 0 - 15 (16 bit)
access : read-write

SRC_COEF1 : coefficient 1
bits : 16 - 47 (32 bit)
access : read-write


COEF32_SET1_REG

SRC coefficient 3,2 set 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF32_SET1_REG COEF32_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF2 SRC_COEF3

SRC_COEF2 : coefficient 2
bits : 0 - 15 (16 bit)
access : read-write

SRC_COEF3 : coefficient 3
bits : 16 - 47 (32 bit)
access : read-write


COEF54_SET1_REG

SRC coefficient 5,4 set 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF54_SET1_REG COEF54_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF4 SRC_COEF5

SRC_COEF4 : coefficient 4
bits : 0 - 15 (16 bit)
access : read-write

SRC_COEF5 : coefficient 5
bits : 16 - 47 (32 bit)
access : read-write


COEF76_SET1_REG

SRC coefficient 7,6 set 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF76_SET1_REG COEF76_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF6 SRC_COEF7

SRC_COEF6 : coefficient 6
bits : 0 - 15 (16 bit)
access : read-write

SRC_COEF7 : coefficient 7
bits : 16 - 47 (32 bit)
access : read-write


COEF98_SET1_REG

SRC coefficient 9,8 set 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF98_SET1_REG COEF98_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF8 SRC_COEF9

SRC_COEF8 : coefficient 8
bits : 0 - 15 (16 bit)
access : read-write

SRC_COEF9 : coefficient 9
bits : 16 - 47 (32 bit)
access : read-write


COEF0A_SET1_REG

SRC coefficient 10 set 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

COEF0A_SET1_REG COEF0A_SET1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_COEF10

SRC_COEF10 : coefficient 10
bits : 0 - 15 (16 bit)
access : read-write


SRC1_IN_FS_REG

SRC1 Sample input rate
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_IN_FS_REG SRC1_IN_FS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_IN_FS

SRC_IN_FS : SRC_IN Sample rate SRC_IN_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG[SRC_IN_DS] must be set as shown below: Sample_rate SRC_IN_FS SRC_IN_DS Audio BW 8000 Hz 0xA0000 0 4000 Hz 11025 Hz 0x0DC800 0 5512 Hz 16000 Hz 0x140000 0 8000 Hz 22050 Hz 0x1B9000 0 11025 Hz 32000 Hz 0x280000 0 16000 Hz 44100 Hz 0x372000 0 22050 Hz 48000 Hz 0x3C0000 0 24000 Hz 96000 Hz 0x3C0000 1 24000 Hz 192000 Hz 0x3C0000 3 24000 Hz In manual SRC mode, SRC_IN_FS can be set and adjusted to the desired sample rate at any time. In automatic mode the SRC returns the final sample rate as soon as SRC_IN_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz.
bits : 0 - 23 (24 bit)
access : read-write


SRC1_OUT_FS_REG

SRC1 Sample output rate
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_OUT_FS_REG SRC1_OUT_FS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_OUT_FS

SRC_OUT_FS : SRC_OUT Sample rate SRC_OUT_FS = 8192*Sample_rate/100 Sample_rate upper limit is 192 kHz. For 96 kHz and 192 kHz SRC_CTRLx_REG[SRC_DS] must be set as shown below: Sample_rate SRC_OUT_FS SRC_OUT_DS Audio BW 8000 Hz 0xA0000 0 4000 Hz 11025 Hz 0x0DC800 0 5512 Hz 16000 Hz 0x140000 0 8000 Hz 22050 Hz 0x1B9000 0 11025 Hz 32000 Hz 0x280000 0 16000 Hz 44100 Hz 0x372000 0 22050 Hz 48000 Hz 0x3C0000 0 24000 Hz 96000 Hz 0x3C0000 1 24000 Hz 192000 Hz 0x3C0000 3 24000 Hz In manual SRC mode, SRC_OUT_FS can be set and adjusted to the desired sample rate at any time. In automatic mode the SRC returns the final sample rate as soon as SRC_OUT_OK. Note that SRC_DS is not calculated in automatic mode and must be set manually automatic mode with Sample_rate of 96 kHz and 192 kHz.
bits : 0 - 23 (24 bit)
access : read-write


SRC1_IN1_REG

SRC1 data in 1
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC1_IN1_REG SRC1_IN1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_IN

SRC_IN : SRC1_IN1
bits : 8 - 39 (32 bit)
access : read-write



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