CTRL_REG

PRI1_REG

PRI2_REG

PRI3_REG

PRI4_REG

PRI5_REG

PRI6_REG

PRI7_REG

STAT_REG

PRI8_REG

PRI9_REG

PRI10_REG

PRI11_REG

PRI12_REG

PRI13_REG

PRI14_REG

PRI15_REG

PRI16_REG

PRI17_REG

INT_MASK_REG

INT_STAT_REG

BLE_PTI_REG

FTDF_PTI_REG

DIAG_REG

PRGING_ARBITER : If set to 1 then the current BLE transaction will complete normally and after that no further decision will be taken by the arbiter. The SW must keep this bit to 1 as long as it performs write operations on the COEX_PRI*_REG registers. As soon as the update on the priority registers will be completed, the SW should clear this bit. Note: This bit is updated with the COEX_CLK, so depending on the relationship between the PCLK and COEX_CLK periods a write operation to this bit may be effective in more than one PCLK clock cycles, e.g. when the COEX_CLK rate is slower than the PCLK.
bits : 0 - 0 (1 bit)
access : read-write

SMART_ACT_IMPL : Controls the behavior of the SMART_ACT (and SMART_PRI as a consequence). If SMART_ACT_IMPL= 0 then if any BLE or FTDF MAC request is active then SMART_ACT will be asserted. SMART_ACT will actually be the logical OR of ble_active and ftdf_active internal signals. SMART_ACT will be asserted regardless the decision of the Arbiter to allow or disallow the access to the on-chip radio from the active MAC(s). if SMART_ACT_IMPL= 1 then if the Arbiter's decision is to allow EXTernal MAC, then keep SMART_ACT to 0 , otherwise follow the implementation of SMART_ACT_IMPL= 0 .
bits : 4 - 8 (5 bit)
access : read-write

SEL_COEX_DIAG : The COEX block can provide internal diagnostic signals by overwriting the BLE diagnostic bus, which is forwarded to GPIO multiplexing. There is no need to program the BLE registers, but only this field and the GPIO PID fields. The encoding of this bitfield is: 0: Don't overwrite any BLE diagnostic signal. 1: Overwrite the BLE Diagnostic bits 2 down to 0: P2[2]: closing sub-state P2[1:0]: decision state 2: Overwrite the BLE Diagnostic bits 5 down to 3: P1[2]: closing sub-state P1[1:0]: decision state 3: Reserved..
bits : 5 - 11 (7 bit)
access : read-write

SEL_FTDF_CCA : If set to 1 and the COEX decision is different than FTDF , then the CCA_STAT signal going to FTDF (generated from the radio) will be forced to 1 otherwise the FTDF.CCA_STAT will be driven with the signal generated from the radio. Recommended value for SEL_FTDF_CCA is 1 .
bits : 7 - 14 (8 bit)
access : read-write

SEL_FTDF_PTI : It controls the source of the FTDF PTI value that the COEX Arbiter will use. If 0 then use the COEX_FTDF_PTI_REG. If 1 then use the PTI value provided by the FTDF core.
bits : 8 - 16 (9 bit)
access : read-write

SEL_BLE_WLAN_TX_RX : If set to 1 then the COEX block will drive the WLAN_TX and WLAN_RX inputs of the BLE core. Otherwise both BLE inputs will be forced to 0 .
bits : 10 - 20 (11 bit)
access : read-write

SEL_BLE_RADIO_BUSY : Select the logic driving the BLE core input ble.radio_busy : 0: (decision==BLE) AND rfcu.radio_busy. 1: Hold to 0 . 2: (decision==FTDF) OR (decision==EXT) OR rfcu.radio_busy. 3: (decision==FTDF) OR (decision==EXT). Selection 0 is the default, while selection 2 is the recommended value if the BLE SW supports it.
bits : 11 - 23 (13 bit)
access : read-write

IGNORE_EXT : If set to 1 then all EXT requests are ignored by masking the internal ext_act signal ( ext_act is the logical OR of ext_act0 and ext_act1 ). Refer also to IGNORE_EXT_STAT.
bits : 13 - 26 (14 bit)
access : read-write

IGNORE_FTDF : If set to 1 then all FTDF requests are ignored by masking the internal ftdf_active signal. Refer also to IGNORE_FTDF_STAT.
bits : 14 - 28 (15 bit)
access : read-write

IGNORE_BLE : If set to 1 then all BLE requests are ignored by masking the internal ble_active signal. Refer also to IGNORE_BLE_STAT.
bits : 15 - 30 (16 bit)
access : read-write

COEX_PRI_PTI : The priority level specified by this register will be applied to the packets coming from the MAC specified by the COEX_PRI_MAC bitfield and characterized with the PTI value specified by the COEX_PRI_PTI bitfield.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Specifies the MAC that has been assigned with the specific priority level. The MAC encoding follows the COEX_DECISION bitfield encoding.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_DECISION_PTR : Provides the number x of the COEX_PRIx_REG that win the last arbitration cycle. If 0 then it is a null pointer, pointing to no COEX_PRIx_REG.
bits : 0 - 4 (5 bit)
access : read-only

COEX_DECISION : Decision values: 0: Decision is NONE. 1: Decision is BLE. 2: Decision is FTDF. 3: Decision is EXT. Note: If 0 (i.e. decision is NONE) then no MAC will have access to the on-chip radio. As a consequence, the SMART_PRI signal will stay low, since no on-chip (SMART) MAC will have priority. Note: The decision NONE will be held as long as there is no *_active internal signal from BLE, FTDF or EXT. Also, if in programming state and the last transaction has been finished, then the decision will be held also to NONE. Note: While in programming mode, the COEX_PRIx_REGs are considered as invalid, which means that no new decision can be taken.
bits : 5 - 11 (7 bit)
access : read-only

COEX_DECISION_CLOSING : Provides the value of the CLOSING substate.
bits : 7 - 14 (8 bit)
access : read-only

SMART_ACT : Current state of the pin.
bits : 8 - 16 (9 bit)
access : read-only

SMART_PRI : Current state of the pin.
bits : 9 - 18 (10 bit)
access : read-only

EXT_ACT0 : Current state of the pin.
bits : 10 - 20 (11 bit)
access : read-only

EXT_ACT1 : Current state of the pin.
bits : 11 - 22 (12 bit)
access : read-only

COEX_RADIO_BUSY : Current state of RADIO_BUSY signal generated from RFCU, which is the logical OR among all Radio DCFs. Note that the arbiter will process this value with one COEX clock cycle delay.
bits : 12 - 24 (13 bit)
access : read-only

IGNORE_EXT_STAT : If set to 1 then all EXT requests are ignored by masking immediately the request signal from the external MAC. In more detail, the internal signal ext_active is the logical AND of this bitfield and the ext_act .
bits : 13 - 26 (14 bit)
access : read-only

IGNORE_FTDF_STAT : This signal is constantly 1 on BLE-only chips. If set to 1 then all FTDF requests are ignored by masking immediately the request signal from the FTDF. In more detail, the internal signal ftdf_active is the logical AND of this bitfield and the ftdf.phy_en .
bits : 14 - 28 (15 bit)
access : read-only

IGNORE_BLE_STAT : This signal is constantly 1 on FTDF-only chips. If set to 1 then all BLE requests are ignored by masking immediately the request signal from the BLE. In more detail, the internal signal ble_active is the logical AND of this bitfield and the ble.event_in_process .
bits : 15 - 30 (16 bit)
access : read-only

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_IRQ_MASK : If set to 1 then sent an COEX_IRQ event to CPU as long as COEX_INT_STAT_REG[COEX_IRQ_STAT] is 1 . If cleared then don't sent any IRQ event to CPU.
bits : 0 - 0 (1 bit)
access : read-write

COEX_IRQ_ON_SMART_ACT_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 1 - 2 (2 bit)
access : read-write

COEX_IRQ_ON_SMART_ACT_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_ACT_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 2 - 4 (3 bit)
access : read-write

COEX_IRQ_ON_SMART_PRI_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 3 - 6 (4 bit)
access : read-write

COEX_IRQ_ON_SMART_PRI_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_SMART_PRI_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 4 - 8 (5 bit)
access : read-write

COEX_IRQ_ON_EXT_ACT_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 5 - 10 (6 bit)
access : read-write

COEX_IRQ_ON_EXT_ACT_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_EXT_ACT_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 6 - 12 (7 bit)
access : read-write

COEX_IRQ_ON_FTDF_ACTIVE_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 7 - 14 (8 bit)
access : read-write

COEX_IRQ_ON_FTDF_ACTIVE_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_FTDF_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 8 - 16 (9 bit)
access : read-write

COEX_IRQ_ON_BLE_ACTIVE_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 9 - 18 (10 bit)
access : read-write

COEX_IRQ_ON_BLE_ACTIVE_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_BLE_ACTIVE_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 10 - 20 (11 bit)
access : read-write

COEX_IRQ_ON_RADIO_BUSY_R : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_R] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 11 - 22 (12 bit)
access : read-write

COEX_IRQ_ON_RADIO_BUSY_F : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_RADIO_BUSY_F] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 12 - 24 (13 bit)
access : read-write

COEX_IRQ_ON_CLOSING_BRK : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_CLOSING_BRK] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 13 - 26 (14 bit)
access : read-write

COEX_IRQ_ON_START_MID : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_START_MID] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 14 - 28 (15 bit)
access : read-write

COEX_IRQ_ON_DECISION_SW : If 1 then a 1 on COEX_INT_STAT_REG[COEX_IRQ_ON_DECISION_SW] will cause COEX_IRQ_STAT to be set also to 1 .
bits : 15 - 30 (16 bit)
access : read-write

COEX_IRQ_STAT : For each COEX_IRQ_ON_* bitfield of COEX_INT_STAT_REG the corresponding mask is applied and afterwards all the intermediate results are combined with a logical OR in order to produce the COEX_IRQ_STAT bitfield. If furthermore the COEX_INT_MASK_REG[COEX_IRQ_MASK] is set to 1 , then a COEX_IRQ signal will be forwarded to the CPU. Note: Each COEX_IRQ_ON_* bitfield of COEX_INT_STAT_REG will be set to 1 on the detection of the corresponding event and will be cleared to 0 on the read of COEX_INT_STAT_REG. The automated clear may delay a couple of PCLK cycles, depending on the relationship between PCLK and COEX_CLK.
bits : 0 - 0 (1 bit)
access : read-only

COEX_IRQ_ON_SMART_ACT_R : IRQ event on rising edge of SMART_ACT.
bits : 1 - 2 (2 bit)
access : read-only

COEX_IRQ_ON_SMART_ACT_F : IRQ event on falling edge of SMART_ACT.
bits : 2 - 4 (3 bit)
access : read-only

COEX_IRQ_ON_SMART_PRI_R : IRQ event on rising edge of SMART_PRI.
bits : 3 - 6 (4 bit)
access : read-only

COEX_IRQ_ON_SMART_PRI_F : IRQ event on falling edge of SMART_PRI.
bits : 4 - 8 (5 bit)
access : read-only

COEX_IRQ_ON_EXT_ACT_R : IRQ event on rising edge of EXT_ACT.
bits : 5 - 10 (6 bit)
access : read-only

COEX_IRQ_ON_EXT_ACT_F : RQ event on falling edge of EXT_ACT.
bits : 6 - 12 (7 bit)
access : read-only

COEX_IRQ_ON_FTDF_ACTIVE_R : IRQ event on rising edge of FTDF_ACTIVE internal signal.
bits : 7 - 14 (8 bit)
access : read-only

COEX_IRQ_ON_FTDF_ACTIVE_F : IRQ event on falling edge of FTDF_ACTIVE internal signal.
bits : 8 - 16 (9 bit)
access : read-only

COEX_IRQ_ON_BLE_ACTIVE_R : IRQ event on rising edge of BLE_ACTIVE internal signal.
bits : 9 - 18 (10 bit)
access : read-only

COEX_IRQ_ON_BLE_ACTIVE_F : IRQ event on falling edge of BLE_ACTIVE internal signal.
bits : 10 - 20 (11 bit)
access : read-only

COEX_IRQ_ON_RADIO_BUSY_R : IRQ event on rising edge of RADIO_BUSY.
bits : 11 - 22 (12 bit)
access : read-only

COEX_IRQ_ON_RADIO_BUSY_F : IRQ event on falling edge of RADIO_BUSY.
bits : 12 - 24 (13 bit)
access : read-only

COEX_IRQ_ON_CLOSING_BRK : IRQ if while entering into closing sub-state, the TX_EN or RX_EN are active. This event signals a potential break of a transmission or reception.
bits : 13 - 26 (14 bit)
access : read-only

COEX_IRQ_ON_START_MID : IRQ event when the decision switches to a MAC, while the TX_EN or RX_EN of this MAC are high. This event signals a potential break of a transmission or reception.
bits : 14 - 28 (15 bit)
access : read-only

COEX_IRQ_ON_DECISION_SW : IRQ event when the decision switches to a new MAC. It ignores the intermediate transitions to DECISION==NONE. Note that after a Radio domain reset, the first transition of the decision to any MAC will also trigger this event.
bits : 15 - 30 (16 bit)
access : read-only

COEX_BLE_PTI : This value specifies the PTI value that characterizes the next BLE transaction that will be initiated on the following ble_active positive edge. The value should remain constant during the high period of the ble_active signal.
bits : 0 - 2 (3 bit)
access : read-write

COEX_FTDF_PTI : This value specifies the PTI value that characterizes the next FTDF transaction that will be initiated on the following ftdf_active positive edge. The value should remain constant during the high period of the ftdf_active signal. Refer also to bitfield COEX_CTRL_REG.SEL_FTDF_PTI.
bits : 0 - 2 (3 bit)
access : read-write

COEX_DIAG_MON : provides the current value of the diagnostic bus forwarded to the GPIO multiplexing (named PPA). Refer to the Pxy_MODE_REG[PID] value BLE_DIAG.
bits : 0 - 15 (16 bit)
access : read-only