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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x4C byte (0x0)
mem_usage : registers
protection :

Registers

CLK_PER_REG

PCM_DIV_REG

PCM_FDIV_REG

PDM_DIV_REG

SRC_DIV_REG

USBPAD_REG


CLK_PER_REG

Peripheral divider register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_PER_REG CLK_PER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ENABLE SPI_ENABLE I2C_ENABLE QUAD_ENABLE IR_CLK_ENABLE KBSCAN_ENABLE SPI_CLK_SEL I2C_CLK_SEL KBSCAN_CLK_SEL ADC_CLK_SEL

UART_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-write

SPI_ENABLE : Enables the clock
bits : 1 - 2 (2 bit)
access : read-write

I2C_ENABLE : Enables the clock
bits : 2 - 4 (3 bit)
access : read-write

QUAD_ENABLE : Enables the clock
bits : 3 - 6 (4 bit)
access : read-write

IR_CLK_ENABLE : Enables the clock
bits : 4 - 8 (5 bit)
access : read-write

KBSCAN_ENABLE : Enables the clock
bits : 5 - 10 (6 bit)
access : read-write

SPI_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 8 - 16 (9 bit)
access : read-write

I2C_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 9 - 18 (10 bit)
access : read-write

KBSCAN_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 10 - 20 (11 bit)
access : read-write

ADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 11 - 22 (12 bit)
access : read-write


PCM_DIV_REG

PCM divider and enables
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM_DIV_REG PCM_DIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_DIV CLK_PCM_EN PCM_SRC_SEL

PCM_DIV : PCM clock divider
bits : 0 - 11 (12 bit)
access : read-write

CLK_PCM_EN : Enable for the internally generated PCM clock The PCM_DIV must be set before or together with CLK_PCM_EN.
bits : 12 - 24 (13 bit)
access : read-write

PCM_SRC_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 13 - 26 (14 bit)
access : read-write


PCM_FDIV_REG

PCM fractional division register
address_offset : 0x42 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCM_FDIV_REG PCM_FDIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCM_FDIV

PCM_FDIV : These bits define the fractional division part of the PCM clock. The left most '1' defines the denominator, the number of '1' bits define the numerator. E.g. 0x0110 means 2/9, with a distribution of 1.0001.0000 0xfeee means 13/16, with a distribution of 1111.1110.1110.1110
bits : 0 - 15 (16 bit)
access : read-write


PDM_DIV_REG

PDM divider and enables
address_offset : 0x44 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PDM_DIV_REG PDM_DIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDM_DIV CLK_PDM_EN PDM_MASTER_MODE

PDM_DIV : PDM clock divider
bits : 0 - 7 (8 bit)
access : read-write

CLK_PDM_EN : Enable for the internally generated PDM clock The PDM_DIV must be set before or together with CLK_PDM_EN.
bits : 8 - 16 (9 bit)
access : read-write

PDM_MASTER_MODE : Master mode selection 0: slave mode 1: master mode
bits : 9 - 18 (10 bit)
access : read-write


SRC_DIV_REG

SRC divider and enables
address_offset : 0x46 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRC_DIV_REG SRC_DIV_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SRC_DIV CLK_SRC_EN

SRC_DIV : SRC clock divider
bits : 0 - 7 (8 bit)
access : read-write

CLK_SRC_EN : Enable for the internally generated SRC clock The SRC_DIV must be set before or together with CLK_SRC_EN.
bits : 8 - 16 (9 bit)
access : read-write


USBPAD_REG

USB pads control register
address_offset : 0x4A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

USBPAD_REG USBPAD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 USBPAD_EN USBPHY_FORCE_SW1_OFF USBPHY_FORCE_SW2_ON

USBPAD_EN : 0: The power for the USB PHY and USB pads is switched on when the USB is enabled. 1: The power for the USB PHY and USB pads is forced on.
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_FORCE_SW1_OFF : 0: Pull up resistor SW1 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be switched off.
bits : 1 - 2 (2 bit)
access : read-write

USBPHY_FORCE_SW2_ON : 0: Pull up resistor SW2 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be 2.3Kohm
bits : 2 - 4 (3 bit)
access : read-write



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