CLK_AMBA_REG

PMU_CTRL_REG

SYS_CTRL_REG

SYS_STAT_REG

CLK_FREQ_TRIM_REG

CLK_32K_REG

CLK_16M_REG

CLK_RCX20K_REG

BANDGAP_REG

ANA_STATUS_REG

VBUS_IRQ_MASK_REG

VBUS_IRQ_CLEAR_REG

BOD_CTRL_REG

BOD_CTRL2_REG

BOD_STATUS_REG

LDO_CTRL1_REG

LDO_CTRL2_REG

SLEEP_TIMER_REG

XTALRDY_CTRL_REG

CLK_RADIO_REG

CLK_CTRL_REG

CLK_TMR_REG

HCLK_DIV : AHB interface and microprocessor clock. Source clock divided by: 000 = divide hclk by 1 001 = divide hclk by 2 010 = divide hclk by 4 011 = divide hclk by 8 1xx = divide hclk by 16
bits : 0 - 2 (3 bit)
access : read-write

PCLK_DIV : APB interface clock, Cascaded with HCLK: 00 = divide hclk by 1 01 = divide hclk by 2 10 = divide hclk by 4 11 = divide hclk by 8
bits : 4 - 9 (6 bit)
access : read-write

AES_CLK_ENABLE : Clock enable for AES crypto block
bits : 6 - 12 (7 bit)
access : read-write

ECC_CLK_ENABLE : Clock enable for ECC block
bits : 7 - 14 (8 bit)
access : read-write

TRNG_CLK_ENABLE : Clock enable for TRNG block
bits : 8 - 16 (9 bit)
access : read-write

OTP_ENABLE : Clock enable for OTP controller
bits : 9 - 18 (10 bit)
access : read-write

QSPI_DIV : QSPI divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8
bits : 10 - 21 (12 bit)
access : read-write

QSPI_ENABLE : Clock enable for QSPI controller
bits : 12 - 24 (13 bit)
access : read-write

PERIPH_SLEEP : Put all peripherals (I2C, UART, SPI, ADC) in powerdown
bits : 0 - 0 (1 bit)
access : read-write

RADIO_SLEEP : Put the digital part of the radio in powerdown
bits : 1 - 2 (2 bit)
access : read-write

BLE_SLEEP : Put the BLE in powerdown. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU.
bits : 2 - 4 (3 bit)
access : read-write

FTDF_SLEEP : Put the FTDF in powerdown
bits : 3 - 6 (4 bit)
access : read-write

RESET_ON_WAKEUP : Perform a Hardware Reset after waking up. Booter will be started.
bits : 5 - 10 (6 bit)
access : read-write

OTP_COPY_DIV : Sets the HCLK division during OTP mirroring
bits : 6 - 13 (8 bit)
access : read-write

RETAIN_RAM : Select the retainability of the 5 system memory RAM macros during deep sleep. '1' is retainable, '0' is power gated (4) is SYSRAM5 (3) is SYSRAM4 (2) is SYSRAM3 (1) is SYSRAM2 (0) is SYSRAM1
bits : 8 - 20 (13 bit)
access : read-write

ENABLE_CLKLESS : Selects the clockless sleep mode. Wakeup is done asynchronously. When set to '1', the lp_clk is stopped during deep sleep, until a wakeup event (not debounced) is detected by the WAKUPCT block. When set to '0', the lp_clk continues running, so the MAC counters keep on running. This mode cannot be combined with regulated sleep, so keep SLEEP_TIMER=0 when using ENABLE_CLKLESS.
bits : 13 - 26 (14 bit)
access : read-write

RETAIN_CACHE : Selects the retainability of the cache block during deep sleep. '1' is retainable, '0' is power gated
bits : 14 - 28 (15 bit)
access : read-write

RETAIN_ECCRAM : Selects the retainability of the ECC RAM during deep sleep. '1' is retainable, '0' is power gated
bits : 15 - 30 (16 bit)
access : read-write

REMAP_ADR0 : Controls which memory is located at address 0x0000 for execution. 0x0: ROM 0x1: OTP 0x2: FLASH 0x3: RAMS (for the exact configuration see REMAP_RAMS) 0x4: FLASH un-cached (for verification only) 0x5: OTP un-cached (for verification only) 0x6: Cache Data RAM (CACHERAM_MUX=0, for testing purposes only) Note 1: DWord (64 bits) access is not supported by the Cache Data RAM interface in mirrored mode (only 32, 16 and 8 bits). Note 2: DMA access is not supported by the Cache Data RAM interface when REMAP_ADR0=0x6.
bits : 0 - 2 (3 bit)
access : read-write

REMAP_RAMS : Defines the sequence of the 3 first DataRAMs in the memory space. DataRAM4, DataRAM5 and potentially CacheRAM, cannot not be reshuffled. 0x0: DataRAM1, DataRAM2, DataRAM3 0x1: DataRAM2, DataRAM1, DataRAM3 0x2: DataRAM3, DataRAM1, DataRAM2 0x3: DataRAM3, DataRAM2, DataRAM1
bits : 3 - 7 (5 bit)
access : read-write

PAD_LATCH_EN : Latches the control signals of the pads for state retention in powerdown mode. 0 = Control signals are retained 1 = Latch is transparant, pad can be recontrolled
bits : 5 - 10 (6 bit)
access : read-write

OTPC_RESET_REQ : Reset request for the OTP controller.
bits : 6 - 12 (7 bit)
access : read-write

DEBUGGER_ENABLE : Enable the debugger. This bit is set by the booter according to the OTP header. If not set, the SWDIO and SW_CLK can be used as gpio ports.
bits : 7 - 14 (8 bit)
access : read-write

DRA_OFF : Disables the DRA mode, and released the ARM reset
bits : 8 - 16 (9 bit)
access : read-write

TIMEOUT_DISABLE : Disables timeout in Power statemachine. By default, the statemachine continues if after 2 ms the blocks are not started up. This can be read back from ANA_STATUS_REG
bits : 9 - 18 (10 bit)
access : read-write

CACHERAM_MUX : Controls accessiblity of Cache RAM: 0: the cache controller is bypassed, the cacheRAM is visible in the memory space next to the DataRAMs 1: the cache controller is enabled, the cacheRAM is not visible anymore in the memory space
bits : 10 - 20 (11 bit)
access : read-write

DEV_PHASE : Sets the development phase mode, used in combination with OTP_COPY No copy action to SysRAM is done when the system wakes up. For emulating startup time, the OTP_COPY bit still needs to be set.
bits : 11 - 22 (12 bit)
access : read-write

QSPI_INIT : Enables QSPI initialization after wakeup
bits : 12 - 24 (13 bit)
access : read-write

OTP_COPY : Enables OTP to SysRAM copy action after waking up PD_SYS
bits : 13 - 26 (14 bit)
access : read-write

REMAP_INTVECT : 0: normal operation 1: If ARM is in address range 0 to 0xFF then the address is remapped to SYS-RAM 0x07FC.0000 to 0x07FC.00FF. This allows to put the interrupt vector table to be placed in RAM while executing from QSPI
bits : 14 - 28 (15 bit)
access : read-write

SW_RESET : Writing a '1' to this bit will generate a SW_RESET.
bits : 15 - 30 (16 bit)
access : write-only

RAD_IS_DOWN : Indicates that PD_RAD is in power down
bits : 0 - 0 (1 bit)
access : read-only

RAD_IS_UP : Indicates that PD_RAD is functional
bits : 1 - 2 (2 bit)
access : read-only

PER_IS_DOWN : Indicates that PD_PER is in power down
bits : 2 - 4 (3 bit)
access : read-only

PER_IS_UP : Indicates that PD_PER is functional
bits : 3 - 6 (4 bit)
access : read-only

DBG_IS_ACTIVE : Indicates that a debugger is attached.
bits : 5 - 10 (6 bit)
access : read-only

XTAL16_TRIM_READY : Indicates that XTAL trimming mechanism is ready, i.e. the trimming equals CLK_FREQ_TRIM_REG.
bits : 6 - 12 (7 bit)
access : read-only

BLE_IS_DOWN : Indicates that PD_DBG is in power down
bits : 8 - 16 (9 bit)
access : read-only

BLE_IS_UP : Indicates that PD_DBG is functional
bits : 9 - 18 (10 bit)
access : read-only

FTDF_IS_DOWN : Indicates that PD_DBG is in power down
bits : 10 - 20 (11 bit)
access : read-only

FTDF_IS_UP : Indicates that PD_DBG is functional
bits : 11 - 22 (12 bit)
access : read-only

FINE_ADJ : Xtal frequency fine trimming register.0x00 = lowest frequency 0xFF = highest frequency
bits : 0 - 7 (8 bit)
access : read-write

COARSE_ADJ : Xtal frequency course trimming register. 0x0 = lowest frequency 0x7 = highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200usec to allow the adjustment to settle.
bits : 8 - 18 (11 bit)
access : read-write

XTAL32K_ENABLE : Enables the 32kHz XTAL oscillator
bits : 0 - 0 (1 bit)
access : read-write

XTAL32K_RBIAS : Setting for the bias resistor. 00 is maximum, 11 is minimum. Prefered setting will be provided by Dialog
bits : 1 - 3 (3 bit)
access : read-write

XTAL32K_CUR : Bias current for the 32kHz XTAL oscillator. 0000 is minimum, 1111 is maximum, 0011 is default. For each application there is an optimal setting for which the start-up behavior is optimal
bits : 3 - 9 (7 bit)
access : read-write

RC32K_ENABLE : Enables the 32kHz RC oscillator
bits : 7 - 14 (8 bit)
access : read-write

RC32K_TRIM : 0000 = lowest frequency 0111 = default 1111 = highest frequency
bits : 8 - 19 (12 bit)
access : read-write

XTAL32K_DISABLE_AMPREG : Setting this bit disables the amplitude regulation of the XTAL32kHz oscillator. Set this bit to '1' for an external clock to XTAL32Kp Keep this bit '0' with a crystal between XTAL32Kp and XTAL32Km
bits : 12 - 24 (13 bit)
access : read-write

RC16M_ENABLE : Enables the 16MHz RC oscillator
bits : 0 - 0 (1 bit)
access : read-write

RC16M_TRIM : 0000 = lowest frequency 1111 = highest frequency
bits : 1 - 5 (5 bit)
access : read-write

XTAL16_CUR_SET : start-up current for the 16MHz XTAL oscillator. 000 is minimum, 110 is maximum.
bits : 5 - 12 (8 bit)
access : read-write

XTAL16_MAX_CURRENT : Uses the maximum current, for testing purpose only.
bits : 8 - 16 (9 bit)
access : read-write

XTAL16_EXT_CLK_ENABLE : Uses the signal on the xtal-p pin as the clock, the xtal-n pin can float.
bits : 9 - 18 (10 bit)
access : read-write

XTAL16_AMP_TRIM : sets xtal amplitude, 0 is minimum, 101 is maximum
bits : 10 - 22 (13 bit)
access : read-write

XTAL16_SPIKE_FLT_BYPASS : bypasses spikefilter
bits : 13 - 26 (14 bit)
access : read-write

XTAL16_HPASS_FLT_EN : enables high pass filter
bits : 14 - 28 (15 bit)
access : read-write

RC16M_STARTUP_DISABLE : Gates the RC16M enable from the startup block. The enable from the clksel and CLK_16M_REG[0] are not gated by this bit.
bits : 15 - 30 (16 bit)
access : read-write

RCX20K_TRIM : 0000 = lowest frequency 0111 = default 1111 = highest frequency
bits : 0 - 3 (4 bit)
access : read-write

RCX20K_NTC : Temperature control
bits : 4 - 11 (8 bit)
access : read-write

RCX20K_BIAS : Bias control
bits : 8 - 17 (10 bit)
access : read-write

RCX20K_LOWF : Extra low frequency
bits : 10 - 20 (11 bit)
access : read-write

RCX20K_ENABLE : Enable the RCX oscillator
bits : 11 - 22 (12 bit)
access : read-write

BGR_TRIM : Trim register for bandgap
bits : 0 - 4 (5 bit)
access : read-write

BGR_ITRIM : Current trimming for bias
bits : 5 - 14 (10 bit)
access : read-write

LDO_SLEEP_TRIM : 0x4 --> 1120 mV 0x5 --> 1089 mV 0x6 --> 1058 mV 0x7 --> 1030 mV 0x0 --> 1037 mV 0x1 --> 1005 mV 0x2 --> 978 mV 0x3 --> 946 mV 0x8 --> 952 mV 0x9 --> 918 mV 0xA --> 889 mV 0xB --> 861 mV 0xC --> 862 mV 0xD --> 828 mV 0xE --> 798 mV 0xF --> 770 mV These values are from simulation and vary over corners
bits : 10 - 23 (14 bit)
access : read-write

BYPASS_COLD_BOOT_DISABLE : 0x1 -> Switch to LDO_SUPPLY_USB on vbus_available and vbus_high and wokenup (SET to 0x1 after boot) 0x0 -> Switch to LDO_SUPPLY_USB on vbus_available
bits : 14 - 28 (15 bit)
access : read-write

LDO_RADIO_OK : ldo_radio = ok
bits : 0 - 0 (1 bit)
access : read-only

COMP_VBAT_OK : vbat > 1.7V
bits : 1 - 2 (2 bit)
access : read-only

VBUS_AVAILABLE : vbus is available (vbus > vbat)
bits : 2 - 4 (3 bit)
access : read-only

NEWBAT : new battery has been detected
bits : 3 - 6 (4 bit)
access : read-only

LDO_SUPPLY_VBAT_OK : ldo_supply_vbat =ok
bits : 4 - 8 (5 bit)
access : read-only

LDO_SUPPLY_USB_OK : ldo_supply_usb = ok
bits : 5 - 10 (6 bit)
access : read-only

BANDGAP_OK : bandgap = ok
bits : 6 - 12 (7 bit)
access : read-only

COMP_VDD_HIGH : VDD > 1.13V
bits : 7 - 14 (8 bit)
access : read-only

LDO_CORE_OK : ldo_core = ok
bits : 8 - 16 (9 bit)
access : read-only

LDO_1V8_PA_OK : ldo_vdd1v8P = ok
bits : 9 - 18 (10 bit)
access : read-only

LDO_1V8_FLASH_OK : ldo_vdd1v8 = ok
bits : 10 - 20 (11 bit)
access : read-only

COMP_VBUS_HIGH : VBUS > 4V
bits : 11 - 22 (12 bit)
access : read-only

COMP_VBUS_LOW : VBUS > 3.4V
bits : 12 - 24 (13 bit)
access : read-only

COMP_V33_HIGH : V33 > 1.7V
bits : 13 - 26 (14 bit)
access : read-only

COMP_1V8_FLASH_HIGH : VDD1V8 > 1.7V
bits : 14 - 28 (15 bit)
access : read-only

COMP_1V8_PA_HIGH : VDD1V8P > 1.7V
bits : 15 - 30 (16 bit)
access : read-only

VBUS_IRQ_EN_FALL : Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold
bits : 0 - 0 (1 bit)
access : read-write

VBUS_IRQ_EN_RISE : Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold
bits : 1 - 2 (2 bit)
access : read-write

VBUS_IRQ_CLEAR : Writing any value to this register will reset the VBUS_IRQ line
bits : 0 - 15 (16 bit)
access : read-write

BOD_VDD_TRIM : VDD BOD Trimming bits
bits : 0 - 1 (2 bit)
access : read-write

BOD_1V8_FLASH_TRIM : 1V8 Flash BOD Trimming bits
bits : 2 - 5 (4 bit)
access : read-write

BOD_1V8_PA_TRIM : 1V8 PA BOD Trimming bits
bits : 4 - 9 (6 bit)
access : read-write

BOD_V33_TRIM : V33 BOD Trimming bits
bits : 6 - 13 (8 bit)
access : read-write

BOD_VDD_LVL : VDD BOD Level 0=700mV 1=700mV 3=800mV 7=1.05V
bits : 8 - 18 (11 bit)
access : read-write

BOD_RESET_EN : Generate a chip reset on BOD event
bits : 0 - 0 (1 bit)
access : read-write

BOD_VDD_EN : VDD BOD Enable
bits : 1 - 2 (2 bit)
access : read-write

BOD_V33_EN : V33 BOD Enable
bits : 2 - 4 (3 bit)
access : read-write

BOD_1V8_PA_EN : 1V8 PA BOD Enable
bits : 3 - 6 (4 bit)
access : read-write

BOD_1V8_FLASH_EN : 1V8 Flash BOD Enable
bits : 4 - 8 (5 bit)
access : read-write

BOD_VBAT_EN : VBAT BOD Enable
bits : 5 - 10 (6 bit)
access : read-write

BOD_VDD_LOW : Indicates VDD > VDD_Trigger
bits : 0 - 0 (1 bit)
access : read-write

BOD_1V8_PA_LOW : Indicates V18_PA > V18_PA_Trigger
bits : 1 - 2 (2 bit)
access : read-write

BOD_1V8_FLASH_LOW : Indicates V18_Flash > V18_Flash_Trigger
bits : 2 - 4 (3 bit)
access : read-write

BOD_V33_LOW : Indicates V33 > V33_Trigger
bits : 3 - 6 (4 bit)
access : read-write

BOD_VBAT_LOW : Indicates VBAT > VBAT_Trigger
bits : 4 - 8 (5 bit)
access : read-write

LDO_CORE_CURLIM : Sets the current limit of LDO_CORE 00 = Current limiter disabled 01 = 8 mA 10 = 60 mA 11 = 80 mA
bits : 0 - 1 (2 bit)
access : read-write

LDO_VBAT_RET_LEVEL : Sets the output voltage of LDO_VBAT_RET 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V
bits : 2 - 5 (4 bit)
access : read-write

LDO_SUPPLY_VBAT_LEVEL : Sets the output voltage of LDO_SUPPLY_VBAT 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V
bits : 4 - 9 (6 bit)
access : read-write

LDO_SUPPLY_USB_LEVEL : Sets the output voltage of LDO_SUPPLY_USB 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.60 V
bits : 6 - 13 (8 bit)
access : read-write

LDO_CORE_SETVDD : Sets the output voltage of LDO_CORE 000 = 1.20 V 001 = 1.15 V 010 = 1.10 V 011 = 1.05 V 1XX = 1.32 V
bits : 8 - 18 (11 bit)
access : read-write

LDO_RADIO_SETVDD : Sets the output voltage of LDO_RADIO 000 = 1.30 V 001 = 1.35 V 010 = 1.40 V 011 = 1.45 V 1XX = 1.50 V
bits : 11 - 24 (14 bit)
access : read-write

LDO_RADIO_ENABLE : Enables (1) or disables (0) LDO_RADIO (V14) For fast XTAL startup, this bit may be kept to '1' during deep sleep. The LDO is switched off automatically when in deep sleep, and enabled when waking up.
bits : 14 - 28 (15 bit)
access : read-write

LDO_1V2_ON : Enables (1) or disables (0) LDO_CORE
bits : 0 - 0 (1 bit)
access : read-write

LDO_3V3_ON : Enables (1) or disables (0) LDO_SUPPLY_VBAT and LDO_SUPPLY_USB
bits : 1 - 2 (2 bit)
access : read-write

LDO_1V8_FLASH_ON : Enables (1) or disables (0) LDO_1V8_FLASH
bits : 2 - 4 (3 bit)
access : read-write

LDO_1V8_PA_ON : Enables (1) or disables (0) LDO_1V8_PA
bits : 3 - 6 (4 bit)
access : read-write

LDO_VBAT_RET_DISABLE : Disables (1) or enables (0) LDO_VBAT_RET
bits : 4 - 8 (5 bit)
access : read-write

LDO_1V8_FLASH_RET_DISABLE : Disables (1) or enables (0) LDO_1V8_FLASH_RET
bits : 5 - 10 (6 bit)
access : read-write

LDO_1V8_PA_RET_DISABLE : Disables (1) or enables (0) LDO_1V8_PA_RET
bits : 6 - 12 (7 bit)
access : read-write

SLEEP_TIMER : Defines the amount of ticks of the sleep clock between enabling the bandgap for re-charging the retention LDOs. This value depends on the load and should be calibrated on a per application basis.If set to 0, no recharging cycle will happen at all. Keep this value to 0 (no recharging) when using the clockless sleep.
bits : 0 - 15 (16 bit)
access : read-write

XTALRDY_CNT : Number of LP cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. 0x00: no interrupt
bits : 0 - 7 (8 bit)
access : read-write

RFCU_DIV : Division factor for RF Control Unit 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 The programmed frequency must be exactly 8MHz.
bits : 0 - 1 (2 bit)
access : read-write

RFCU_ENABLE : Enable the RF control Unit clock
bits : 3 - 6 (4 bit)
access : read-write

BLE_DIV : Division factor for BLE core blocks, having as reference the DIVN clock: 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 The programmed frequency should not be lower than 8MHz, not faster than 16MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
bits : 4 - 9 (6 bit)
access : read-write

BLE_LP_RESET : Reset for the BLE LP timer
bits : 6 - 12 (7 bit)
access : read-write

BLE_ENABLE : Enable the BLE core clocks. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU.
bits : 7 - 14 (8 bit)
access : read-write

FTDF_MAC_DIV : Division factor for FTCF MAC clock, relative to the DIVN clock 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 It should always be set to 00.
bits : 8 - 17 (10 bit)
access : read-write

FTDF_MAC_ENABLE : Enable the FTDF MAC core clocks
bits : 11 - 22 (12 bit)
access : read-write

SYS_CLK_SEL : Selects the clock source. 0x0 : XTAL16M (check the XTAL16_TRIM_READY bit!!) 0x1 : RC16M 0x2 : The Low Power clock is used 0x3 : The PLL96Mhz is used
bits : 0 - 1 (2 bit)
access : read-write

XTAL16M_DISABLE : Setting this bit instantaneously disables the 16 MHz crystal oscillator. This bit may not be set to '1' when RUNNING_AT_XTAL16M is '1' to prevent deadlock. After resetting this bit, wait for XTAL16_TRIM_READY to become '1' before switching to XTAL16 clock source.
bits : 2 - 4 (3 bit)
access : read-write

XTAL32M_MODE : Enables dividers in the XTAL for both the RF and the BB PLL.
bits : 3 - 6 (4 bit)
access : read-write

USB_CLK_SRC : Selects the USB source clock 0 : PLL clock, divided by 2 1 : HCLK
bits : 4 - 8 (5 bit)
access : read-write

PLL_DIV2 : Divides the PLL clock by 2 before being used
bits : 5 - 10 (6 bit)
access : read-write

DIVN_XTAL32M_MODE : Enables the DIVN divide-by-2, in case of a 32 MHz crystal (See also XTAL32M_MODE), to keep the DIVN clock at 16 MHz.
bits : 6 - 12 (7 bit)
access : read-write

DIVN_SYNC_LEVEL : Level of the RF divider to sync with in case XTAL32_MODE is set. This is used to align the internal DIVN clock XTAL@32MHz divided by 2 with the radio clock
bits : 7 - 14 (8 bit)
access : read-write

CLK32K_SOURCE : Sets the clock source of the LowerPower clock '00': 32 Khz RC Oscillator '01': RCX Oscillator '10': XTAL32kHz, when using an external crystal i.c.w. the internal oscillator (set P20 and P21 to FUNC_XTAL32) '11': XTAL32kHz, when an external generator or MCU applies a square wave on P20 (set P20 to FUNC_GPIO)
bits : 8 - 17 (10 bit)
access : read-write

RUNNING_AT_32K : Indicates that either the RC32k or XTAL32k is being used as clock
bits : 12 - 24 (13 bit)
access : read-only

RUNNING_AT_RC16M : Indicates that the RC16M clock is used as clock
bits : 13 - 26 (14 bit)
access : read-only

RUNNING_AT_XTAL16M : Indicates that the XTAL16M clock is used as clock, and may not be switched off
bits : 14 - 28 (15 bit)
access : read-only

RUNNING_AT_PLL96M : Indicates that the PLL96MHz clock is used as clock, and may not be switched off
bits : 15 - 30 (16 bit)
access : read-only

TMR0_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 0 - 1 (2 bit)
access : read-write

TMR0_ENABLE : Enable timer clock
bits : 2 - 4 (3 bit)
access : read-write

TMR0_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 3 - 6 (4 bit)
access : read-write

TMR1_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 4 - 9 (6 bit)
access : read-write

TMR1_ENABLE : Enable timer clock
bits : 6 - 12 (7 bit)
access : read-write

TMR1_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 7 - 14 (8 bit)
access : read-write

TMR2_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 8 - 17 (10 bit)
access : read-write

TMR2_ENABLE : Enable timer clock
bits : 10 - 20 (11 bit)
access : read-write

TMR2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 11 - 22 (12 bit)
access : read-write

BREATH_ENABLE : Enables the clock
bits : 12 - 24 (13 bit)
access : read-write

WAKEUPCT_ENABLE : Enables the clock
bits : 13 - 26 (14 bit)
access : read-write

P06_TMR1_PWM_MODE : Maps Timer1_pwm onto P0_6, when DEBUGGER_EN = '0'. This state is preserved during deep sleep, to allow PWM5 output on the pad during deep sleep.
bits : 14 - 28 (15 bit)
access : read-write