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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3A byte (0x0)
mem_usage : registers
protection :

Registers

VDD_0_REG

VDD_1_REG

V18P_0_REG

V18P_1_REG

RET_0_REG

RET_1_REG

TRIM_REG

TEST_0_REG

CTRL_0_REG

TEST_1_REG

STATUS_0_REG

STATUS_1_REG

STATUS_2_REG

STATUS_3_REG

STATUS_4_REG

TRIM_0_REG

TRIM_1_REG

TRIM_2_REG

TRIM_3_REG

IRQ_STATUS_REG

IRQ_CLEAR_REG

IRQ_MASK_REG

CTRL_1_REG

CTRL_2_REG

V14_0_REG

V14_1_REG

V18_0_REG

V18_1_REG


VDD_0_REG

DCDC VDD First Control Register
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDD_0_REG VDD_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VDD_CUR_LIM_MIN DCDC_VDD_CUR_LIM_MAX_HV DCDC_VDD_VOLTAGE DCDC_VDD_FAST_RAMPING

DCDC_VDD_CUR_LIM_MIN : VDD output minimum current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_VDD_CUR_LIM_MAX_HV : VDD output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 5 - 14 (10 bit)
access : read-write

DCDC_VDD_VOLTAGE : VDD output voltage V = 0.8 V + 25 mV * N
bits : 10 - 24 (15 bit)
access : read-write

DCDC_VDD_FAST_RAMPING : VDD output fast current ramping (improves response time at the cost of more ripple)
bits : 15 - 30 (16 bit)
access : read-write


VDD_1_REG

DCDC VDD Second Control Register
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDD_1_REG VDD_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VDD_IDLE_MIN DCDC_VDD_IDLE_HYST DCDC_VDD_CUR_LIM_MAX_LV DCDC_VDD_ENABLE_LV DCDC_VDD_ENABLE_HV

DCDC_VDD_IDLE_MIN : VDD output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 0 - 4 (5 bit)
access : read-write

DCDC_VDD_IDLE_HYST : VDD output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 5 - 14 (10 bit)
access : read-write

DCDC_VDD_CUR_LIM_MAX_LV : VDD output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)
bits : 10 - 23 (14 bit)
access : read-write

DCDC_VDD_ENABLE_LV : VDD output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 14 - 28 (15 bit)
access : read-write

DCDC_VDD_ENABLE_HV : VDD output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 15 - 30 (16 bit)
access : read-write


V18P_0_REG

DCDC VPA First Control Register
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18P_0_REG V18P_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18P_CUR_LIM_MIN DCDC_V18P_CUR_LIM_MAX_HV DCDC_V18P_VOLTAGE DCDC_V18P_FAST_RAMPING

DCDC_V18P_CUR_LIM_MIN : V18P output minimum current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V18P_CUR_LIM_MAX_HV : V18P output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V18P_VOLTAGE : V18P output voltage V = 1.2 V + 25 mV * N
bits : 10 - 24 (15 bit)
access : read-write

DCDC_V18P_FAST_RAMPING : V18P output fast current ramping (improves response time at the cost of more ripple)
bits : 15 - 30 (16 bit)
access : read-write


V18P_1_REG

DCDC VPA Second Control Register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18P_1_REG V18P_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18P_IDLE_MIN DCDC_V18P_IDLE_HYST DCDC_V18P_CUR_LIM_MAX_LV DCDC_V18P_ENABLE_LV DCDC_V18P_ENABLE_HV

DCDC_V18P_IDLE_MIN : V18P output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V18P_IDLE_HYST : V18P output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V18P_CUR_LIM_MAX_LV : V18P output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)
bits : 10 - 23 (14 bit)
access : read-write

DCDC_V18P_ENABLE_LV : V18P output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 14 - 28 (15 bit)
access : read-write

DCDC_V18P_ENABLE_HV : V18P output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 15 - 30 (16 bit)
access : read-write


RET_0_REG

DCDC First Retention Mode Register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET_0_REG RET_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VDD_CUR_LIM_RET DCDC_VDD_RET_CYCLES DCDC_V18P_CUR_LIM_RET DCDC_V18P_RET_CYCLES

DCDC_VDD_CUR_LIM_RET : VDD output sleep mode current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_VDD_RET_CYCLES : Charge cycles for VDD output in sleep mode Cycles = 1 + 2 * N
bits : 5 - 12 (8 bit)
access : read-write

DCDC_V18P_CUR_LIM_RET : V18P output sleep mode current limit I = 30 mA * (1 + N)
bits : 8 - 20 (13 bit)
access : read-write

DCDC_V18P_RET_CYCLES : Charge cycles for V18P output in sleep mode Cycles = 1 + 2 * N
bits : 13 - 28 (16 bit)
access : read-write


RET_1_REG

DCDC Second Retention Mode Register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RET_1_REG RET_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_CUR_LIM_RET DCDC_V14_RET_CYCLES DCDC_V18_CUR_LIM_RET DCDC_V18_RET_CYCLES

DCDC_V14_CUR_LIM_RET : V14 output sleep mode current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V14_RET_CYCLES : Charge cycles for V14 output in sleep mode Cycles = 1 + 2 * N
bits : 5 - 12 (8 bit)
access : read-write

DCDC_V18_CUR_LIM_RET : V18 output sleep mode current limit I = 30 mA * (1 + N)
bits : 8 - 20 (13 bit)
access : read-write

DCDC_V18_RET_CYCLES : Charge cycles for V18 output in sleep mode Cycles = 1 + 2 * N
bits : 13 - 28 (16 bit)
access : read-write


TRIM_REG

DCDC Comparator Trim Register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_REG TRIM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_N_COMP_TRIM DCDC_N_COMP_MAN_TRIM DCDC_P_COMP_TRIM DCDC_P_COMP_MAN_TRIM

DCDC_N_COMP_TRIM : Manual trim value for N side comparator Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 0 - 5 (6 bit)
access : read-write

DCDC_N_COMP_MAN_TRIM : Trim mode for N side comparator 0 = Automatic 1 = Manual
bits : 6 - 12 (7 bit)
access : read-write

DCDC_P_COMP_TRIM : Manual trim value for P side comparator Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV
bits : 7 - 19 (13 bit)
access : read-write

DCDC_P_COMP_MAN_TRIM : Trim mode for P side comparator 0 = Automatic 1 = Manual
bits : 13 - 26 (14 bit)
access : read-write


TEST_0_REG

DCDC Test Register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_0_REG TEST_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_FORCE_PSW DCDC_FORCE_NSW DCDC_FORCE_FW DCDC_FORCE_V14 DCDC_FORCE_V18 DCDC_FORCE_VDD DCDC_FORCE_V18P DCDC_FORCE_IDLE DCDC_ANA_TEST DCDC_OUTPUT_MONITOR DCDC_FORCE_CURRENT DCDC_FORCE_COMP_CLK

DCDC_FORCE_PSW : Force P switch on
bits : 0 - 0 (1 bit)
access : read-write

DCDC_FORCE_NSW : Force N switch on
bits : 1 - 2 (2 bit)
access : read-write

DCDC_FORCE_FW : Force FW switch on
bits : 2 - 4 (3 bit)
access : read-write

DCDC_FORCE_V14 : Force V14 switch on
bits : 3 - 6 (4 bit)
access : read-write

DCDC_FORCE_V18 : Force V18 switch on
bits : 4 - 8 (5 bit)
access : read-write

DCDC_FORCE_VDD : Force VDD switch on
bits : 5 - 10 (6 bit)
access : read-write

DCDC_FORCE_V18P : Force V18P switch on
bits : 6 - 12 (7 bit)
access : read-write

DCDC_FORCE_IDLE : Force idle mode
bits : 7 - 14 (8 bit)
access : read-write

DCDC_ANA_TEST : Analog test bus 000 = None 001 = High side ground 010 = Low side supply 011 = 1.2 V buffer output 100 = None 101 = None 110 = None 111 = None
bits : 8 - 18 (11 bit)
access : read-write

DCDC_OUTPUT_MONITOR : Output monitor switch (connect to ADC) 000 = None 001 = V14 010 = V18 011 = VDD 100 = VPA 101 = None 110 = None 111 = None
bits : 11 - 24 (14 bit)
access : read-write

DCDC_FORCE_CURRENT : Force output current setting
bits : 14 - 28 (15 bit)
access : read-write

DCDC_FORCE_COMP_CLK : Disables automatic comparator clock, clock lines values based on DCDC_COMP_CLK
bits : 15 - 30 (16 bit)
access : read-write


CTRL_0_REG

DCDC First Control Register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_0_REG CTRL_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_MODE DCDC_FW_ENABLE DCDC_PRIORITY DCDC_IDLE_CLK_DIV DCDC_BROWNOUT_LV_MODE DCDC_FAST_STARTUP

DCDC_MODE : DCDC converter mode 00 = Disabled 01 = Active 10 = Sleep mode 11 = Disabled
bits : 0 - 1 (2 bit)
access : read-write

DCDC_FW_ENABLE : Freewheel switch enable
bits : 2 - 4 (3 bit)
access : read-write

DCDC_PRIORITY : Charge priority register (4x 2 bit ID) Charge sequence is [1:0] > [3:2] > [5:4] > [7:6] ID[V14] = 00 ID[V18] = 01 ID[VDD] = 10 ID[V18P] = 11
bits : 3 - 13 (11 bit)
access : read-write

DCDC_IDLE_CLK_DIV : Idle Clock Divider 00 = 2 01 = 4 10 = 8 11 = 16
bits : 11 - 23 (13 bit)
access : read-write

DCDC_BROWNOUT_LV_MODE : Switches to low voltage settings when battery voltage drops below 2.5 V
bits : 13 - 26 (14 bit)
access : read-write

DCDC_FAST_STARTUP : Set current limit to maximum during initial startup
bits : 14 - 28 (15 bit)
access : read-write


TEST_1_REG

DCDC Test Register
address_offset : 0x20 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_1_REG TEST_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_TEST_REG DCDC_TEST_CURRENT DCDC_COMP_CLK

DCDC_TEST_REG : Determines which register appears on the testbus 0x0 = DCDC_NONE 0x1 = DCDC_STATUS_0 0x2 = DCDC_STATUS_1 0x3 = DCDC_STATUS_2 0x4 = DCDC_STATUS_3 0x5 = DCDC_STATUS_4 0x6 = DCDC_TRIM_0 0x7 = DCDC_TRIM_1 0x8 = DCDC_TRIM_2 0x9 = DCDC_TRIM_3 0xA-0xF = DCDC_NONE
bits : 0 - 3 (4 bit)
access : read-write

DCDC_TEST_CURRENT : Current limit setting when current limit is forced
bits : 4 - 12 (9 bit)
access : read-write

DCDC_COMP_CLK : Forced clock values for [COMP_VPA, COMP_VDD, COMP_V18, COMP_V14] (requires DCDC_FORCE_COMP_CLK = 1)
bits : 9 - 21 (13 bit)
access : read-write


STATUS_0_REG

DCDC First Status Register
address_offset : 0x22 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_0_REG STATUS_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_CHARGE_REG_0 DCDC_CHARGE_REG_1 DCDC_CHARGE_REG_2 DCDC_CHARGE_REG_3

DCDC_CHARGE_REG_0 : Charge register position 0
bits : 0 - 2 (3 bit)
access : read-only

DCDC_CHARGE_REG_1 : Charge register position 1
bits : 3 - 8 (6 bit)
access : read-only

DCDC_CHARGE_REG_2 : Charge register position 2
bits : 6 - 14 (9 bit)
access : read-only

DCDC_CHARGE_REG_3 : Charge register position 3
bits : 9 - 20 (12 bit)
access : read-only


STATUS_1_REG

DCDC Second Status Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_1_REG STATUS_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_NOK DCDC_V18_NOK DCDC_VDD_NOK DCDC_V18P_NOK DCDC_V14_OK DCDC_V18_OK DCDC_VDD_OK DCDC_V18P_OK DCDC_V14_AVAILABLE DCDC_V18_AVAILABLE DCDC_VDD_AVAILABLE DCDC_V18P_AVAILABLE

DCDC_V14_NOK : NOK output of V14 comparator
bits : 0 - 0 (1 bit)
access : read-only

DCDC_V18_NOK : NOK output of V18 comparator
bits : 1 - 2 (2 bit)
access : read-only

DCDC_VDD_NOK : NOK output of VDD comparator
bits : 2 - 4 (3 bit)
access : read-only

DCDC_V18P_NOK : NOK output of V18P comparator
bits : 3 - 6 (4 bit)
access : read-only

DCDC_V14_OK : OK output of V14 comparator
bits : 4 - 8 (5 bit)
access : read-only

DCDC_V18_OK : OK output of V18 comparator
bits : 5 - 10 (6 bit)
access : read-only

DCDC_VDD_OK : OK output of VDD comparator
bits : 6 - 12 (7 bit)
access : read-only

DCDC_V18P_OK : OK output of V18P comparator
bits : 7 - 14 (8 bit)
access : read-only

DCDC_V14_AVAILABLE : Indicates whether V14 is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured
bits : 8 - 16 (9 bit)
access : read-only

DCDC_V18_AVAILABLE : Indicates whether V18 is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured
bits : 9 - 18 (10 bit)
access : read-only

DCDC_VDD_AVAILABLE : Indicates whether VDD is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured
bits : 10 - 20 (11 bit)
access : read-only

DCDC_V18P_AVAILABLE : Indicates whether V18P is available Requires that converter is enabled, output is enabled and V_OK and V_NOK have both occured
bits : 11 - 22 (12 bit)
access : read-only


STATUS_2_REG

DCDC Third Status Register
address_offset : 0x26 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_2_REG STATUS_2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_N_COMP DCDC_P_COMP DCDC_N_COMP_N DCDC_N_COMP_P DCDC_P_COMP_N DCDC_P_COMP_P DCDC_PSW_STATE DCDC_NSW_STATE DCDC_V14_SW_STATE DCDC_V18_SW_STATE DCDC_VDD_SW_STATE DCDC_V18P_SW_STATE

DCDC_N_COMP : DCDC N side continuous time comparator output
bits : 0 - 0 (1 bit)
access : read-only

DCDC_P_COMP : DCDC P side continuous time comparator output
bits : 1 - 2 (2 bit)
access : read-only

DCDC_N_COMP_N : DCDC N side dynamic comparator N output
bits : 2 - 4 (3 bit)
access : read-only

DCDC_N_COMP_P : DCDC N side dynamic comparator P output
bits : 3 - 6 (4 bit)
access : read-only

DCDC_P_COMP_N : DCDC P side dynamic comparator N output
bits : 4 - 8 (5 bit)
access : read-only

DCDC_P_COMP_P : DCDC P side dynamic comparator P output
bits : 5 - 10 (6 bit)
access : read-only

DCDC_PSW_STATE : DCDC state machine PSW output
bits : 6 - 12 (7 bit)
access : read-only

DCDC_NSW_STATE : DCDC state machine NSW output
bits : 7 - 14 (8 bit)
access : read-only

DCDC_V14_SW_STATE : DCDC state machine V14 output
bits : 8 - 16 (9 bit)
access : read-only

DCDC_V18_SW_STATE : DCDC state machine V18 output
bits : 9 - 18 (10 bit)
access : read-only

DCDC_VDD_SW_STATE : DCDC state machine VDD output
bits : 10 - 20 (11 bit)
access : read-only

DCDC_V18P_SW_STATE : DCDC state machine V18P output
bits : 11 - 22 (12 bit)
access : read-only


STATUS_3_REG

DCDC Fourth Status Register
address_offset : 0x28 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_3_REG STATUS_3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_I_LIM_VDD DCDC_I_LIM_V18P DCDC_LV_MODE

DCDC_I_LIM_VDD : Actual VDD current limit
bits : 0 - 4 (5 bit)
access : read-only

DCDC_I_LIM_V18P : Actual V18P current limit
bits : 5 - 14 (10 bit)
access : read-only

DCDC_LV_MODE : Indicates if the converter is in low battery voltage mode
bits : 10 - 20 (11 bit)
access : read-only


STATUS_4_REG

DCDC Fifth Status Register
address_offset : 0x2A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS_4_REG STATUS_4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_I_LIM_V14 DCDC_I_LIM_V18

DCDC_I_LIM_V14 : Actual V14 current limit
bits : 0 - 4 (5 bit)
access : read-only

DCDC_I_LIM_V18 : Actual V18 current limit
bits : 5 - 14 (10 bit)
access : read-only


TRIM_0_REG

DCDC V14 Comparator Trim Register
address_offset : 0x2C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_0_REG TRIM_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TRIM_N DCDC_V14_TRIM_P

DCDC_V14_TRIM_N : N comparator trim value when V14 is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 0 - 5 (6 bit)
access : read-only

DCDC_V14_TRIM_P : P comparator trim value when V14 is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV
bits : 6 - 17 (12 bit)
access : read-only


TRIM_1_REG

DCDC V18 Comparator Trim Register
address_offset : 0x2E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_1_REG TRIM_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18_TRIM_N DCDC_V18_TRIM_P

DCDC_V18_TRIM_N : N comparator trim value when V18 is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 0 - 5 (6 bit)
access : read-only

DCDC_V18_TRIM_P : P comparator trim value when V18 is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV
bits : 6 - 17 (12 bit)
access : read-only


TRIM_2_REG

DCDC VDD Comparator Trim Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_2_REG TRIM_2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VDD_TRIM_N DCDC_VDD_TRIM_P

DCDC_VDD_TRIM_N : N comparator trim value when VDD is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 0 - 5 (6 bit)
access : read-only

DCDC_VDD_TRIM_P : P comparator trim value when VDD is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV
bits : 6 - 17 (12 bit)
access : read-only


TRIM_3_REG

DCDC VPA Comparator Trim Register
address_offset : 0x32 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_3_REG TRIM_3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18P_TRIM_N DCDC_V18P_TRIM_P

DCDC_V18P_TRIM_N : N comparator trim value when V18P is active Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 0 - 5 (6 bit)
access : read-only

DCDC_V18P_TRIM_P : P comparator trim value when V18P is active Signed magnitude representation 011111 = +47 mV 000000 = 100000 = +16 mV 111111 = -15 mV
bits : 6 - 17 (12 bit)
access : read-only


IRQ_STATUS_REG

DCDC Interrupt Status Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_STATUS_REG IRQ_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_STATUS DCDC_V18_TIMEOUT_IRQ_STATUS DCDC_VDD_TIMEOUT_IRQ_STATUS DCDC_V18P_TIMEOUT_IRQ_STATUS DCDC_BROWN_OUT_IRQ_STATUS

DCDC_V14_TIMEOUT_IRQ_STATUS : Timeout occured on V14 output
bits : 0 - 0 (1 bit)
access : read-only

DCDC_V18_TIMEOUT_IRQ_STATUS : Timeout occured on V18 output
bits : 1 - 2 (2 bit)
access : read-only

DCDC_VDD_TIMEOUT_IRQ_STATUS : Timeout occured on VDD output
bits : 2 - 4 (3 bit)
access : read-only

DCDC_V18P_TIMEOUT_IRQ_STATUS : Timeout occured on V18P output
bits : 3 - 6 (4 bit)
access : read-only

DCDC_BROWN_OUT_IRQ_STATUS : Brown out detector triggered (battery voltage below 2.5 V)
bits : 4 - 8 (5 bit)
access : read-only


IRQ_CLEAR_REG

DCDC Interrupt Clear Register
address_offset : 0x36 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_CLEAR_REG IRQ_CLEAR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_CLEAR DCDC_V18_TIMEOUT_IRQ_CLEAR DCDC_VDD_TIMEOUT_IRQ_CLEAR DCDC_V18P_TIMEOUT_IRQ_CLEAR DCDC_BROWN_OUT_IRQ_CLEAR

DCDC_V14_TIMEOUT_IRQ_CLEAR : Clear V14 timeout interrupt
bits : 0 - 0 (1 bit)
access : write-only

DCDC_V18_TIMEOUT_IRQ_CLEAR : Clear V18 timeout interrupt
bits : 1 - 2 (2 bit)
access : write-only

DCDC_VDD_TIMEOUT_IRQ_CLEAR : Clear VDD timeout interrupt
bits : 2 - 4 (3 bit)
access : write-only

DCDC_V18P_TIMEOUT_IRQ_CLEAR : Clear V18P timeout interrupt
bits : 3 - 6 (4 bit)
access : write-only

DCDC_BROWN_OUT_IRQ_CLEAR : Clear brown out interrupt
bits : 4 - 8 (5 bit)
access : write-only


IRQ_MASK_REG

DCDC Interrupt Clear Register
address_offset : 0x38 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_MASK_REG IRQ_MASK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_MASK DCDC_V18_TIMEOUT_IRQ_MASK DCDC_VDD_TIMEOUT_IRQ_MASK DCDC_V18P_TIMEOUT_IRQ_MASK DCDC_BROWN_OUT_IRQ_MASK

DCDC_V14_TIMEOUT_IRQ_MASK : Mask V14 timeout interrupt
bits : 0 - 0 (1 bit)
access : read-write

DCDC_V18_TIMEOUT_IRQ_MASK : Mask V18 timeout interrupt
bits : 1 - 2 (2 bit)
access : read-write

DCDC_VDD_TIMEOUT_IRQ_MASK : Mask VDD timeout interrupt
bits : 2 - 4 (3 bit)
access : read-write

DCDC_V18P_TIMEOUT_IRQ_MASK : Mask V18P timeout interrupt
bits : 3 - 6 (4 bit)
access : read-write

DCDC_BROWN_OUT_IRQ_MASK : Mask brown out interrupt
bits : 4 - 8 (5 bit)
access : read-write


CTRL_1_REG

DCDC Second Control Register
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_1_REG CTRL_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_TIMEOUT DCDC_GLOBAL_MAX_IDLE_TIME DCDC_STARTUP_DELAY

DCDC_TIMEOUT : P and N switch timeout, if switch is closed longer than this a timeout is generated and the FSM is forced to the next state 0 - 1937.5 ns, 62.5 ns step size
bits : 0 - 4 (5 bit)
access : read-write

DCDC_GLOBAL_MAX_IDLE_TIME : Global maximum idle time The current limit of any output that is idle for this long will be downramped faster than normal 0 - 7875 ns, 125 ns step size
bits : 5 - 15 (11 bit)
access : read-write

DCDC_STARTUP_DELAY : Delay between turning bias on and converter becoming active 0 - 31 us, 1 us step size
bits : 11 - 26 (16 bit)
access : read-write


CTRL_2_REG

DCDC Third Control Register
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_2_REG CTRL_2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_HSGND_TRIM DCDC_LSSUP_TRIM DCDC_TUNE DCDC_TIMEOUT_IRQ_RES DCDC_TIMEOUT_IRQ_TRIG

DCDC_HSGND_TRIM : Trim high side ground V = VBAT - (2.2 V + 200 mV * N)
bits : 0 - 2 (3 bit)
access : read-write

DCDC_LSSUP_TRIM : Trim low side supply voltage V = 2 V + 100 mV * N
bits : 3 - 8 (6 bit)
access : read-write

DCDC_TUNE : Trim current sensing circuitry 00 = +0 percent 01 = +4 percent 10 = +8 percent 11 = +12 percent
bits : 6 - 13 (8 bit)
access : read-write

DCDC_TIMEOUT_IRQ_RES : Number of successive non-timed out charge events required to clear timeout event counter
bits : 8 - 19 (12 bit)
access : read-write

DCDC_TIMEOUT_IRQ_TRIG : Number of timeout events before timeout interrupt is generated
bits : 12 - 27 (16 bit)
access : read-write


V14_0_REG

DCDC V14 First Control Register
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V14_0_REG V14_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_CUR_LIM_MIN DCDC_V14_CUR_LIM_MAX_HV DCDC_V14_VOLTAGE DCDC_V14_FAST_RAMPING

DCDC_V14_CUR_LIM_MIN : V14 output minimum current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V14_CUR_LIM_MAX_HV : V14 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V14_VOLTAGE : V14 output voltage V = 1.2 V + 25 mV * N
bits : 10 - 24 (15 bit)
access : read-write

DCDC_V14_FAST_RAMPING : V14 output fast current ramping (improves response time at the cost of more ripple)
bits : 15 - 30 (16 bit)
access : read-write


V14_1_REG

DCDC V14 Second Control Register
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V14_1_REG V14_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_IDLE_MIN DCDC_V14_IDLE_HYST DCDC_V14_CUR_LIM_MAX_LV DCDC_V14_ENABLE_LV DCDC_V14_ENABLE_HV

DCDC_V14_IDLE_MIN : V14 output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V14_IDLE_HYST : V14 output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V14_CUR_LIM_MAX_LV : V14 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)
bits : 10 - 23 (14 bit)
access : read-write

DCDC_V14_ENABLE_LV : V14 output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 14 - 28 (15 bit)
access : read-write

DCDC_V14_ENABLE_HV : V14 output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 15 - 30 (16 bit)
access : read-write


V18_0_REG

DCDC V18 First Control Register
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18_0_REG V18_0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18_CUR_LIM_MIN DCDC_V18_CUR_LIM_MAX_HV DCDC_V18_VOLTAGE DCDC_V18_FAST_RAMPING

DCDC_V18_CUR_LIM_MIN : V18 output minimum current limit I = 30 mA * (1 + N)
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V18_CUR_LIM_MAX_HV : V18 output maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V18_VOLTAGE : V18 output voltage V = 1.2 V + 25 mV * N
bits : 10 - 24 (15 bit)
access : read-write

DCDC_V18_FAST_RAMPING : V18 output fast current ramping (improves response time at the cost of more ripple)
bits : 15 - 30 (16 bit)
access : read-write


V18_1_REG

DCDC V18 Second Control Register
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18_1_REG V18_1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18_IDLE_MIN DCDC_V18_IDLE_HYST DCDC_V18_CUR_LIM_MAX_LV DCDC_V18_ENABLE_LV DCDC_V18_ENABLE_HV

DCDC_V18_IDLE_MIN : V18 output minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 0 - 4 (5 bit)
access : read-write

DCDC_V18_IDLE_HYST : V18 output idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 5 - 14 (10 bit)
access : read-write

DCDC_V18_CUR_LIM_MAX_LV : V18 output maximum current limit low battery voltage mode) I = 30 mA * (1 + N)
bits : 10 - 23 (14 bit)
access : read-write

DCDC_V18_ENABLE_LV : V18 output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 14 - 28 (15 bit)
access : read-write

DCDC_V18_ENABLE_HV : V18 output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 15 - 30 (16 bit)
access : read-write



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