Peripheral_Registers

TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported.
bits : 0 - 31 (32 bit)
access : read-write

TX_FIFO_2_0_REG

Address transmit fifo 2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported.
bits : 0 - 31 (32 bit)
access : read-write

REL_NAME_0_REG

Name of the release
address_offset : 0x10000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REL_NAME : Name of the release
bits : 0 - 31 (32 bit)
access : read-only

REL_NAME_1_REG

Name of the release
address_offset : 0x10004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REL_NAME : Name of the release
bits : 0 - 31 (32 bit)
access : read-only

REL_NAME_2_REG

Name of the release
address_offset : 0x10008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REL_NAME : Name of the release
bits : 0 - 31 (32 bit)
access : read-only

REL_NAME_3_REG

Name of the release
address_offset : 0x1000C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REL_NAME : Name of the release
bits : 0 - 31 (32 bit)
access : read-only

BUILDTIME_0_REG

Build time
address_offset : 0x10010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUILDTIME : Build time of device
bits : 0 - 31 (32 bit)
access : read-only

BUILDTIME_1_REG

Build time
address_offset : 0x10014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUILDTIME : Build time of device
bits : 0 - 31 (32 bit)
access : read-only

BUILDTIME_2_REG

Build time
address_offset : 0x10018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUILDTIME : Build time of device
bits : 0 - 31 (32 bit)
access : read-only

BUILDTIME_3_REG

Build time
address_offset : 0x1001C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUILDTIME : Build time of device
bits : 0 - 31 (32 bit)
access : read-only

GLOB_CONTROL_0_REG

Global control register
address_offset : 0x10020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISPANCOORDINATOR : Enable/disable receiver check on address fields (0=enabled, 1=disabled)
bits : 1 - 2 (2 bit)
access : read-write

RX_DMA_REQ : Source of the RX_DMA_REQ output of this block.
bits : 2 - 4 (3 bit)
access : read-write

TX_DMA_REQ : Source of the TX_DMA_REQ output of this block.
bits : 3 - 6 (4 bit)
access : read-write

MACSIMPLEADDRESS : Simple address of the PAN coordinator
bits : 8 - 23 (16 bit)
access : read-write

MACLEENABLED : If set, Low Energy mode is enabled
bits : 17 - 34 (18 bit)
access : read-write

MACTSCHENABLED : If set, TSCH mode is enabled
bits : 18 - 36 (19 bit)
access : read-write

GLOB_CONTROL_1_REG

Global control register
address_offset : 0x10024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACPANID : The values 0xFFFF indicates that the device is not associated
bits : 0 - 15 (16 bit)
access : read-write

MACSHORTADDRESS : The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available. The latter one is used if the device i
bits : 16 - 47 (32 bit)
access : read-write

GLOB_CONTROL_2_REG

Global control register
address_offset : 0x10028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AEXTENDEDADDRESS_L : Unique device address, lower 32 bit
bits : 0 - 31 (32 bit)
access : read-write

GLOB_CONTROL_3_REG

Global control register
address_offset : 0x1002C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AEXTENDEDADDRESS_H : Unique device address, higher 16 bit
bits : 0 - 31 (32 bit)
access : read-write

LMAC_CONTROL_0_REG

Lmac control register
address_offset : 0x10030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXONDURATION : Time the Rx must be on
bits : 1 - 25 (25 bit)
access : read-write

RXALWAYSON : If set, the receiver shall be always on if RxEnable is set
bits : 25 - 50 (26 bit)
access : read-write

PTI : Info to arbiter if phy_en is set
bits : 27 - 57 (31 bit)
access : read-write

KEEP_PHY_EN : When the transmit or receive action is ready (LmacReady4Sleep will is set), the phy_en signal is cleared unless the control register keep_phy_en is set. When the control register keep_phy_en is set, the signal phy_en shall remain being set until the keep_phy_en is cleared.
bits : 31 - 62 (32 bit)
access : read-write

TXPIPEPROPDELAY_REG

Prop delay transmit register
address_offset : 0x10034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXPIPEPROPDELAY : Prop delay of tx pipe, start to DPHY
bits : 0 - 7 (8 bit)
access : read-write

MACACKWAITDURATION_REG

Maximum time to wait for a ACK
address_offset : 0x10038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACACKWAITDURATION : Max time to wait for a (normal) ACK
bits : 0 - 7 (8 bit)
access : read-write

MACENHACKWAITDURATION_REG

Maximum time to wait for an enhanced ACK frame
address_offset : 0x1003C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACENHACKWAITDURATION : The maximum time (in s) to wait for an enhanced acknowledgement frame
bits : 0 - 15 (16 bit)
access : read-write

LMAC_CONTROL_1_REG

Lmac control register
address_offset : 0x10040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYRXATTR_DEM_PTI : DEM packet information.
bits : 0 - 3 (4 bit)
access : read-write

PHYRXATTR_CN : Channel Number.
bits : 4 - 11 (8 bit)
access : read-write

PHYRXATTR_CALCAP : CalCap value.
bits : 8 - 19 (12 bit)
access : read-write

PHYRXATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 12 - 26 (15 bit)
access : read-write

PHYRXATTR_HSI : HighSide injection.
bits : 15 - 30 (16 bit)
access : read-write

LMAC_CONTROL_2_REG

Lmac control register
address_offset : 0x10044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDSCANENABLE : if set, Energy Detect scan will be done
bits : 0 - 0 (1 bit)
access : read-write

EDSCANDURATION : Length of ED scan
bits : 8 - 39 (32 bit)
access : read-write

LMAC_CONTROL_3_REG

Lmac control register
address_offset : 0x10048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACMAXFRAMETOTALWAITTIME : Max time to wait for a requested Data Frame or an announced broadcast frame
bits : 0 - 15 (16 bit)
access : read-write

CCAIDLEWAIT : Time to wait after CCA returned and quot medium idle and quot before starting TX-ON (in us). Note: not applicable in TSCH mode since there macTSRxTx shall be used.
bits : 16 - 39 (24 bit)
access : read-write

LMAC_CONTROL_OS_REG

Lmac control register
address_offset : 0x10050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GETGENERATORVAL : If set, the current values of WU gen and TS gen will be captured.
bits : 0 - 0 (1 bit)
access : write-only

RXENABLE : If set, receiving data may be done
bits : 1 - 2 (2 bit)
access : write-only

SINGLECCA : If set, a single CCA will be performed.
bits : 2 - 4 (3 bit)
access : write-only

LMAC_CONTROL_STATUS_REG

Lmac status register
address_offset : 0x10054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMACREADY4SLEEP : Indicates that the LMAC is ready to go to sleep.
bits : 1 - 2 (2 bit)
access : read-only

CCASTAT : Value single CCA when CCAstat_e is set.
bits : 2 - 4 (3 bit)
access : read-only

WAKEUPTIMERENABLESTATUS : Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value).
bits : 6 - 12 (7 bit)
access : read-only

EDSCANVALUE : Result of ED scan.
bits : 8 - 23 (16 bit)
access : read-only

EVENTCURRVAL_REG

Value of event generator
address_offset : 0x10058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVENTCURRVAL : Value of captured Event generator
bits : 0 - 31 (32 bit)
access : read-only

TIMESTAMPCURRVAL_REG

Value of timestamp generator
address_offset : 0x1005C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMESTAMPCURRVAL : Value of captured TS gen
bits : 0 - 31 (32 bit)
access : read-only

LMAC_CONTROL_4_REG

Lmac control register
address_offset : 0x10060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYSLEEPWAIT : Time between negate and assert PHY_EN When the signal phy_en is deasserted, it will not be asserted within the time phySleepWait. This time is indicated by the control register phySleepWait (resolution: ~s).
bits : 0 - 7 (8 bit)
access : read-write

RXPIPEPROPDELAY : The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the and quot data valid and quot indication to the LMAC controller.
bits : 8 - 23 (16 bit)
access : read-write

PHYACKATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write

PHYACKATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write

PHYACKATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write

PHYACKATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write

PHYACKATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write

LMAC_CONTROL_5_REG

Lmac control register
address_offset : 0x10064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACK_RESPONSE_DELAY : In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. The default value shall is 192 ~s (12 symbols).
bits : 0 - 7 (8 bit)
access : read-write

CCASTATWAIT : The output CCASTAT is valid after 8 symbols + phyRxStartup. The 8 symbols are programmable by control registerCcaStatWait[4] in symbol timesl. Default value is 8d.
bits : 8 - 19 (12 bit)
access : read-write

PHYCSMACAATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write

PHYCSMACAATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write

PHYCSMACAATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write

PHYCSMACAATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write

PHYCSMACAATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write

LMAC_CONTROL_6_REG

Lmac control register
address_offset : 0x10068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIFSPERIOD : The LIFS period is programmable by LifsPeriod (in symbols). The default is 40 symbols (640 ~s),
bits : 0 - 7 (8 bit)
access : read-write

SIFSPERIOD : The SIFS period is programmable by SifsPeriod (in symbols). The default is 12 symbols (192 ~s).
bits : 8 - 23 (16 bit)
access : read-write

WUIFSPERIOD : The WakeUp IFS period is programmable by WUifsPeriod (in symbols). The default is 12 symbols (192 ~s).
bits : 16 - 39 (24 bit)
access : read-write

LMAC_CONTROL_11_REG

Lmac control register
address_offset : 0x1006C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRXTOTALCYCLETIME : In order to make it easier to calculate if it is efficient to disable and enable the PHY Rx until the RZ time is reached, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution in 10 sym)
bits : 0 - 15 (16 bit)
access : read-write

MACDISCARXOFFTORZ : This switching off and on of the PHY Rx can be disabled whith the control register macDisCaRxOfftoRZ. 0 : Disabled 1 : Enabled
bits : 16 - 32 (17 bit)
access : read-write

LMAC_CONTROL_DELTA_REG

Lmac delta control register
address_offset : 0x10070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMACREADY4SLEEP_D : Delta bit for register and quot LmacReady4sleep and quot
bits : 1 - 2 (2 bit)
access : read-write

SYNCTIMESTAMP_E : The SyncTimeStamp_e event is set when the TimeStampgenerator is loaded with SyncTimeStampVal. This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr.
bits : 2 - 4 (3 bit)
access : read-write

SYMBOLTIMETHR_E : Event that symboltime counter matched SymbolTimeThr
bits : 3 - 6 (4 bit)
access : read-write

SYMBOLTIME2THR_E : Event that symboltime counter matched SymbolTime2Thr
bits : 4 - 8 (5 bit)
access : read-write

GETGENERATORVAL_E : Event which indicates the getGeneratorVal request is completed
bits : 5 - 10 (6 bit)
access : read-write

WAKEUPTIMERENABLESTATUS_D : Delta which indicates that WakeupTimerEnableStatus has changed
bits : 6 - 12 (7 bit)
access : read-write

TIMESTAMPCURRPHASEVAL_REG

Value of timestamp generator phase within a symbol
address_offset : 0x10074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMESTAMPCURRPHASEVAL : Value of captured TS gen phase within a symbol
bits : 0 - 7 (8 bit)
access : read-only

MACTSTXACKDELAYVAL_REG

Time left until next ACK is sent (us)
address_offset : 0x10078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSTXACKDELAYVAL : The time in us left until the ack frame is sent by the lmac
bits : 0 - 15 (16 bit)
access : read-only

LMAC_CONTROL_MASK_REG

Lmac mask control register
address_offset : 0x10080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMACREADY4SLEEP_M : Mask bit for delta bit and quot LmacReady4sleep_d and quot
bits : 1 - 2 (2 bit)
access : read-write

SYNCTIMESTAMP_M : Mask bit for event register SyncTimeStamp_e.
bits : 2 - 4 (3 bit)
access : read-write

SYMBOLTIMETHR_M : Mask for SymbolTimeThr_e
bits : 3 - 6 (4 bit)
access : read-write

SYMBOLTIME2THR_M : Mask for SymbolTime2Thr_e
bits : 4 - 8 (5 bit)
access : read-write

GETGENERATORVAL_M : Mask for getGeneratorVal_e
bits : 5 - 10 (6 bit)
access : read-write

WAKEUPTIMERENABLESTATUS_M : Mask for WakeupTimerEnableStatus_d
bits : 6 - 12 (7 bit)
access : read-write

LMAC_EVENT_REG

Lmac event regsiter
address_offset : 0x10090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDSCANREADY_E : The event EdScanReady_e is set to notify that the ED scan is ready.
bits : 0 - 0 (1 bit)
access : read-write

CCASTAT_E : If set, the single CCA is ready
bits : 1 - 2 (2 bit)
access : read-write

RXTIMEREXPIRED_E : Set if one of the timers enabling the RX-ON mode expires without having received any valid frame
bits : 2 - 4 (3 bit)
access : read-write

LMAC_MASK_REG

Lmac mask register
address_offset : 0x10094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EDSCANREADY_M : Mask bit for event and quot EdScanReady_e and quot
bits : 0 - 0 (1 bit)
access : read-write

CCASTAT_M : Mask bit for event and quot CCAstat_e and quot
bits : 1 - 2 (2 bit)
access : read-write

RXTIMEREXPIRED_M : Mask bit for event and quot RxTimerExpired_e and quot
bits : 2 - 4 (3 bit)
access : read-write

LMAC_MANUAL_1_REG

Lmax manual PHY register
address_offset : 0x100A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMAC_MANUAL_MODE : If the control register lmac_manual_mode is set, the LMAC controller control signals should be controlled by the lmac_manual_control registers
bits : 0 - 0 (1 bit)
access : read-write

LMAC_MANUAL_PHY_EN : lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set
bits : 1 - 2 (2 bit)
access : read-write

LMAC_MANUAL_TX_EN : lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set
bits : 2 - 4 (3 bit)
access : read-write

LMAC_MANUAL_RX_EN : lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set
bits : 3 - 6 (4 bit)
access : read-write

LMAC_MANUAL_RX_PIPE_EN : lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set
bits : 4 - 8 (5 bit)
access : read-write

LMAC_MANUAL_ED_REQUEST : lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set
bits : 5 - 10 (6 bit)
access : read-write

LMAC_MANUAL_TX_FRM_NR : lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted.
bits : 6 - 13 (8 bit)
access : read-write

LMAC_MANUAL_PTI : lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set
bits : 8 - 19 (12 bit)
access : read-write

LMAC_MANUAL_PHY_ATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write

LMAC_MANUAL_PHY_ATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write

LMAC_MANUAL_PHY_ATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write

LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write

LMAC_MANUAL_PHY_ATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write

LMAC_MANUAL_OS_REG

One shot register triggers transmission in manual mode
address_offset : 0x100A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMAC_MANUAL_TX_START : One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode
bits : 0 - 0 (1 bit)
access : write-only

LMAC_MANUAL_STATUS_REG

Lmac status register in manual mode
address_offset : 0x100A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMAC_MANUAL_CCA_STAT : lmac_manual_cca_stat shows the status of the CCA_STAT
bits : 0 - 0 (1 bit)
access : read-only

LMAC_MANUAL_ED_STAT : lmac_manual_ed_stat shows the status of the ED_STAT interface signal.
bits : 8 - 23 (16 bit)
access : read-only

LMAC_CONTROL_7_REG

Lmac control register
address_offset : 0x10100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACWUPERIOD : Wake-up duration in symbols.
bits : 0 - 15 (16 bit)
access : read-write

MACCSLSAMPLEPERIOD : When performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbols).
bits : 16 - 47 (32 bit)
access : read-write

LMAC_CONTROL_8_REG

Lmac control register
address_offset : 0x10104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACCSLSTARTSAMPLETIME : The control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbols) when to start listening (called and quot idle listening and quot ).
bits : 0 - 31 (32 bit)
access : read-write

LMAC_CONTROL_9_REG

Lmac control register
address_offset : 0x10108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACCSLDATAPERIOD : After the wake-up sequence a frame is expected, the receiver will be enabled for at least a period of macCSLdataPeriod (in symbols).
bits : 0 - 15 (16 bit)
access : read-write

MACCSLFRAMEPENDINGWAITT : If a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbols) after the end of the received frame. The time the Enhanced ACK transmission lasts (if applicable) is included in this time.
bits : 16 - 47 (32 bit)
access : read-write

LMAC_CONTROL_10_REG

Lmac control register
address_offset : 0x1010C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACWURZCORRECTION : This register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 sym).
bits : 0 - 7 (8 bit)
access : read-write

MACCSLMARGINRZ : The UMAC can set the margin for the expected frame by control register macCSLmarginRZ (in 10 sym). So the LMAC will make sure the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time
bits : 16 - 35 (20 bit)
access : read-write

MACRZZEROVAL : If the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame
bits : 28 - 59 (32 bit)
access : read-write

SECURITY_0_REG

Security register
address_offset : 0x10110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECTXRXN : See register and quot secEntry and quot
bits : 1 - 2 (2 bit)
access : read-write

SECENTRY : The UMAC shall indicate by control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0').
bits : 8 - 19 (12 bit)
access : read-write

SECALENGTH : The length of the a_data is indicated by control register secAlength. The end of the a_data is the start point of the m_data. (So secAlength must also be set if security level==4)
bits : 16 - 38 (23 bit)
access : read-write

SECMLENGTH : The length of the m_data is indicated by control register secMlength.
bits : 24 - 54 (31 bit)
access : read-write

SECENCDECN : The control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data.
bits : 31 - 62 (32 bit)
access : read-write

SECURITY_1_REG

Security register
address_offset : 0x10114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECAUTHFLAGS : Register secAuthFlags contains the authentication flags fields. bit[7] is '0' bit[6] is and quot A_data present and quot bit[5:3]: 3-bit security level of m_data bit[2:0]: 3-bit security level of a_data.
bits : 0 - 7 (8 bit)
access : read-write

SECENCRFLAGS : Register secEncrFlags contain the encryption flags field. Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'.
bits : 8 - 23 (16 bit)
access : read-write

SECKEY_0_REG

Seckey register
address_offset : 0x10118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECKEY_0 : Registers secKey[0..3] contain the key to be used.
bits : 0 - 31 (32 bit)
access : read-write

SECKEY_1_REG

Seckey register
address_offset : 0x1011C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECKEY_1 : See register and quot secKey_0 and quot
bits : 0 - 31 (32 bit)
access : read-write

SECKEY_2_REG

SecKey register
address_offset : 0x10120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECKEY_2 : See register and quot secKey_0 and quot
bits : 0 - 31 (32 bit)
access : read-write

SECKEY_3_REG

Seckey register
address_offset : 0x10124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECKEY_3 : See register and quot secKey_0 and quot
bits : 0 - 31 (32 bit)
access : read-write

SECNONCE_0_REG

Nonce register used for encryption/decryption
address_offset : 0x10128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECNONCE_0 : Register secNonce[0..3] contains the Nonce to be used for encryption/decryption.
bits : 0 - 31 (32 bit)
access : read-write

SECNONCE_1_REG

Nonce register used for encryption/decryption
address_offset : 0x1012C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECNONCE_1 : See register and quot Nonce_0 and quot
bits : 0 - 31 (32 bit)
access : read-write

SECNONCE_2_REG

Nonce register used for encryption/decryption
address_offset : 0x10130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECNONCE_2 : See register and quot Nonce_0 and quot
bits : 0 - 31 (32 bit)
access : read-write

SECNONCE_3_REG

Nonce register used for encryption/decryption
address_offset : 0x10134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECNONCE_3 : See register and quot Nonce_0 and quot
bits : 0 - 7 (8 bit)
access : read-write

SECURITY_OS_REG

One shot register to start encryption/decryption
address_offset : 0x10138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECABORT : See register and quot Nonce_0 and quot
bits : 0 - 0 (1 bit)
access : write-only

SECSTART : One_shot register to start the encryption, decryption and authentication support task.
bits : 1 - 2 (2 bit)
access : write-only

SECURITY_STATUS_REG

Security status register
address_offset : 0x10140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECBUSY : Register and quot secBusy and quot indicates if the encryption/decryption process is still running.
bits : 0 - 0 (1 bit)
access : read-only

SECAUTHFAIL : In case of decryption, the status bit secAuthFail will be set when the authentication has failed.
bits : 1 - 2 (2 bit)
access : read-only

SECURITY_EVENT_REG

security event register
address_offset : 0x10150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECREADY_E : The Event bit secReady_e is set when the authentication process is ready (i.e. secBusy is cleared). This Event shall contribute to the gen_irq.
bits : 0 - 0 (1 bit)
access : read-write

SECURITY_EVENTMASK_REG

security event mask register
address_offset : 0x10154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SECREADY_M : Mask bit for event and quot secReady_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TSCH_CONTROL_0_REG

Lmac tsch control register
address_offset : 0x10160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSTXACKDELAY : End of Rx frame to start of Ack
bits : 0 - 15 (16 bit)
access : read-write

MACTSRXWAIT : The times to wait for start of frame
bits : 16 - 47 (32 bit)
access : read-write

TSCH_CONTROL_1_REG

Lmac tsch control register
address_offset : 0x10164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSRXTX : The time between the CCA and the TX of a frame
bits : 0 - 15 (16 bit)
access : read-write

TSCH_CONTROL_2_REG

Lmac tsch control register
address_offset : 0x10168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTSRXACKDELAY : End of frame to when the transmitter shall listen for Acknowledgement
bits : 0 - 15 (16 bit)
access : read-write

MACTSACKWAIT : The minimum time to wait for start of an Acknowledgement
bits : 16 - 47 (32 bit)
access : read-write

PHY_PARAMETERS_0_REG

Lmac PHY parameter register
address_offset : 0x10180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXBITPOS_0 : Control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. Note1 that this is a conversion from rx DPHY interface to the internal data byte So for(n=7 n>=0 n--) rx_data(n) = dphy_bit(tx_BitPos(n)) endfor Note2 that rxBitPos and txBitPos must have inverse functions.
bits : 0 - 2 (3 bit)
access : read-write

RXBITPOS_1 : See rxBitPos_0
bits : 4 - 10 (7 bit)
access : read-write

RXBITPOS_2 : See rxBitPos_0
bits : 8 - 18 (11 bit)
access : read-write

RXBITPOS_3 : See rxBitPos_0
bits : 12 - 26 (15 bit)
access : read-write

RXBITPOS_4 : See rxBitPos_0
bits : 16 - 34 (19 bit)
access : read-write

RXBITPOS_5 : See rxBitPos_0
bits : 20 - 42 (23 bit)
access : read-write

RXBITPOS_6 : See rxBitPos_0
bits : 24 - 50 (27 bit)
access : read-write

RXBITPOS_7 : See rxBitPos_0
bits : 28 - 58 (31 bit)
access : read-write

PHY_PARAMETERS_1_REG

Lmac PHY parameter register
address_offset : 0x10184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBITPOS_0 : Control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. Note1 that this is a conversion from internal data byte to the DPHY interface. So for(n=7 n>=0 n--) tx_dphy_bit(n) = tx_data(tx_BitPos(n)) endfor Note2 that txBitPos and rxBitPos must have inverse functions.
bits : 0 - 2 (3 bit)
access : read-write

TXBITPOS_1 : See txBitPos_0
bits : 4 - 10 (7 bit)
access : read-write

TXBITPOS_2 : See txBitPos_0
bits : 8 - 18 (11 bit)
access : read-write

TXBITPOS_3 : See txBitPos_0
bits : 12 - 26 (15 bit)
access : read-write

TXBITPOS_4 : See txBitPos_0
bits : 16 - 34 (19 bit)
access : read-write

TXBITPOS_5 : See txBitPos_0
bits : 20 - 42 (23 bit)
access : read-write

TXBITPOS_6 : See txBitPos_0
bits : 24 - 50 (27 bit)
access : read-write

TXBITPOS_7 : See txBitPos_0
bits : 28 - 58 (31 bit)
access : read-write

PHY_PARAMETERS_2_REG

Lmac PHY parameter register
address_offset : 0x10188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYTXSTARTUP : Phy wait time before transmission
bits : 0 - 7 (8 bit)
access : read-write

PHYTXLATENCY : Phy delay between DPHY i/f and air
bits : 8 - 23 (16 bit)
access : read-write

PHYTXFINISH : Phy wait time before deasserting TX_EN
bits : 16 - 39 (24 bit)
access : read-write

PHYTRXWAIT : Phy wait time between TX_EN/RX_EN
bits : 24 - 55 (32 bit)
access : read-write

PHY_PARAMETERS_3_REG

Lmac PHY parameter register
address_offset : 0x1018C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PHYRXSTARTUP : Phy wait time before receiving
bits : 0 - 7 (8 bit)
access : read-write

PHYRXLATENCY : Phy delay between air and DPHY i/f
bits : 8 - 23 (16 bit)
access : read-write

PHYENABLE : Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal phy_en. (resolution: ~s).
bits : 16 - 39 (24 bit)
access : read-write

RX_CONTROL_0_REG

Receive control register
address_offset : 0x10200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGRXTRANSPARENTMODE : If set, Rx pipe is fully set in transparent mode (for debug purpose).
bits : 0 - 0 (1 bit)
access : read-write

RXBEACONONLY : If set, only Beacons frames are accepted
bits : 1 - 2 (2 bit)
access : read-write

RXCOORDREALIGNONLY : If set, only Coordinator Realignment frames are accepted
bits : 2 - 4 (3 bit)
access : read-write

RX_READ_BUF_PTR : Indication where new data will be read All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values.
bits : 3 - 9 (7 bit)
access : read-write

DISRXFRMPENDINGCA : Whan the control register DisRxFrmPendingCa is set, the notification of the received FP bit to the LMAC Controller is disabled.
bits : 7 - 14 (8 bit)
access : read-write

DISRXACKREQUESTCA : When the control register DisRxAckRequestca is set all consequent actions for a received Acknowledge Request bit are disabled.
bits : 8 - 16 (9 bit)
access : read-write

MACALWAYSPASSCRCERROR : If set, a FCS error will not drop the frame
bits : 9 - 18 (10 bit)
access : read-write

DISDATAREQUESTCA : When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled.
bits : 10 - 20 (11 bit)
access : read-write

MACALWAYSPASSRESFRAMEVERSION : If set, a packet with a reserved FrameVersion shall not be dropped
bits : 11 - 22 (12 bit)
access : read-write

MACALWAYSPASSWRONGDPANID : If register macAlwaysPassWrongDPANId is set, packet with a wrong Destiantion PanID will not be dropped. However, in case of an FCS error, the packet is dropped.
bits : 12 - 24 (13 bit)
access : read-write

MACALWAYSPASSWRONGDADDR : If set, a packet with a wrong DAddr is not dropped
bits : 13 - 26 (14 bit)
access : read-write

MACALWAYSPASSBEACONWRONGPANID : If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly.
bits : 14 - 28 (15 bit)
access : read-write

MACALWAYSPASSTOPANCOORDINATOR : When the control register macAlwaysPassToPanCoordinator is set, the frame is not dropped due to a span_coord_error. However, in case of an FCS error, the packet is dropped.
bits : 15 - 30 (16 bit)
access : read-write

MACALWAYSPASSFRMTYPE : The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. If a bit is set, the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. Example: if bit 1 is set, Frame Type 1 shall not be dropped. The error shall be reported in the Rx meta data
bits : 16 - 39 (24 bit)
access : read-write

MACALWAYSPASSWAKEUP : If the control register macAlwaysPassWakeUp is set, received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller.
bits : 24 - 48 (25 bit)
access : read-write

MACPASSWAKEUP : If set, WakeUp frames will not be reported but will be put into the Rx buffer.
bits : 25 - 50 (26 bit)
access : read-write

MACIMPLICITBROADCAST : If set, Frame Version 2 frames without Daddr or DPANId shall be accepted.
bits : 26 - 52 (27 bit)
access : read-write

DISRXACKRECEIVEDCA : If set, the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame
bits : 27 - 54 (28 bit)
access : read-write

RX_EVENT_REG

Receive event register
address_offset : 0x10204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXSOF_E : Set when RX_SOF has been detected.
bits : 0 - 0 (1 bit)
access : read-write

RX_OVERFLOW_E : Indicates that the Rx packet buffer has an overflowl
bits : 1 - 2 (2 bit)
access : read-write

RX_BUF_AVAIL_E : Indicates that a new packet is received
bits : 2 - 4 (3 bit)
access : read-write

RXBYTE_E : Indicates the first byte of a new packet is received
bits : 3 - 6 (4 bit)
access : read-write

RX_MASK_REG

Receive event mask register
address_offset : 0x10208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RXSOF_M : Mask bit for event and quot RxSof_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

RX_OVERFLOW_M : Mask bit for event and quot rx_overflow_e and quot .
bits : 1 - 2 (2 bit)
access : read-write

RX_BUF_AVAIL_M : Mask bit for event and quot rx_buf_avail_e and quot .
bits : 2 - 4 (3 bit)
access : read-write

RXBYTE_M : Mask bit for event and quot rxbyte_e and quot .
bits : 3 - 6 (4 bit)
access : read-write

RX_STATUS_REG

Receive status register
address_offset : 0x1020C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_BUFF_IS_FULL : Indicates that the Rx packet buffer is full
bits : 0 - 0 (1 bit)
access : read-only

RX_WRITE_BUF_PTR : Indication where new data will be written. All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values.
bits : 1 - 5 (5 bit)
access : read-only

SYMBOLTIMESNAPSHOTVAL_REG

Value timestamp generator
address_offset : 0x10210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYMBOLTIMESNAPSHOTVAL : The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator.
bits : 0 - 31 (32 bit)
access : read-only

RX_STATUS_DELTA_REG

Receive status delta register
address_offset : 0x10220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_BUFF_IS_FULL_D : Delta bit of status and quot rx_buff_is_full and quot
bits : 0 - 0 (1 bit)
access : read-write

RX_STATUS_MASK_REG

Receive status delta mask register
address_offset : 0x10224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RX_BUFF_IS_FULL_M : Mask bit of status and quot rx_buff_is_full and quot
bits : 0 - 0 (1 bit)
access : read-write

TX_CONTROL_0_REG

Transmit control register
address_offset : 0x10240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBGTXTRANSPARENTMODE : If 1, the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose).
bits : 0 - 0 (1 bit)
access : read-write

MACMAXBE : Maximum Backoff Exponent (range 3-8)
bits : 4 - 11 (8 bit)
access : read-write

MACMINBE : Minimum Backoff Exponent (range 0-macMaxBE)
bits : 8 - 19 (12 bit)
access : read-write

MACMAXCSMABACKOFFS : Maximum number of CSMA-CA backoffs (range 0-5)
bits : 12 - 26 (15 bit)
access : read-write

CE_REG

Selection register events
address_offset : 0x10250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTDF_CE : Composite serveice request from ftdf macro (see FR0400 in v40.100.2.41.pdf) Bit 0 = unused Bit 1 = rx interrupts Bit 2 = unused Bit 3 = miscelaneous interrupts Bit 4 = tx interrupts Bit 5 = Reserved
bits : 0 - 5 (6 bit)
access : read-only

CM_REG

Mask selection register events
address_offset : 0x10254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FTDF_CM : mask bits for ftf_ce
bits : 0 - 5 (6 bit)
access : read-write

SYNCTIMESTAMPTHR_REG

Threshold timestamp generator
address_offset : 0x10304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCTIMESTAMPTHR : Threshold for synchronize TS gen. Note that due to implementation this register may only be written once per two LP_CLK periods.
bits : 0 - 31 (32 bit)
access : read-write

SYNCTIMESTAMPVAL_REG

Value timestamp generator
address_offset : 0x10308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCTIMESTAMPVAL : Value to sync TS gen with.
bits : 0 - 31 (32 bit)
access : read-write

TIMER_CONTROL_1_REG

Timer control register
address_offset : 0x1030C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCTIMESTAMPENA : If set, the TimeStampThr is enabled to generate a sync of the TS gen.
bits : 1 - 2 (2 bit)
access : read-write

MACTXSTDACKFRMCNT_REG

Transmitted acknowledgment frames
address_offset : 0x10310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACTXSTDACKFRMCNT : Standard Acknowledgment frames transmitted
bits : 0 - 31 (32 bit)
access : read-only

MACRXSTDACKFRMOKCNT_REG

Received acknowledgment frames
address_offset : 0x10314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRXSTDACKFRMOKCNT : Standard Acknowledgment frames received
bits : 0 - 31 (32 bit)
access : read-only

MACRXADDRFAILFRMCNT_REG

Discarded frames register
address_offset : 0x10318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRXADDRFAILFRMCNT : Frames discarded due to incorrect address or PAN Id
bits : 0 - 31 (32 bit)
access : read-only

MACRXUNSUPFRMCNT_REG

Unsupported frames register
address_offset : 0x1031C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACRXUNSUPFRMCNT : Frames which do pass the checks but are not supported
bits : 0 - 31 (32 bit)
access : read-only

SYNCTIMESTAMPPHASEVAL_REG

Timestamp phase value regsiter
address_offset : 0x10320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCTIMESTAMPPHASEVAL : Value to sync TS gen phase within a symbol with. Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock).
bits : 0 - 7 (8 bit)
access : read-write

MACFCSERRORCOUNT_REG

Lmac FCS error register
address_offset : 0x10340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACFCSERRORCOUNT : The number of received frames that were discarded due to an incorrect FCS.
bits : 0 - 31 (32 bit)
access : read-only

LMACRESET_REG

Lmax reset register
address_offset : 0x10360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LMACRESET_CONTROL : LmacReset_control: A '1' Resets LMAC Controller (for debug and MLME-reset)
bits : 0 - 0 (1 bit)
access : write-only

LMACRESET_RX : LmacReset_rx: A '1' Resets LMAC rx pipeline (for debug and MLME-reset)
bits : 1 - 2 (2 bit)
access : write-only

LMACRESET_TX : LmacReset_tx: A '1' Resets LMAC tx pipeline (for debug and MLME-reset)
bits : 2 - 4 (3 bit)
access : write-only

LMACRESET_AHB : LmacReset_ahb: A '1' Resets LMAC ahb interface (for debug and MLME-reset)
bits : 3 - 6 (4 bit)
access : write-only

LMACRESET_OREG : LmacReset_oreg: A '1' Resets LMAC on_off regmap (for debug and MLME-reset) #$LmacReset_areg@on_off_regmap #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset)
bits : 4 - 8 (5 bit)
access : write-only

LMACRESET_TSTIM : LmacReset_tstim: A '1' Resets LMAC timestamp timer (for debug and MLME-reset)
bits : 6 - 12 (7 bit)
access : write-only

LMACRESET_SEC : LmacReset_sec: A '1' Resets LMAC security (for debug and MLME-reset) #$LmacReset_wutim@on_off_regmap #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset)
bits : 7 - 14 (8 bit)
access : write-only

LMACRESET_COUNT : LmacReset_count: A '1' Resets LMAC mac counters (for debug and MLME-reset)
bits : 9 - 18 (10 bit)
access : write-only

LMACRESET_TIMCTRL : LmacReset_count: A '1' Resets LMAC timing control block (for debug and MLME-reset)
bits : 10 - 20 (11 bit)
access : write-only

LMACGLOBRESET_COUNT : If set, the LMAC performance and traffic counters will be reset. Use this register for functionally reset these counters.
bits : 16 - 32 (17 bit)
access : write-only

SYMBOLTIMETHR_REG

Symboltime threshold register 1
address_offset : 0x10380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYMBOLTIMETHR : Symboltime Threshold to generate a general interrupt
bits : 0 - 31 (32 bit)
access : read-write

SYMBOLTIME2THR_REG

Symboltime threshold register 2
address_offset : 0x10384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYMBOLTIME2THR : Symboltime 2 Threshold to generate a general interrupt
bits : 0 - 31 (32 bit)
access : read-write

DEBUGCONTROL_REG

Debug control register
address_offset : 0x10390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBG_RX_INPUT : If set, the Rx debug interface will be selected as input for the Rx pipeline.
bits : 8 - 16 (9 bit)
access : read-write

TXBYTE_E_REG

Transmit first byte register
address_offset : 0x10394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBYTE_E : Indicates the first byte of a frame is transmitted
bits : 0 - 0 (1 bit)
access : read-write

TX_LAST_SYMBOL_E : Indicates the last symbol of a frame is transmitted
bits : 1 - 2 (2 bit)
access : read-write

TXBYTE_M_REG

Transmit first byte mask register
address_offset : 0x10398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TXBYTE_M : Mask bit for event and quot txbyte_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TX_LAST_SYMBOL_M : Mask bit for event and quot tx_last_symbol_e and quot .
bits : 1 - 2 (2 bit)
access : read-write

TX_FLAG_S_0_REG

Transmit packet ready for transmission register 0
address_offset : 0x10400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_STAT : Packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only

TX_FLAG_CLEAR_E_0_REG

Clear flag register 0
address_offset : 0x10404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_E : When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set.
bits : 0 - 0 (1 bit)
access : read-write

TX_FLAG_CLEAR_M_0_REG

Mask flag register 0
address_offset : 0x10408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_M : Mask bit for event and quot tx_flag_clear_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TX_PRIORITY_0_REG

Transmit priority register 0
address_offset : 0x10410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_PRIORITY : Priority of packet
bits : 0 - 3 (4 bit)
access : read-write

ISWAKEUP : A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame.
bits : 4 - 8 (5 bit)
access : read-write

TX_FLAG_S_1_REG

Transmit packet ready for transmission register 1
address_offset : 0x10420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_STAT : Packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only

TX_FLAG_CLEAR_E_1_REG

Clear flag register 1
address_offset : 0x10424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_E : When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set.
bits : 0 - 0 (1 bit)
access : read-write

TX_FLAG_CLEAR_M_1_REG

Mask flag register 1
address_offset : 0x10428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_M : Mask bit for event and quot tx_flag_clear_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TX_PRIORITY_1_REG

Transmit priority register 1
address_offset : 0x10430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_PRIORITY : Priority of packet
bits : 0 - 3 (4 bit)
access : read-write

TX_FLAG_S_2_REG

Transmit packet ready for transmission register 2
address_offset : 0x10440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_STAT : Packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only

TX_FLAG_CLEAR_E_2_REG

Clear flag register 2
address_offset : 0x10444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_E : When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set.
bits : 0 - 0 (1 bit)
access : read-write

TX_FLAG_CLEAR_M_2_REG

Clear flag register 2
address_offset : 0x10448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_M : Mask bit for event and quot tx_flag_clear_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TX_PRIORITY_2_REG

Transmit priority register 2
address_offset : 0x10450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_PRIORITY : Priority of packet
bits : 0 - 3 (4 bit)
access : read-write

TX_FLAG_S_3_REG

Transmit packet ready for transmission register 3
address_offset : 0x10460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_STAT : Packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only

TX_FLAG_CLEAR_E_3_REG

Clear flag register 3
address_offset : 0x10464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_E : When the LMAC clears the tx_flag_stat status event bit tx_flag_clear_e is set.
bits : 0 - 0 (1 bit)
access : read-write

TX_FLAG_CLEAR_M_3_REG

Clear flag register 3
address_offset : 0x10468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR_M : Mask bit for event and quot tx_flag_clear_e and quot .
bits : 0 - 0 (1 bit)
access : read-write

TX_PRIORITY_3_REG

Transmit priority register 3
address_offset : 0x10470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_PRIORITY : Priority of packet
bits : 0 - 3 (4 bit)
access : read-write

TX_SET_OS_REG

One shot register to set flag
address_offset : 0x10480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_SET : To set tx_flag_stat
bits : 0 - 3 (4 bit)
access : write-only

TX_CLEAR_OS_REG

One shot register to clear flag
address_offset : 0x10484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FLAG_CLEAR : To clear tx_flag_stat
bits : 0 - 3 (4 bit)
access : write-only

WAKEUPINTTHR_REG

Treshold value Wakeup timer
address_offset : 0x11000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUPINTTHR : Threshold for wake-up interrupt.
bits : 0 - 31 (32 bit)
access : read-write

WAKEUP_CONTROL_REG

Wakeup timer vcontrol register
address_offset : 0x11004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKEUPTIMERENABLE : A '1' Enables the wakeup timer. Note that in on_off_regmap, the register WakeupTimerEnableStatus shows the status of this register after being clocked by LP_CLK. Checking this register can be used as indication for software that this bit is effective in the desing.
bits : 0 - 0 (1 bit)
access : read-write

WAKEUPENABLE : If set, the WakeUpIntThr is enabled to generate an interrupt.
bits : 1 - 2 (2 bit)
access : read-write

TX_FIFO_3_0_REG

Address transmit fifo 3
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported.
bits : 0 - 31 (32 bit)
access : read-write

TX_META_DATA_0_0_REG

Transmit metadata register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FRAME_LENGTH : Frame length
bits : 0 - 6 (7 bit)
access : read-write

PHYATTR_DEM_PTI : DEM packet information.
bits : 7 - 17 (11 bit)
access : read-write

PHYATTR_CN : Channel Number.
bits : 11 - 25 (15 bit)
access : read-write

PHYATTR_CALCAP : CalCap value.
bits : 15 - 33 (19 bit)
access : read-write

PHYATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 19 - 40 (22 bit)
access : read-write

PHYATTR_HSI : HighSide injection.
bits : 22 - 44 (23 bit)
access : read-write

FRAMETYPE : Data/Cmd/Ack etc. Also indicate wakeup frame
bits : 23 - 48 (26 bit)
access : read-write

CSMACA_ENA : Indicates whether a CSMA-CA is required for the transmission of this packet.
bits : 26 - 52 (27 bit)
access : read-write

ACKREQUEST : Indicates whether an acknowledge is expected from the recipient of this packet.
bits : 28 - 56 (29 bit)
access : read-write

CRC16_ENA : Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16
bits : 30 - 60 (31 bit)
access : read-write

TX_META_DATA_1_0_REG

Transmit metadata register 0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MACSN : Sequence Number of this packet.
bits : 0 - 7 (8 bit)
access : read-write

TX_META_DATA_0_1_REG

Transmit metadata register 1
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0