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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection :

Registers

TIMER0_CTRL_REG

PWM3_END_CYCLE

PWM4_END_CYCLE

TRIPLE_PWM_FREQUENCY

TRIPLE_PWM_CTRL_REG

BREATH_CFG_REG

BREATH_DUTY_MAX_REG

BREATH_DUTY_MIN_REG

BREATH_CTRL_REG

TIMER0_ON_REG

TIMER0_RELOAD_M_REG

TIMER0_RELOAD_N_REG

PWM2_START_CYCLE

PWM3_START_CYCLE

PWM4_START_CYCLE

PWM2_END_CYCLE


TIMER0_CTRL_REG

Timer0 control register
address_offset : 0x0 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_CTRL_REG TIMER0_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_CTRL TIM0_CLK_SEL TIM0_CLK_DIV PWM_MODE

TIM0_CTRL : 0 = Timer0 is off and in reset state. 1 = Timer0 is running.
bits : 0 - 0 (1 bit)
access : read-write

TIM0_CLK_SEL : 1 = Timer0 uses fast clock frequency. 0 = Timer0 uses 32 kHz (slow) clock frequency.
bits : 1 - 2 (2 bit)
access : read-write

TIM0_CLK_DIV : 1 = Timer0 uses selected clock frequency as is. 0 = Timer0 uses selected clock frequency divided by 10. Note that this applies only to the ON-counter.
bits : 2 - 4 (3 bit)
access : read-write

PWM_MODE : 0 = PWM signals are '1' during high time. 1 = PWM signals send out the (fast) clock divided by 2 during high time.
bits : 3 - 6 (4 bit)
access : read-write


PWM3_END_CYCLE

Defines end Cycle for PWM3
address_offset : 0x10 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3_END_CYCLE PWM3_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


PWM4_END_CYCLE

Defines end Cycle for PWM4
address_offset : 0x12 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM4_END_CYCLE PWM4_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1
bits : 0 - 13 (14 bit)
access : read-write


TRIPLE_PWM_FREQUENCY

Defines the PMW2,3,4 frequency
address_offset : 0x14 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_FREQUENCY TRIPLE_PWM_FREQUENCY read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FREQ

FREQ : Freq for PWM 2 3 4, period = timer_clk * ( FREQ+1)
bits : 0 - 13 (14 bit)
access : read-write


TRIPLE_PWM_CTRL_REG

PWM 2 3 4 Control register
address_offset : 0x16 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIPLE_PWM_CTRL_REG TRIPLE_PWM_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIPLE_PWM_ENABLE SW_PAUSE_EN HW_PAUSE_EN

TRIPLE_PWM_ENABLE : '1' = PWM 2 3 4 is enabled
bits : 0 - 0 (1 bit)
access : read-write

SW_PAUSE_EN : '1' = PWM 2 3 4 is paused
bits : 1 - 2 (2 bit)
access : read-write

HW_PAUSE_EN : '1' = HW can pause PWM 2,3,4
bits : 2 - 4 (3 bit)
access : read-write


BREATH_CFG_REG

Breath configuration register
address_offset : 0x18 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREATH_CFG_REG BREATH_CFG_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRTH_DIV BRTH_STEP

BRTH_DIV : Defines the division factor of the system clock to get to the PWM frequency.( = Sys Clock / (value+1)
bits : 0 - 7 (8 bit)
access : read-write

BRTH_STEP : Defines the number of PWM periods minus 1, duty cycle will be changed
bits : 8 - 23 (16 bit)
access : read-write


BREATH_DUTY_MAX_REG

Breath max duty cycle register
address_offset : 0x1A Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREATH_DUTY_MAX_REG BREATH_DUTY_MAX_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRTH_DUTY_MAX

BRTH_DUTY_MAX : Defines the maximum duty cycle of the PWM breath function. Duty cycle = value / (brth_div+1)
bits : 0 - 7 (8 bit)
access : read-write


BREATH_DUTY_MIN_REG

Breath min duty cycle register
address_offset : 0x1C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREATH_DUTY_MIN_REG BREATH_DUTY_MIN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRTH_DUTY_MIN

BRTH_DUTY_MIN : Defines the minimum duty cycle of the PWM breath function. Duty cycle = value / (brth_div+1)
bits : 0 - 7 (8 bit)
access : read-write


BREATH_CTRL_REG

Breath control register
address_offset : 0x1E Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BREATH_CTRL_REG BREATH_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BRTH_EN BRTH_PWM_POL

BRTH_EN : '1' enable the Breath operation
bits : 0 - 0 (1 bit)
access : read-write

BRTH_PWM_POL : Define the output polarity.
bits : 1 - 2 (2 bit)
access : read-write


TIMER0_ON_REG

Timer0 on control register
address_offset : 0x2 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_ON_REG TIMER0_ON_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_ON

TIM0_ON : Timer0 On reload value: If read the actual counter value ON_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


TIMER0_RELOAD_M_REG

16 bits reload value for Timer0
address_offset : 0x4 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_RELOAD_M_REG TIMER0_RELOAD_M_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_M

TIM0_M : Timer0 'high' reload valueIf read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


TIMER0_RELOAD_N_REG

16 bits reload value for Timer0
address_offset : 0x6 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER0_RELOAD_N_REG TIMER0_RELOAD_N_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM0_N

TIM0_N : Timer0 'low' reload value: If read the actual counter value T0_CNTer is returned
bits : 0 - 15 (16 bit)
access : write-only


PWM2_START_CYCLE

Defines start Cycle for PWM2
address_offset : 0x8 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2_START_CYCLE PWM2_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM3_START_CYCLE

Defines start Cycle for PWM3
address_offset : 0xA Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM3_START_CYCLE PWM3_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM4_START_CYCLE

Defines start Cycle for PWM4
address_offset : 0xC Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM4_START_CYCLE PWM4_START_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 START_CYCLE

START_CYCLE : Define the cycle in which the PWM becomes high. if start_cycle larger than freq or end and start are equal, pwm out is always 0
bits : 0 - 13 (14 bit)
access : read-write


PWM2_END_CYCLE

Defines end Cycle for PWM2
address_offset : 0xE Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWM2_END_CYCLE PWM2_END_CYCLE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 END_CYCLE

END_CYCLE : Define the cycle in which the PWM becomes low. If end cycle larger then freq pwm and start cycle not larger then freq pwm, output is always 1
bits : 0 - 13 (14 bit)
access : read-write



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