FREQ_CARRIER_ON_REG

REPEAT_FIFO_REG

IRQ_STATUS_REG

FREQ_CARRIER_OFF_REG

LOGIC_ONE_TIME_REG

LOGIC_ZERO_TIME_REG

CTRL_REG

STATUS_REG

REPEAT_TIME_REG

MAIN_FIFO_REG

IR_FREQ_CARRIER_ON : Defines the carrier signal high duration in IR_clk cycles. 0x0 is not allowed as a value.
bits : 0 - 9 (10 bit)
access : read-write

IR_REPEAT_FIFO_DATA : Repeat FIFO data write port
bits : 0 - 15 (16 bit)
access : write-only

IR_IRQ_ACK : When read Interrupt line is cleared
bits : 0 - 0 (1 bit)
access : read-only

IR_FREQ_CARRIER_OFF : Defines the carrier signal low duration in IR_clk cycles
bits : 0 - 9 (10 bit)
access : read-write

IR_LOGIC_ONE_SPACE : Defines the space duration in carrier clock cycles. Must be >0
bits : 0 - 7 (8 bit)
access : read-write

IR_LOGIC_ONE_MARK : Defines the mark duration in carrier clock cycles. Must be >0
bits : 8 - 23 (16 bit)
access : read-write

IR_LOGIC_ZERO_SPACE : Defines the space duration in carrier clock cycles. Must be >0
bits : 0 - 7 (8 bit)
access : read-write

IR_LOGIC_ZERO_MARK : Defines the mark duration in carrier clock cycles. Must be >0
bits : 8 - 23 (16 bit)
access : read-write

IR_CODE_FIFO_RESET : 1 = Flush Code FIFO (auto clear)
bits : 0 - 0 (1 bit)
access : write-only

IR_REP_FIFO_RESET : 1 = Flush Repeat FIFO (auto clear)
bits : 1 - 2 (2 bit)
access : write-only

IR_ENABLE : 1 = IR block is enabled 0 = IR block is disabled and at reset state. This also resets the pointers at the FIFOs
bits : 2 - 4 (3 bit)
access : read-write

IR_TX_START : 1 = IR transmits a command 0 = IR is stopped While this bit is 1 and SW programs it to 0, the code FIFO will be flushed automatically.
bits : 3 - 6 (4 bit)
access : read-write

IR_REPEAT_TYPE : 1 = repeat command is defined at Repeat FIFO 0 = repeat command is defined at Code FIFO
bits : 4 - 8 (5 bit)
access : read-write

IR_INVERT_OUTPUT : 1 = IR output is inverted 0 = IR output is not inverted
bits : 5 - 10 (6 bit)
access : read-write

IR_LOGIC_ZERO_FORMAT : 1 = Logic zero starts with a Space followed by a Mark 0 = Logic zero starts with a Mark followed by a Space
bits : 6 - 12 (7 bit)
access : read-write

IR_LOGIC_ONE_FORMAT : 1 = Logic one starts with a Space followed by a Mark 0 = Logic one starts with a Mark followed by a Space
bits : 7 - 14 (8 bit)
access : read-write

IR_IRQ_EN : 1 = Enables the interrupt generation upon TX completion 0 = masks out the interrupt generation upon TX completion
bits : 8 - 16 (9 bit)
access : read-write

IR_CODE_FIFO_WRDS : Contains the amount of words in Code FIFO (updated only on write)
bits : 0 - 5 (6 bit)
access : read-only

IR_REP_FIFO_WRDS : Contains the amount of words in Repeat FIFO (updated only on write)
bits : 6 - 15 (10 bit)
access : read-only

IR_BUSY : 1 = IR generator is busy sending a message 0 = IR generator is idle
bits : 10 - 20 (11 bit)
access : read-only

IR_REPEAT_TIME : Defines the repeat time in carrier clock cycles. The repeat timer will start counting from the start of the command and will trigger the output of the same command residing in the Code FIFO or the special command residing in the Repeat FIFO as soon as it expires.
bits : 0 - 15 (16 bit)
access : read-write

IR_CODE_FIFO_DATA : Code FIFO data write port
bits : 0 - 15 (16 bit)
access : write-only