MODE_REG

CELADR_REG

NWORDS_REG

FFPRT_REG

FFRD_REG

PWORDL_REG

PWORDH_REG

TIM1_REG

TIM2_REG

PCTRL_REG

STAT_REG

AHBADR_REG

OTPC_MODE_MODE : Defines the mode of operation of the OTPC controller. The encoding of the modes is as follows: 000 - STBY mode 001 - MREAD mode 010 - MPROG mode 011 - AREAD mode 100 - APROG mode 101 - TBLANK mode 110 - TDEC mode 111 - TWR mode
bits : 0 - 2 (3 bit)
access : read-write

OTPC_MODE_USE_DMA : Selects the use of the dma, when the controller is configured in one of the modes: AREAD or APROG. 0 - The dma is not used. The data should be transferred from/to controller through the register OTPC_FFPRT_REG. 1 - The dma is used. The data transfers from/to controller are performed automatically, with the help of the internal DMA of the OTP controller. The AHB base address should be configured in register OTPC_AHBADR_REG, before the selection of one of the two modes: AREAD or APROG.
bits : 4 - 8 (5 bit)
access : read-write

OTPC_MODE_FIFO_FLUSH : By writing with 1, removes any content from the fifo. This bit returns automatically to value 0.
bits : 5 - 10 (6 bit)
access : read-write

OTPC_MODE_ERR_RESP_DIS : When is performed a read from the OTP memory in the MREAD mode, a double error is likely be detected during the retrieving of the data from the OTP. This error condition is always indicated in the status bit OTPC_STAT_REG[OTPC_STAT_RERROR]. However, the OTP controller has also the ability to indicates this error condition, by generating an ERROR response in the AHB bus. The generation of the ERROR response can be avoided with the help of this configuration bit. 0 - The OTP controller generates an ERROR response in the AHB bus, when a double error is detected during a reading in MREAD mode. The OTPC_STAT_REG[OTPC_STAT_RERROR] is also updated. The receiving of an ERROR response by the CPU causes a Hard Fault exception in the CPU. 1 - Only the OTPC_STAT_REG[OTPC_STAT_RERROR] is updated in a case of such error. The OTP controller will not generate an ERROR response in the AHB bus.
bits : 6 - 12 (7 bit)
access : read-write

OTPC_MODE_USE_SP_ROWS : Selects the memory area of the OTP cell that will be used. 0 - Uses the normal memory area of the OTP cell 1 - Uses the spare rows of the OTP cell This selection has meaning only if the mode of the controller is not TDEC and TWR. The controller should be in STBY mode, in order to takes into account this bit. The selection will take effect at the next mode that will be enabled.
bits : 8 - 16 (9 bit)
access : read-write

OTPC_MODE_RLD_RR_REQ : Write with 1 in order to be requested the reloading of the repair records. The reloading of the repair records will be performed at the next enabling of the OTP cell. That means that first the controller should be configured to the STBY mode and after should be activated any other mode. The hardware will clear this register, when the reloading will be performed. The reloading has meaning only if the repair records have been updated manually (MPROG mode).
bits : 9 - 18 (10 bit)
access : read-write

OTPC_CELADR : It represents an OTP address, where the OTP word width should be considered equal to 32-bits. The physical word width of the OTP memory is 72 bits. The 8-bits of them are used for the implementation of an error correcting code and are not available for the application. The remaining 64 bits of the physical word are available for the application. The OTPC_CELADDR can distinguish the upper 32 bits from the lower 32 bits of the available for the application bits of the OTP word. When OTPC_CELADDR[0] = 1 the address refers to the upper 32 bits of the physical OTP address OTPC_CELADDR[14:1]. The register is used during the modes: AREAD and APROG.
bits : 0 - 13 (14 bit)
access : read-write

OTPC_NWORDS : The number of words (minus one) for reading /programming during the AREAD/APROG mode. The width of the word should be considered equal to 32-bits. The value of the register remains unchanged, by the internal logic of the controller. During mirroring, this register reflects the current ammount of copied data.
bits : 0 - 13 (14 bit)
access : read-write

OTPC_FFPRT : Provides access to the fifo through an access port. Write to this register with the corresponding data, when the APROG mode is selected and the dma is disabled. Read from this register the corresponding data, when the AREAD mode is selected and the dma is disabled. The software should check the OTPCC_STAT_FWORDS register for the availability of data/space, before accessing the fifo.
bits : 0 - 31 (32 bit)
access : read-write

OTPC_FFRD : Contains the value which taken from the fifo, after a read of the OTPC_FFPRT_REG register.
bits : 0 - 31 (32 bit)
access : read-only

OTPC_PWORDL : Contains the lower 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode.
bits : 0 - 31 (32 bit)
access : read-write

OTPC_PWORDH : Contains the upper 32 bits that can be programmed with the help of the OTPC_PCTRL_REG, while the controller is in MPROG mode.
bits : 0 - 31 (32 bit)
access : read-write

OTPC_TIM1_CC_T_CADX : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 2us.It is used as a wait time each time where the OTP cell is enabled.
bits : 0 - 7 (8 bit)
access : read-write

OTPC_TIM1_CC_T_PW : The number of hclk_c clock periods (minus one) that give a time interval that is - at least higher than 4.8us - and lower than 5.2 us It is preferred the programmed value to give a time interval equal to 5us. It defines the duration of the programming pulse for every bit that written in the OTP cell.
bits : 8 - 23 (16 bit)
access : read-write

OTPC_TIM1_CC_T_1US : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 1us.
bits : 16 - 37 (22 bit)
access : read-write

OTPC_TIM1_CC_T_500NS : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 500ns
bits : 22 - 48 (27 bit)
access : read-write

OTPC_TIM1_CC_T_200NS : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 200ns.
bits : 27 - 57 (31 bit)
access : read-write

OTPC_TIM1_CC_T_25NS : The number of hclk_c clock periods (minus one) that give a time interval at least higher than 25ns.
bits : 31 - 62 (32 bit)
access : read-write

OTPC_TIM2_CC_STBY_THR : This register controls a power saving feature, which is applicable only in MREAD mode. The controller monitors the accesses in the OTP cell. If there is no access for more than OTPC_TIM2_CC_STBY_THR hclk_c clock cycles, the OTP cell goes to the standby while the controller itself remains in the MREAD mode. The OTP cell will be enabled again when will be applied a new read request. The enabling of the OTP cell has a cost of 2us (OTPC_TIM1_CC_T_CADX hclk_c clock cycles). When OTPC_TIM2_CC_STBY_THR = 0 the power saving feature is disabled and the OTP cell remains active while the controller is in MREAD mode.
bits : 0 - 9 (10 bit)
access : read-write

OTPC_TIM2_CC_T_BCHK : The number of hclk_c clock periods (minus one) that give a time interval between 100ns and 200ns. This time interval is used for the reading of the contents of the OTP cell during the TBLANK mode.
bits : 16 - 38 (23 bit)
access : read-write

OTPC_TIM2_RDENL_PROT : This bit has meaning only when the OTPC_TIM1_CC_T_25NS = 1, otherwise has no functionality. 0 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is one clock cycle. This is also applicable if OTPC_TIM1_CC_T_25NS = 0. 1 - The minimum number of clock cycles for which the signal read_enable of the OTP memory stays inactive is two clock cycles. The controller adds one extra wait state in the AHB access , if it is required, in order to achieves this constraint. This setting is applicable only if OTPC_TIM1_CC_T_25NS = 1.
bits : 23 - 46 (24 bit)
access : read-write

OTPC_PCTRL_WADDR : Defines the OTP position where will be programmed the 64-bits that are contained into the registers OTPC_PWORDx_REG. It points to a physical 72 bits OTP word.
bits : 0 - 12 (13 bit)
access : read-write

OTPC_PCTRL_PRETRY : It distinguishes the first attempt of a programming of an OTP position, from a retry of programming. 0 - A new value will be programmed in a blank OTP position. The hardware will try to write all the bits that are equal to '1'. 1 - The programming that is applied is not the first attempt, but is a request for reprogramming. Will be processed only the bits that were failed to be programmed during the previous attempt. The hardware knows the bits that were failed during the previous attempt. The registers OTPC_PWORDx_REG should contain the 64 bits of the value that should be programmed, independent of the value of the OTPC_PCTRL_PRETRY bit. Also, the OTPC_PCTRL_WADDR should contain always the required OTP address. A retry of a programming should be requested only if the previous action was the first attempt of programming or a retry of programming. Should not be requested a retry if the first attempt has not been performed.
bits : 14 - 28 (15 bit)
access : read-write

OTPC_PCTRL_PSTART : Write with '1' to trigger the programming of one OTP word, in the case where the MPROG mode is selected. The bit is cleared automatically. The 64-bits that will be programmed into the OTP memory are contained into the two registers OTPC_PWORDx_REG. This bit should be used when a new programming is initiated, but also when the programming must be retried. The OTPC_PCTRL_WADDR defines the OTP position where will be performed the programming.
bits : 15 - 30 (16 bit)
access : read-write

OTPC_STAT_PRDY : Indicates the state of a bit-programming process. 0 - The controller is busy. A bit-programming is in progress 1 - The logic which performs bit-programming is idle. When the controller is in MPROG mode, this bit should be used to monitor the progress of a programming request. During APROG mode, the value of this field it is normal to changing periodically.
bits : 0 - 0 (1 bit)
access : read-only

OTPC_STAT_PERR_UNC : Indicates that an uncorrectable error has been occurred during the word programming process. 0 - There is no uncorrectable error in the word-programming process. 1 - The process of word-programming failed due to an uncorrectable error. An uncorrectable error is considered when two or more of the bits in an OTP position cannot take the required values. This is a critical failure in the programming process, which means that the data cannot corrected by the single error correcting algorithm. When the controller is in MPROG mode, this bit should be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates if the programming was failed or ended successfully.
bits : 1 - 2 (2 bit)
access : read-only

OTPC_STAT_PERR_COR : Indicates that a correctable error has been occurred during the word programming process. 0 - There is no correctable error in the word-programming process. 1 - The process of word - programming reported a correctable error. The correctable error occurs when exactly one bit in an OTP position cannot take the required value. This is not a critical failure in the programming process. The data can still be retrieved correctly by the OTP memory, due to that the error correcting algorithm can repair the corrupted bit. When the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more words had a correctable error.
bits : 2 - 4 (3 bit)
access : read-only

OTPC_STAT_PZERO : Indicates that the programming sequence has been avoided during a programming request, due to that the word that should be programmed is equal to zero. 0 - At least one bit has been programmed into the OTP. 1 - The programming has not been performed. All the bits of the word that should be programmed are equal to zero. When the controller is in MPROG mode, this bit can be checked after the end of the programming process (OTPC_STAT_PRDY = 1). During APROG mode, the value of this field it is normal to changing periodically. After the end of the APROG mode (OTPC_STAT_ARDY = 1), this field indicates that one or more of words that have been processed are equal to zero.
bits : 3 - 6 (4 bit)
access : read-only

OTPC_STAT_TRDY : Indicates the state of a test mode. Should be used to monitor the progress of the TBLANK, TDEC and TWR modes. 0 - The controller is busy. One of the test modes is in progress. 1 - There is no active test mode.
bits : 4 - 8 (5 bit)
access : read-only

OTPC_STAT_TERROR : Indicates the result of a test sequence. Should be checked after the end of a TBLANK, TDEC and TWR mode (OTPC_STAT_TRDY = 1). 0 - The test sequence ends with no error. 1 - The test sequence has failed.
bits : 5 - 10 (6 bit)
access : read-only

OTPC_STAT_ARDY : Should be used to monitor the progress of the AREAD and APROG modes. 0 - One of the APROG or AREAD mode is selected. The controller is busy. 1 - The controller is not in an active AREAD or APROG mode.
bits : 6 - 12 (7 bit)
access : read-only

OTPC_STAT_RERROR : Indicates that during a normal reading (MREAD or AREAD) was reported a double error by the SECDED logic. That means that the data are corrupted. 0 - The read data are considered as correct. 1- The SECDED logic detects a double error. This bit can be cleared only with a write with '1'.
bits : 7 - 14 (8 bit)
access : read-write

OTPC_STAT_FWORDS : Indicates the number of words which contained in the fifo of the controller.
bits : 8 - 19 (12 bit)
access : read-only

OTPC_STAT_NWORDS : It contains the live value of the number of (32 bits) words that remain to be processed by the controller.
bits : 16 - 45 (30 bit)
access : read-only

OTPC_AHBADR : It is the AHB address used by the AHB master interface of the controller (the bits [31:2]). The bits [1:0] of the address are considered always as equal to zero.
bits : 2 - 33 (32 bit)
access : read-write