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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x104 byte (0x0)
mem_usage : registers
protection :

Registers

CRYPTO_CTRL_REG

CRYPTO_DEST_ADDR_REG

CRYPTO_KEYS_START

CRYPTO_STATUS_REG

CRYPTO_CLRIRQ_REG

CRYPTO_MREG0_REG

CRYPTO_MREG1_REG

CRYPTO_MREG2_REG

CRYPTO_MREG3_REG

CRYPTO_START_REG

CRYPTO_FETCH_ADDR_REG

CRYPTO_LEN_REG


CRYPTO_CTRL_REG

Crypto Control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_CTRL_REG CRYPTO_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_ALG CRYPTO_ALG_MD CRYPTO_OUT_MD CRYPTO_AES_KEY_SZ CRYPTO_ENCDEC CRYPTO_IRQ_EN CRYPTO_HASH_SEL CRYPTO_HASH_OUT_LEN CRYPTO_MORE_IN CRYPTO_AES_KEXP

CRYPTO_ALG : Algorithm selection. When CRYPTO_HASH_SEL = 0 the only available choice is the AES algorithm. 00 - AES 01 - Reserved 10 - Reserved 11 - Reserved When CRYPTO_HASH_SEL = 1, this field selects the desired hash algorithms, with the help of the CRYPTO_ALG_MD field. If CRYPTO_ALG_MD = 00 00 - MD5 01 - SHA-1 10 - SHA-256/224 11 - SHA-256 If CRYPTO_ALG_MD = 01 00 - SHA-384 01 - SHA-512 10 - SHA-512/224 11 - SHA-512/256
bits : 0 - 1 (2 bit)
access : read-write

CRYPTO_ALG_MD : It defines the mode of operation of the AES algorithm when the controller is configured for an encryption/decryption processing (CRYPTO_HASH_SEL = 0). 00 - ECB 01 - ECB 10 - CTR 11 - CBC When the controller is configured to applies a HASH function, this field selects the desired HASH algorithm with the help of the CRYPTO_ALG. 00 - HASH algorithms that are based on 32 bits operations 01 - HASH algorithms that are based on 64 bits operations 10 - Reserved 11 - Reserved See also the CRYPTO_ALG field.
bits : 2 - 5 (4 bit)
access : read-write

CRYPTO_OUT_MD : Output Mode. This field makes sense only when the AES algorithm is selected (CRYPTO_HASH_SEL =0) 0 - Write back to memory all the resulting data 1 - Write back to memory only the final block of the resulting data
bits : 4 - 8 (5 bit)
access : read-write

CRYPTO_AES_KEY_SZ : The size of AES Key 00 - 128 bits AES Key 01 - 192 bits AES Key 10 - 256 bits AES Key 11 - 256 bits AES Key
bits : 5 - 11 (7 bit)
access : read-write

CRYPTO_ENCDEC : Encryption/Decryption 0 - Decryption 1 - Encryption
bits : 7 - 14 (8 bit)
access : read-write

CRYPTO_IRQ_EN : Interrupt Request Enable 0 - The interrupt generation ability is disabled. 1 - The interrupt generation ability is enabled. Generates an interrupt request at the end of operation.
bits : 8 - 16 (9 bit)
access : read-write

CRYPTO_HASH_SEL : Selects the type of the algorithm 0 - The encryption algorithm (AES) 1 - A hash algorithm. The exact algorithm is defined by the fileds CRYPTO_ALG and CRYPTO_ALG_MD.
bits : 9 - 18 (10 bit)
access : read-write

CRYPTO_HASH_OUT_LEN : The number of bytes minus one of the hash result which will be saved at the memory by the DMA. In relation with the selected hash algorithm the accepted values are: MD5: 0..15 -> 1-16 bytes SHA-1: 0..19 -> 1-20 bytes SHA-256: 0..31 -> 1 - 32 bytes SHA-256/224: 0..27 -> 1- 28 bytes SHA-384: 0..47 -> 1 - 48 bytes SHA-512: 0..63 -> 1 - 64 bytes SHA-512/224: 0..27 -> 1- 28 bytes SHA-512/256: 0..31 -> 1 - 32 bytes
bits : 10 - 25 (16 bit)
access : read-write

CRYPTO_MORE_IN : 0 - Define that this is the last input block. When the current input is consumed by the crypto engine and the output data is written to the memory, the calculation ends (CRYPTO_INACTIVE goes to one). 1 - The current input data block is not the last. More input data will follow. When the current input is consumed, the engine stops and waits for more data (CRYPTO_WAIT_FOR_IN goes to one).
bits : 16 - 32 (17 bit)
access : read-write

CRYPTO_AES_KEXP : It forces (active high) the execution of the key expansion process with the starting of the AES encryption/decryption process. The bit will be cleared automatically by the hardware, after the completion of the AES key expansion process.
bits : 17 - 34 (18 bit)
access : read-write


CRYPTO_DEST_ADDR_REG

Crypto DMA destination memory
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_DEST_ADDR_REG CRYPTO_DEST_ADDR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_DEST_ADDR

CRYPTO_DEST_ADDR : Destination address at where the result of the processing is stored. The value of this register is updated as the calculation proceeds and the output data are written to the memory.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_KEYS_START

Crypto First position of the AES keys storage memory
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_KEYS_START CRYPTO_KEYS_START read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_KEY_X

CRYPTO_KEY_X : CRYPTO_KEY_(0-63) This is the AES keys storage memory. This memory is accessible via AHB slave interface, only when the CRYPTO is inactive (CRYPTO_INACTIVE = 1).
bits : 0 - 31 (32 bit)
access : write-only


CRYPTO_STATUS_REG

Crypto Status register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_STATUS_REG CRYPTO_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_INACTIVE CRYPTO_WAIT_FOR_IN CRYPTO_IRQ_ST

CRYPTO_INACTIVE : 0 - The CRYPTO is active. The processing is in progress. 1 - The CRYPTO is inactive. The processing has finished.
bits : 0 - 0 (1 bit)
access : read-only

CRYPTO_WAIT_FOR_IN : Indicates the situation where the engine waits for more input data. This is applicable when the CRYPTO_MORE_IN= 1, so the input data are fragmented in the memory. 0 - The crypto is not waiting for more input data. 1 - The crypto waits for more input data. The CRYPTO_INACTIVE flag remains to zero to indicate that the calculation is not finished. The supervisor of the CRYPTO must program to the CRYPTO_FETCH_ADDR and CRYPTO_LEN a new input data fragment. The calculation will be continued as soon as the CRYPTO_START register will be written with 1. This action will clear the CRYPTO_WAIT_FOR_IN flag.
bits : 1 - 2 (2 bit)
access : read-only

CRYPTO_IRQ_ST : The status of the interrupt request line of the CRYPTO block. 0 - There is no active interrupt request. 1 - An interrupt request is pending.
bits : 2 - 4 (3 bit)
access : read-only


CRYPTO_CLRIRQ_REG

Crypto Clear interrupt request
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_CLRIRQ_REG CRYPTO_CLRIRQ_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_CLRIRQ

CRYPTO_CLRIRQ : Write 1 to clear a pending interrupt request.
bits : 0 - 0 (1 bit)
access : write-only


CRYPTO_MREG0_REG

Crypto Mode depended register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_MREG0_REG CRYPTO_MREG0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_MREG0

CRYPTO_MREG0 : It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[31:0] CTR - CTRBLK[31:0]. It is the initial value of the 32 bits counter. At any other mode, the contents of this register has no meaning.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_MREG1_REG

Crypto Mode depended register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_MREG1_REG CRYPTO_MREG1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_MREG1

CRYPTO_MREG1 : It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[63:32] CTR - CTRBLK[63:32] At any other mode, the contents of this register has no meaning.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_MREG2_REG

Crypto Mode depended register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_MREG2_REG CRYPTO_MREG2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_MREG2

CRYPTO_MREG2 : It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[95:64] CTR - CTRBLK[95:64] At any other mode, the contents of this register has no meaning.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_MREG3_REG

Crypto Mode depended register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_MREG3_REG CRYPTO_MREG3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_MREG3

CRYPTO_MREG3 : It contains information that are depended by the mode of operation, when is used the AES algorithm: CBC - IV[127:96] CTR - CTRBLK[127:96] At any other mode, the contents of this register has no meaning.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_START_REG

Crypto Start calculation
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_START_REG CRYPTO_START_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_START

CRYPTO_START : Write 1 to initiate the processing of the input data. This register is auto-cleared.
bits : 0 - 0 (1 bit)
access : write-only


CRYPTO_FETCH_ADDR_REG

Crypto DMA fetch register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_FETCH_ADDR_REG CRYPTO_FETCH_ADDR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_FETCH_ADDR

CRYPTO_FETCH_ADDR : The memory address from where will be retrieved the data that will be processed. The value of this register is updated as the calculation proceeds and the output data are written to the memory.
bits : 0 - 31 (32 bit)
access : read-write


CRYPTO_LEN_REG

Crypto Length of the input block in bytes
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRYPTO_LEN_REG CRYPTO_LEN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRYPTO_LEN

CRYPTO_LEN : It contains the number of bytes of input data. If this number is not a multiple of a block size, the data is automatically extended with zeros. The value of this register is updated as the calculation proceeds and the output data are written to the memory.
bits : 0 - 23 (24 bit)
access : read-write



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