CTRL_REG

PRI1_REG

PRI2_REG

PRI3_REG

PRI4_REG

PRI5_REG

PRI6_REG

PRI7_REG

STAT_REG

PRI8_REG

PRI9_REG

PRI10_REG

PRI11_REG

PRI12_REG

PRI13_REG

PRI14_REG

PRI15_REG

STAT2_REG

INT_MASK_REG

INT_STAT_REG

BLE_PTI_REG

FTDF_PTI_REG

PRGING_ARBITER : If set to 1 then the current transaction (Tx or Rx) will complete normally and after that no further decision will be taken by the arbiter. Will be set to 1 automatically by the HW as soon as a write operation will be detected to the COEX_PRIx_REG registers. As soon as the update on the priorities will be completed, the SW should clear this bit. The SW can set or clear this bit. Note: Depending on the relationship between the PCLK and COEX_CLK periods a write operation to this bitfield may be effective in more than one PCLK clock cycles.
bits : 0 - 0 (1 bit)
access : read-write

DECISION_SW_ALL : Refer to COEX_INT_STAT_REG[ IRQ_DECISION_SW ] bitfield description.
bits : 1 - 2 (2 bit)
access : read-write

TXRX_MON_FTDF_ALL : It controls the behavior of the Monitoring bitfields COEX_INT_STAT_REG[ *TXRX_MON* ] If 0 then update the Monitoring bitfields with FTDF Rx/Tx that has been masked. If 1 then update for every FTDF Rx/Tx, either masked or not.
bits : 2 - 4 (3 bit)
access : read-write

TXRX_MON_BLE_ALL : It controls the behavior of the Monitoring bitfields COEX_INT_STAT_REG[ *TXRX_MON* ] If 0 then update the Monitoring bitfields with BLE Rx/Tx that has been masked. If 1 then update for every BLE Rx/Tx, either masked or not.
bits : 3 - 6 (4 bit)
access : read-write

SMART_ACT_IMPL : Controls the behavior of the SMART_ACT (and SMART_PRI as a consequence). If SMART_ACT_IMPL= 0 then if any BLE or FTDF MAC request is active then SMART_ACT will be asserted. SMART_ACT will actually be the logical OR of ble_active and ftdf_active internal signals. SMART_ACT will be asserted regardless the decision of the Arbiter to allow or disallow the access to the on-chip radio from the active MAC(s). if SMART_ACT_IMPL= 1 then if the Arbiter's decision is to allow EXTernal MAC, then keep SMART_ACT to 0 , otherwise follow the implementation of SMART_ACT_IMPL= 0 .
bits : 4 - 8 (5 bit)
access : read-write

SEL_COEX_DIAG : The COEX block can provide internal diagnostic signals by overwriting the BLE diagnostic bus, which is forwarded to GPIO multiplexing. There is no need to program the BLE registers, but only this field and the GPIO PID fields. 0: No COEX diagnostics, only BLE. 1: BLE_DIAG[4:3]=decision[1:0] BLE_DIAG[5]=closing. 2: BLE_DIAG[4:3]=decision[1:0] BLE_DIAG[5]=closing BLE_DIAG[6]=OR( ftdf/ble2coex_tx/rx_en ) 3: BLE_DIAG[2]=closing OR radio_busy BLE_DIAG[6:3]=decision_ptr[3:0] BLE_DIAG[7]=0.
bits : 5 - 11 (7 bit)
access : read-write

SEL_FTDF_CCA : If set to 1 and the COEX decision is different than FTDF , then the CCA_STAT signal going to FTDF (generated from the radio) will be forced to 1 otherwise the FTDF.CCA_STAT will be driven with the signal generated from the radio. Recommended value for SEL_FTDF_CCA is 1 .
bits : 7 - 14 (8 bit)
access : read-write

SEL_FTDF_PTI : It controls the source of the FTDF PTI value that the COEX Arbiter will use. If 0 then use the COEX_FTDF_PTI_REG. If 1 then use the PTI value provided by the FTDF core.
bits : 8 - 16 (9 bit)
access : read-write

SEL_BLE_PTI : It controls the source of the BLE PTI value that the COEX Arbiter will use. If 0 then use the COEX_BLE_PTI_REG. If 1 then use the PTI value provided by the BLE core.
bits : 9 - 18 (10 bit)
access : read-write

SEL_BLE_WLAN_TX_RX : If set to 1 then the COEX block will drive the WLAN_TX and WLAN_RX inputs of the BLE core. Otherwise both BLE inputs will be forced to 0 .
bits : 10 - 20 (11 bit)
access : read-write

SEL_BLE_RADIO_BUSY : Select the logic driving the BLE core input ble.radio_busy : 0: (decision==BLE) AND rfcu.radio_busy. 1: Hold to 0 . 2: (decision==FTDF) OR (decision==EXT) OR rfcu.radio_busy. 3: (decision==FTDF) OR (decision==EXT). Selection 0 is the default, while selection 2 is the recommended value if the BLE SW supports it.
bits : 11 - 23 (13 bit)
access : read-write

IGNORE_EXT : If set to 1 then all EXT requests are ignored by masking the internal ext_act signal ( ext_act is the logical OR of ext_act0 and ext_act1 ). Refer also to IGNORE_EXT_STAT.
bits : 13 - 26 (14 bit)
access : read-write

IGNORE_FTDF : If set to 1 then all FTDF requests are ignored by masking the internal ftdf_active signal. Refer also to IGNORE_FTDF_STAT.
bits : 14 - 28 (15 bit)
access : read-write

IGNORE_BLE : If set to 1 then all BLE requests are ignored by masking the internal ble_active signal. Refer also to IGNORE_BLE_STAT.
bits : 15 - 30 (16 bit)
access : read-write

COEX_PRI_PTI : The priority level specified by the name of this register will be applied to the packets coming from the MAC specified by the COEX_PRI_MAC bitfield and characterized with the PTI value specified by the COEX_PRI_PTI bitfield. The effective PTI value of the packets coming from BLE and FTDF is controlled by the register bitfields SEL_BLE_PTI and SEL_FTDF_PTI, while for the External MAC (EXT) the PTI is considered always as 0 .
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Specifies the MAC that has been assigned with the specific priority level. The MAC encoding follows the COEX_DECISION bitfield encoding.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_DECISION_PTR : Provides the number x of the COEX_PRIx_REG that win the last arbitration cycle. If 0 then it is a null pointer, pointing to no COEX_PRIx_REG.
bits : 0 - 3 (4 bit)
access : read-only

COEX_DECISION : Decision values: 0: Decision is NONE. 1: Decision is BLE. 2: Decision is FTDF. 3: Decision is EXT. Note: If 0 (i.e. decision is NONE) then no MAC will have access to the on-chip radio. As a consequence, the SMART_PRI signal will stay low, since no on-chip (SMART) MAC will have priority. Note: While in programming mode, the COEX_PRIx_REGs are considered as invalid, which means that no new decision can be taken. Note: The decision NONE will be held as long as there is no *_active internal signal from BLE, FTDF or EXT. Also, if in programming state and the last transaction has been finished, then the decision will be held also to NONE.
bits : 5 - 11 (7 bit)
access : read-only

COEX_CLOSING : Provides the value of the CLOSING substate.
bits : 7 - 14 (8 bit)
access : read-only

SMART_ACT : Current state of the pin.
bits : 8 - 16 (9 bit)
access : read-only

SMART_PRI : Current state of the pin.
bits : 9 - 18 (10 bit)
access : read-only

EXT_ACT0 : Current state of the pin.
bits : 10 - 20 (11 bit)
access : read-only

EXT_ACT1 : Current state of the pin.
bits : 11 - 22 (12 bit)
access : read-only

COEX_RADIO_BUSY : Current state of RADIO_BUSY signal generated from RFCU, which is the logical OR among all Radio DCFs. Note that the arbiter will process this value with one COEX clock cycle delay.
bits : 12 - 24 (13 bit)
access : read-only

IGNORE_EXT_STAT : If set to 1 then all EXT requests are ignored by masking immediately the request signal from the external MAC. In more detail, the internal signal ext_active is the logical AND of this bitfield and the ext_act .
bits : 13 - 26 (14 bit)
access : read-only

IGNORE_FTDF_STAT : This signal is constantly 1 on BLE-only chips. If set to 1 then all FTDF requests are ignored by masking immediately the request signal from the FTDF. In more detail, the internal signal ftdf_active is the logical AND of this bitfield and the ftdf.phy_en .
bits : 14 - 28 (15 bit)
access : read-only

IGNORE_BLE_STAT : This signal is constantly 1 on FTDF-only chips. If set to 1 then all BLE requests are ignored by masking immediately the request signal from the BLE. In more detail, the internal signal ble_active is the logical AND of this bitfield and the ble.event_in_process .
bits : 15 - 30 (16 bit)
access : read-only

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_PRI_PTI : Refer to COEX_PRI1_REG.
bits : 0 - 2 (3 bit)
access : read-write

COEX_PRI_MAC : Refer to COEX_PRI1_REG.
bits : 3 - 7 (5 bit)
access : read-write

COEX_DECISION_WITH_CLOSING : DECISION (bits [1:0]) appended the CLOSING (bit [2]) state.
bits : 0 - 2 (3 bit)
access : read-only

COEX_FTDF_ACTIVE : The internal FTDF_ACTIVE signal used for the decision taking.
bits : 3 - 6 (4 bit)
access : read-only

COEX_FTDF_RX_EN : The current value of FTDF RX_EN.
bits : 4 - 8 (5 bit)
access : read-only

COEX_FTDF_TX_EN : The current value of FTDF TX_EN.
bits : 5 - 10 (6 bit)
access : read-only

COEX_FTDF_PTI_INT : The FTDF PTI value that is used for decision taking. Value depends on COEX_CTRL_REG.SEL_FTDF_PTI.
bits : 6 - 14 (9 bit)
access : read-only

COEX_BLE_ACTIVE : The internal BLE_ACTIVE signal used for decision taking.
bits : 9 - 18 (10 bit)
access : read-only

COEX_BLE_RX_EN : The current value of BLE RX_EN.
bits : 10 - 20 (11 bit)
access : read-only

COEX_BLE_TX_EN : The current value of BLE TX_EN.
bits : 11 - 22 (12 bit)
access : read-only

COEX_BLE_PTI_INT : The BLE PTI value that is used for decision taking.
bits : 12 - 26 (15 bit)
access : read-only

COEX_EXT_ACT : The internal EXT_ACT used for the decision taking.
bits : 15 - 30 (16 bit)
access : read-only

IRQ_TXRX_MON : If 1 then a 1 on COEX_INT_STAT_REG[IRQ_TXRX_MON] will generate an IRQ to CPU.
bits : 8 - 16 (9 bit)
access : read-write

IRQ_DECISION_SW : If 1 then a 1 on COEX_INT_STAT_REG[IRQ_DECISION_SW] will generate an IRQ to CPU.
bits : 9 - 18 (10 bit)
access : read-write

TXRX_MON_PTR : Tx/Rx Monitor Pointer. If not zero then it provides a pointer to the Priority registers indicating the completion of an Tx or Rx (deassertion of TX_EN or RX_EN) that corresponds to this Priority register. Refer also to the COEX_CTRL_REG[ TXRX_MON_ALL ] control bit. If the PTI that corresponds to the deasserted TX_EN/RX_EN is not in the Priority Register list, then this event will be ignored and will not be reported by the TXRX Monitoring bitfields. Reading the register will clear the bitfield.
bits : 0 - 3 (4 bit)
access : read-only

TXRX_MON_TX : If 0 then the corresponding TXRX_MON_PTR corresponds to an Rx. If 1 then the corresponding TXRX_MON_PTR corresponds to an Tx. The bitfield is valid only when TXRX_MON_PTR is not zero.
bits : 5 - 10 (6 bit)
access : read-only

TXRX_MON_PASSED : This bit indicates if the corresponding TXRX_MON_PTR pointer indicates a Tx/Rx that has been masked or not by the COEX block. If 0 then the Tx/Rx has been masked. If 1 then the Tx/Rx has not been masked. The bitfield is valid only when TXRX_MON_PTR is not zero.
bits : 6 - 12 (7 bit)
access : read-only

TXRX_MON_OVWR : Tx/Rx Monitor entry Overwritten. if 1 then TXRX_MON_PTR loaded a new value without being cleared first by the software. Provides an indication that the software does not fetch the TXRX_MON_PTR fast enough.
bits : 7 - 14 (8 bit)
access : read-only

IRQ_TXRX_MON : Tx/Rx Monitor event pending. When this bitfield is set, then there is a valid entry at the bitfields TXRX_MON_PTR, TXRX_MON_TX, TXRX_MON_PASSED and TXRX_MON_OVWR.
bits : 8 - 16 (9 bit)
access : read-only

IRQ_DECISION_SW : IRQ event when the DECISION switches to another value. If DECISION_SW_ALL=1, then it reports any change of DECISION value. If DECISION_SW_ALL=0, then it reports only the switches to another MAC, ignoring also the intermediate transitions to DECISION==NONE. For example the sequence FTDF-NONE-FTDF-NONE-BLE-NONE-BLE will report only the first switch from NONE to BLE. Note that after a Radio Power domain reset, the first transition of the DECISION to any non-NONE value will also trigger this event.
bits : 9 - 18 (10 bit)
access : read-only

COEX_BLE_PTI : This value specifies the PTI value that characterizes the next BLE transaction that will be initiated on the following ble_active positive edge. The value should remain constant during the high period of the ble_active signal.
bits : 0 - 2 (3 bit)
access : read-write

COEX_FTDF_PTI : This value specifies the PTI value that characterizes the next FTDF transaction that will be initiated on the following ftdf_active positive edge. The value should remain constant during the high period of the ftdf_active signal. Refer also to bitfield COEX_CTRL_REG.SEL_FTDF_PTI.
bits : 0 - 2 (3 bit)
access : read-write