CLK_AMBA_REG

PMU_CTRL_REG

TRIM_CTRL_REG

CLK_FREQ_TRIM_REG

CLK_RCX20K_REG

BANDGAP_REG

ANA_STATUS_REG

VBUS_IRQ_MASK_REG

VBUS_IRQ_CLEAR_REG

BOD_CTRL2_REG

BOD_STATUS_REG

LDO_CTRL1_REG

LDO_CTRL2_REG

SLEEP_TIMER_REG

POR_VBAT_CTRL_REG

XTALRDY_CTRL_REG

LDO_CTRL3_REG

RESET_STAT_REG

SECURE_BOOT_REG

PMU_RESET_RAIL_REG

DISCHARGE_RAIL_REG

CLK_RADIO_REG

CLK_TMR_REG

HCLK_DIV : AHB interface and microprocessor clock. Source clock divided by: 000 = divide hclk by 1 001 = divide hclk by 2 010 = divide hclk by 4 011 = divide hclk by 8 1xx = divide hclk by 16
bits : 0 - 2 (3 bit)
access : read-write

PCLK_DIV : APB interface clock, Cascaded with HCLK: 00 = divide hclk by 1 01 = divide hclk by 2 10 = divide hclk by 4 11 = divide hclk by 8
bits : 4 - 9 (6 bit)
access : read-write

AES_CLK_ENABLE : Clock enable for AES crypto block
bits : 6 - 12 (7 bit)
access : read-write

ECC_CLK_ENABLE : Clock enable for ECC block
bits : 7 - 14 (8 bit)
access : read-write

TRNG_CLK_ENABLE : Clock enable for TRNG block
bits : 8 - 16 (9 bit)
access : read-write

OTP_ENABLE : Clock enable for OTP controller
bits : 9 - 18 (10 bit)
access : read-write

QSPI_DIV : QSPI divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8
bits : 10 - 21 (12 bit)
access : read-write

QSPI_ENABLE : Clock enable for QSPI controller
bits : 12 - 24 (13 bit)
access : read-write

PERIPH_SLEEP : Put all peripherals (I2C, UART, SPI, ADC) in powerdown
bits : 0 - 0 (1 bit)
access : read-write

RADIO_SLEEP : Put the digital part of the radio in powerdown
bits : 1 - 2 (2 bit)
access : read-write

BLE_SLEEP : Put the BLE in powerdown. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU.
bits : 2 - 4 (3 bit)
access : read-write

FTDF_SLEEP : Put the FTDF in powerdown
bits : 3 - 6 (4 bit)
access : read-write

MAP_BANDGAP_EN : Maps the bandgap_enable to P06
bits : 4 - 8 (5 bit)
access : read-write

RESET_ON_WAKEUP : Perform a Hardware Reset after waking up. Booter will be started.
bits : 5 - 10 (6 bit)
access : read-write

OTP_COPY_DIV : Sets the HCLK division during OTP mirroring
bits : 6 - 13 (8 bit)
access : read-write

RETAIN_RAM : Select the retainability of the 5 system memory RAM macros during deep sleep. '1' is retainable, '0' is power gated (4) is SYSRAM5 (3) is SYSRAM4 (2) is SYSRAM3 (1) is SYSRAM2 (0) is SYSRAM1
bits : 8 - 20 (13 bit)
access : read-write

ENABLE_CLKLESS : Selects the clockless sleep mode. Wakeup is done asynchronously. When set to '1', the lp_clk is stopped during deep sleep, until a wakeup event (not debounced) is detected by the WAKUPCT block. When set to '0', the lp_clk continues running, so the MAC counters keep on running. This mode cannot be combined with regulated sleep, so keep SLEEP_TIMER=0 when using ENABLE_CLKLESS.
bits : 13 - 26 (14 bit)
access : read-write

RETAIN_CACHE : Selects the retainability of the cache block during deep sleep. '1' is retainable, '0' is power gated
bits : 14 - 28 (15 bit)
access : read-write

RETAIN_ECCRAM : Selects the retainability of the ECC u-Code RAM during deep sleep. '1' is retainable, '0' is power gated
bits : 15 - 30 (16 bit)
access : read-write

XTAL_COUNT_N : Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 32. 0x01: 32 0x02: 64 0x3f:2016
bits : 0 - 5 (6 bit)
access : read-write

XTAL_TRIM_SELECT : Select which source controls the XTAL trimming 0b00: xtal counter. Starts XTAL16M_START_REG, after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG. 0b01: xtal OK filter. Starts with XTAL16M_START_REG, when xtal is ramping is changed to CLK_FREQ_TRIM_REG 0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG. 0b11: xtal OK filter, 2 stage. Starts with XTAL16M_START_REG switches to XTAL16M_RAMP_REG when sw1='1', and switches to CLK_FREQ_TRIM_REG when sw2='1'.
bits : 6 - 13 (8 bit)
access : read-write

XTAL_SETTLE_N : Designates that the XTAL16 can be safely used as the CPU clock. When XTAL16_CLK_CNT reases this value, the signal XTAL_SETTLE_READY will be set
bits : 8 - 21 (14 bit)
access : read-write

FINE_ADJ : Xtal frequency fine trimming register.0x00 = lowest frequency 0xFF = highest frequency
bits : 0 - 7 (8 bit)
access : read-write

COARSE_ADJ : Xtal frequency course trimming register. 0x0 = lowest frequency 0x7 = highest frequencyIncrement or decrement the binary value with 1. Wait approximately 200usec to allow the adjustment to settle.
bits : 8 - 18 (11 bit)
access : read-write

RCX20K_TRIM : 0000 = lowest frequency 0111 = default 1111 = highest frequency
bits : 0 - 3 (4 bit)
access : read-write

RCX20K_NTC : Temperature control
bits : 4 - 11 (8 bit)
access : read-write

RCX20K_BIAS : Bias control
bits : 8 - 17 (10 bit)
access : read-write

RCX20K_LOWF : Extra low frequency
bits : 10 - 20 (11 bit)
access : read-write

RCX20K_ENABLE : Enable the RCX oscillator
bits : 11 - 22 (12 bit)
access : read-write

BGR_TRIM : Trim register for bandgap
bits : 0 - 4 (5 bit)
access : read-write

BGR_ITRIM : Current trimming for bias
bits : 5 - 14 (10 bit)
access : read-write

LDO_SLEEP_TRIM : 0x4 --> 1120 mV 0x5 --> 1089 mV 0x6 --> 1058 mV 0x7 --> 1030 mV 0x0 --> 1037 mV 0x1 --> 1005 mV 0x2 --> 978 mV 0x3 --> 946 mV 0x8 --> 952 mV 0x9 --> 918 mV 0xA --> 889 mV 0xB --> 861 mV 0xC --> 862 mV 0xD --> 828 mV 0xE --> 798 mV 0xF --> 770 mV These values are from simulation and vary over corners
bits : 10 - 23 (14 bit)
access : read-write

LDO_SUPPLY_USE_BGREF : 0x0 -> LDO_SUPPLY_(VBAT/USB) uses V12 voltage/(V12/2Mohm) current as reference 0x1 -> LDO_SUPPLY_(VBAT/USB) uses bandgap voltage/bandgap current (1uA) as reference -> set 0x1 in (booter-)software Switch to 0x1 at start of user application when maximum BOD functionality is switched on.
bits : 14 - 28 (15 bit)
access : read-write

LDO_RADIO_OK : ldo_radio = ok
bits : 0 - 0 (1 bit)
access : read-only

COMP_VBAT_OK : vbat > 1.7V
bits : 1 - 2 (2 bit)
access : read-only

VBUS_AVAILABLE : vbus is available (vbus > vbat)
bits : 2 - 4 (3 bit)
access : read-only

NEWBAT : new battery has been detected
bits : 3 - 6 (4 bit)
access : read-only

LDO_SUPPLY_VBAT_OK : ldo_supply_vbat =ok
bits : 4 - 8 (5 bit)
access : read-only

LDO_SUPPLY_USB_OK : ldo_supply_usb = ok
bits : 5 - 10 (6 bit)
access : read-only

BANDGAP_OK : bandgap = ok
bits : 6 - 12 (7 bit)
access : read-only

COMP_VDD_HIGH : VDD > 1.13V
bits : 7 - 14 (8 bit)
access : read-only

LDO_CORE_OK : ldo_core = ok
bits : 8 - 16 (9 bit)
access : read-only

LDO_1V8_PA_OK : ldo_vdd1v8P = ok
bits : 9 - 18 (10 bit)
access : read-only

LDO_1V8_FLASH_OK : ldo_vdd1v8 = ok
bits : 10 - 20 (11 bit)
access : read-only

COMP_VBUS_HIGH : VBUS > 4V
bits : 11 - 22 (12 bit)
access : read-only

COMP_VBUS_LOW : VBUS > 3.4V
bits : 12 - 24 (13 bit)
access : read-only

COMP_V33_HIGH : V33 > 1.7V
bits : 13 - 26 (14 bit)
access : read-only

COMP_1V8_FLASH_HIGH : VDD1V8 > 1.7V
bits : 14 - 28 (15 bit)
access : read-only

COMP_1V8_PA_HIGH : VDD1V8P > 1.7V
bits : 15 - 30 (16 bit)
access : read-only

VBUS_IRQ_EN_FALL : Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to fall below threshold
bits : 0 - 0 (1 bit)
access : read-write

VBUS_IRQ_EN_RISE : Setting this bit to '1' enables VBUS_IRQ generation when the VBUS starts to ramp above threshold
bits : 1 - 2 (2 bit)
access : read-write

VBUS_IRQ_CLEAR : Writing any value to this register will reset the VBUS_IRQ line
bits : 0 - 15 (16 bit)
access : write-only

BOD_RESET_EN : Generate a chip reset on BOD event
bits : 0 - 0 (1 bit)
access : read-write

BOD_VDD_EN : VDD BOD Enable
bits : 1 - 2 (2 bit)
access : read-write

BOD_V33_EN : V33 BOD Enable
bits : 2 - 4 (3 bit)
access : read-write

BOD_1V8_PA_EN : 1V8 PA BOD Enable
bits : 3 - 6 (4 bit)
access : read-write

BOD_1V8_FLASH_EN : 1V8 Flash BOD Enable
bits : 4 - 8 (5 bit)
access : read-write

BOD_VBAT_EN : VBAT BOD Enable
bits : 5 - 10 (6 bit)
access : read-write

BOD_V14_EN : V14 BOD Enable
bits : 6 - 12 (7 bit)
access : read-write

BOD_VDD_LOW : Indicates VDD > VDD_Trigger
bits : 0 - 0 (1 bit)
access : read-only

BOD_1V8_PA_LOW : Indicates V18_PA > V18_PA_Trigger
bits : 1 - 2 (2 bit)
access : read-only

BOD_1V8_FLASH_LOW : Indicates V18_Flash > V18_Flash_Trigger
bits : 2 - 4 (3 bit)
access : read-only

BOD_V33_LOW : Indicates V33 > V33_Trigger
bits : 3 - 6 (4 bit)
access : read-only

BOD_VBAT_LOW : Indicates VBAT > VBAT_Trigger
bits : 4 - 8 (5 bit)
access : read-only

BOD_V14_LOW : Indicates V14 > V14_Trigger
bits : 5 - 10 (6 bit)
access : read-only

LDO_CORE_CURLIM : Sets the current limit of LDO_CORE 00 = Current limiter disabled 01 = 8 mA 10 = 60 mA 11 = 80 mA
bits : 0 - 1 (2 bit)
access : read-write

LDO_VBAT_RET_LEVEL : Sets the output voltage of LDO_VBAT_RET 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.00 V
bits : 2 - 5 (4 bit)
access : read-write

LDO_SUPPLY_VBAT_LEVEL : Sets the output voltage of LDO_SUPPLY_VBAT 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.00 V
bits : 4 - 9 (6 bit)
access : read-write

LDO_SUPPLY_USB_LEVEL : Sets the output voltage of LDO_SUPPLY_USB 00 = 2.40 V 01 = 3.30 V 10 = 3.45 V 11 = 3.00 V
bits : 6 - 13 (8 bit)
access : read-write

LDO_CORE_SETVDD : Sets the output voltage of LDO_CORE 000 = 1.20 V 001 = 1.15 V 010 = 1.10 V 011 = 1.05 V 1XX = 1.32 V
bits : 8 - 18 (11 bit)
access : read-write

LDO_RADIO_SETVDD : Sets the output voltage of LDO_RADIO 000 = 1.30 V 001 = 1.35 V 010 = 1.40 V 011 = 1.45 V 1XX = 1.50 V
bits : 11 - 24 (14 bit)
access : read-write

LDO_RADIO_ENABLE : Enables (1) or disables (0) LDO_RADIO For fast XTAL startup, this bit may be kept to '1' during deep sleep. The LDO is switched off automatically when in deep sleep, and enabled when waking up.
bits : 14 - 28 (15 bit)
access : read-write

LDO_1V2_ON : Enables (1) or disables (0) LDO_CORE
bits : 0 - 0 (1 bit)
access : read-write

LDO_3V3_ON : Enables (1) or disables (0) LDO_SUPPLY_VBAT and LDO_SUPPLY_USB
bits : 1 - 2 (2 bit)
access : read-write

LDO_1V8_FLASH_ON : Enables (1) or disables (0) LDO_1V8_FLASH
bits : 2 - 4 (3 bit)
access : read-write

LDO_1V8_PA_ON : Enables (1) or disables (0) LDO_1V8_PA
bits : 3 - 6 (4 bit)
access : read-write

LDO_VBAT_RET_DISABLE : Disables (1) or enables (0) LDO_VBAT_RET
bits : 4 - 8 (5 bit)
access : read-write

LDO_1V8_FLASH_RET_DISABLE : Disables (1) or enables (0) LDO_1V8_FLASH_RET
bits : 5 - 10 (6 bit)
access : read-write

LDO_1V8_PA_RET_DISABLE : Disables (1) or enables (0) LDO_1V8_PA_RET
bits : 6 - 12 (7 bit)
access : read-write

SLEEP_TIMER : Defines the amount of ticks of the sleep clock between enabling the bandgap for re-charging the retention LDOs. This value depends on the load and should be calibrated on a per application basis.If set to 0, no recharging cycle will happen at all. Keep this value to 0 (no recharging) when using the clockless sleep.
bits : 0 - 15 (16 bit)
access : read-write

POR_VBAT_THRES_LOW : Low-side (CTAT) threshold contribution - Align setting with POR_VBAT_THRES_HIGH. Set POR_VBAT_HYST_LOW to 0x0, when non-reset settings are used. Threshold --> Setting 1.25V --> 0xC 1.27V --> 0xC 1.29V --> 0xC 1.31V --> 0xC 1.44V --> 0x0 1.49V --> 0x1 1.53V --> 0x2 1.58V --> 0x3 1.63V --> 0x4 1.68V --> 0x5 1.73V --> 0x6 1.78V --> 0x7 1.83V --> 0x8 1.87V --> 0x9 1.92V --> 0xA 1.97V --> 0xB 1.63V -- > 0xF Reset mode - use only with POR_VBAT_THRES_HIGH=0x6 and POR_VBAT_THRES_HYST=0x2
bits : 0 - 3 (4 bit)
access : read-write

POR_VBAT_THRES_HIGH : High-side (PTAT) threshold contribution - Align setting with POR_VBAT_THRES_LOW. Set POR_VBAT_HYST_LOW to 0x0, when non-reset settings are used. Threshold --> Setting 1.25V --> 0x0 1.27V --> 0x1 1.29V --> 0x2 1.31V --> 0x3 1.44V --> 0x4 1.49V --> 0x5 1.53V --> 0x6 --> RESET 1.58V --> 0x7 1.63V --> 0x8 1.68V --> 0x9 1.73V --> 0xA 1.78V --> 0xB 1.83V --> 0xC 1.87V --> 0xD 1.92V --> 0xE 1.97V --> 0xF
bits : 4 - 11 (8 bit)
access : read-write

POR_VBAT_HYST_LOW : Controls hysteresis of POR (20mV/LSB) - Set to 0x0 when non-reset settings are used for POR_VBAT_THRES_LOW and POR_VBAT_THRES_HIGH.
bits : 8 - 19 (12 bit)
access : read-write

POR_VBAT_ENABLE : Enables generation of the POR
bits : 12 - 24 (13 bit)
access : read-write

POR_VBAT_MASK_N : Enables propagation of the generated POR
bits : 13 - 26 (14 bit)
access : read-write

XTALRDY_CNT : Number of LP cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. 0x00: no interrupt
bits : 0 - 7 (8 bit)
access : read-write

LDO_VBAT_RET_ENABLE : Setting of this register is ORed with the ldo_enable control from the CRG StateMachine. 0 = CRG controls the enable of the LDO. 1 = LDO is always enabled To activate a retention LDO in active-mode , this bit must be 1 and the VREF_HOLD bit must be 0 .
bits : 0 - 0 (1 bit)
access : read-write

LDO_VBAT_RET_VREF_HOLD : Setting of this register is ORed with the vref_hold control from the CRG StateMachine. 0 = CRG controls the T and H of Vref. 1 = T and H is always in Hold
bits : 1 - 2 (2 bit)
access : read-write

LDO_1V8_FLASH_RET_ENABLE : Setting of this register is ORed with the ldo_enable control from the CRG StateMachine. 0 = CRG controls the enable of the LDO. 1 = LDO is always enabled To activate a retention LDO in active-mode , this bit must be 1 and the VREF_HOLD bit must be 0 .
bits : 2 - 4 (3 bit)
access : read-write

LDO_1V8_FLASH_RET_VREF_HOLD : Setting of this register is ORed with the vref_hold control from the CRG StateMachine. 0 = CRG controls the T and H of Vref. 1 = T and H is always in Hold
bits : 3 - 6 (4 bit)
access : read-write

LDO_1V8_PA_RET_ENABLE : Setting of this register is ORed with the ldo_enable control from the CRG StateMachine. 0 = CRG controls the enable of the LDO. 1 = LDO is always enabled To activate a retention LDO in active-mode , this bit must be 1 and the VREF_HOLD bit must be 0 .
bits : 4 - 8 (5 bit)
access : read-write

LDO_1V8_PA_RET_VREF_HOLD : Setting of this register is ORed with the vref_hold control from the CRG StateMachine. 0 = CRG controls the T and H of Vref. 1 = T and H is always in Hold
bits : 5 - 10 (6 bit)
access : read-write

PORESET_STAT : Indicates that a PowerOn Reset has happened
bits : 0 - 0 (1 bit)
access : read-write

HWRESET_STAT : Indicates that a HW Reset has happened
bits : 1 - 2 (2 bit)
access : read-write

SWRESET_STAT : Indicates that a SW Reset has happened
bits : 2 - 4 (3 bit)
access : read-write

WDOGRESET_STAT : Indicates that a Watchdog has happened. Note that it is also set when a POReset has happened.
bits : 3 - 6 (4 bit)
access : read-write

SWD_HWRESET_STAT : Indicates that a write to SWD_RESET_REG has happened. Note thatit is also set when a POReset has happened.
bits : 4 - 8 (5 bit)
access : read-write

SECURE_BOOT : Follows the respective OTP flag value. Is write-one-only and will be reset by POR only! Its value is updated by the BootROM code. 1: system is a secure system supporting secure boot 0: system is not supporting secure boot
bits : 0 - 0 (1 bit)
access : read-write

FORCE_DEBUGGER_OFF : Follows the respective OTP flag value. Is write-one-only and will be reset by POR only! Its value is updated by the BootROM code. 1: The system debugger SWD is totally disabled. 0: The system debugger is enabled with DEBUGGER_ENABLE
bits : 1 - 2 (2 bit)
access : read-write

RESET_V14 : 1: Enables discharging of the V14 rail when HW reset is pressed 0: this rail will not be discharged when HW reset is pressed
bits : 0 - 0 (1 bit)
access : read-write

RESET_V18 : 1: Enables discharging of the V18 rail when HW reset is pressed 0: this rail will not be discharged when HW reset is pressed
bits : 1 - 2 (2 bit)
access : read-write

RESET_V18P : 1: Enables discharging of the V18P rail when HW reset is pressed 0: this rail will not be discharged when HW reset is pressed
bits : 2 - 4 (3 bit)
access : read-write

RESET_V14 : 1: Enables immediate discharging of the V14 rail. Note that the source is not disabled. 0: disable immediate discharging of the V14 rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V14
bits : 0 - 0 (1 bit)
access : read-write

RESET_V18 : 1: Enables immediate discharging of the V18 rail. Note that the source is not disabled. 0: disable immediate discharging of the V18 rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18
bits : 1 - 2 (2 bit)
access : read-write

RESET_V18P : 1: Enables immediate discharging of the V18P rail. Note that the source is not disabled. 0: disable immediate discharging of the V18P rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18P
bits : 2 - 4 (3 bit)
access : read-write

RFCU_DIV : Division factor for RF Control Unit 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8 The programmed frequency must be exactly 8MHz.
bits : 0 - 1 (2 bit)
access : read-write

RFCU_ENABLE : Enable the RF control Unit clock
bits : 3 - 6 (4 bit)
access : read-write

BLE_DIV : Division factor for BLE core blocks, having as reference the DIVN clock: 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 The programmed frequency should not be lower than 8MHz, not faster than 16MHz and not faster than the programmed CPU clock frequency. Refer also to BLE_CNTL2_REG[BLE_CLK_SEL].
bits : 4 - 9 (6 bit)
access : read-write

BLE_LP_RESET : Reset for the BLE LP timer
bits : 6 - 12 (7 bit)
access : read-write

BLE_ENABLE : Enable the BLE core clocks. When the BLE system clock is disabled, either due to the CLK_RADIO_REG[BLE_ENABLE] or due to the PMU_CTRL_REG[BLE_SLEEP], then any access to the BLE Register file will issue a hard fault to the CPU.
bits : 7 - 14 (8 bit)
access : read-write

FTDF_MAC_DIV : Division factor for FTCF MAC clock, relative to the DIVN clock 00 = Divide by 1 01 = Divide by 2 10 = Divide by 4 11 = Divide by 8 It should always be set to 00.
bits : 8 - 17 (10 bit)
access : read-write

FTDF_MAC_ENABLE : Enable the FTDF MAC core clocks
bits : 11 - 22 (12 bit)
access : read-write

TMR0_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 0 - 1 (2 bit)
access : read-write

TMR0_ENABLE : Enable timer clock
bits : 2 - 4 (3 bit)
access : read-write

TMR0_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 3 - 6 (4 bit)
access : read-write

TMR1_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 4 - 9 (6 bit)
access : read-write

TMR1_ENABLE : Enable timer clock
bits : 6 - 12 (7 bit)
access : read-write

TMR1_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 7 - 14 (8 bit)
access : read-write

TMR2_DIV : Division factor for Timer 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 8 - 17 (10 bit)
access : read-write

TMR2_ENABLE : Enable timer clock
bits : 10 - 20 (11 bit)
access : read-write

TMR2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 11 - 22 (12 bit)
access : read-write

BREATH_ENABLE : Enables the clock
bits : 12 - 24 (13 bit)
access : read-write

WAKEUPCT_ENABLE : Enables the clock
bits : 13 - 26 (14 bit)
access : read-write

P06_TMR1_PWM_MODE : Maps Timer1_pwm onto P06, when DEBUGGER_EN = '0'. This state is preserved during deep sleep, to allow PWM output on the pad during deep sleep.
bits : 14 - 28 (15 bit)
access : read-write