Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1200C byte (0x0)
mem_usage : registers
protection :
Address transmit fifo 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep!
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 2
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep!
bits : 0 - 31 (32 bit)
access : read-write
Name of the release
address_offset : 0x10000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REL_NAME : A 4 words wide register, showing in ASCII the name of the release, eg. ftdf_107.
bits : 0 - 31 (32 bit)
access : read-only
Name of the release
address_offset : 0x10004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REL_NAME : A 4 words wide register, showing in ASCII the name of the release, eg. ftdf_107.
bits : 0 - 31 (32 bit)
access : read-only
Name of the release
address_offset : 0x10008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REL_NAME : A 4 words wide register, showing in ASCII the name of the release, eg. ftdf_107.
bits : 0 - 31 (32 bit)
access : read-only
Name of the release
address_offset : 0x1000C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REL_NAME : A 4 words wide register, showing in ASCII the name of the release, eg. ftdf_107.
bits : 0 - 31 (32 bit)
access : read-only
Build time
address_offset : 0x10010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUILDTIME : A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. 01 Dec 14 14:10.
bits : 0 - 31 (32 bit)
access : read-only
Build time
address_offset : 0x10014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUILDTIME : A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. 01 Dec 14 14:10.
bits : 0 - 31 (32 bit)
access : read-only
Build time
address_offset : 0x10018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUILDTIME : A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. 01 Dec 14 14:10.
bits : 0 - 31 (32 bit)
access : read-only
Build time
address_offset : 0x1001C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BUILDTIME : A 4 words wide register, showing in ASCII the build date (dd mmm yy) and time (hh:mm) of device, eg. 01 Dec 14 14:10.
bits : 0 - 31 (32 bit)
access : read-only
Global control register
address_offset : 0x10020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISPANCOORDINATOR : Enable/disable receiver check on address fields (0=enabled, 1=disabled)
bits : 1 - 2 (2 bit)
access : read-write
RX_DMA_REQ : Source of the RX_DMA_REQ output pin of this block.
bits : 2 - 4 (3 bit)
access : read-write
TX_DMA_REQ : Source of the TX_DMA_REQ output pin of this block.
bits : 3 - 6 (4 bit)
access : read-write
MACSIMPLEADDRESS : Simple address of the PAN coordinator
bits : 8 - 23 (16 bit)
access : read-write
MACLEENABLED : If set to '1', the Low Energy mode (also called CSL) is enabled
bits : 17 - 34 (18 bit)
access : read-write
MACTSCHENABLED : If set to '1', the TSCH mode is enabled
bits : 18 - 36 (19 bit)
access : read-write
Global control register
address_offset : 0x10024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACPANID : The PAN ID of this device. The value 0xFFFF indicates that the device is not associated to a PAN.
bits : 0 - 15 (16 bit)
access : read-write
MACSHORTADDRESS : The short address of the device. The values 0xFFFF and 0xFFFE indicate that no IEEE Short Address is available.
bits : 16 - 47 (32 bit)
access : read-write
Global control register
address_offset : 0x10028 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AEXTENDEDADDRESS_L : Unique device address, 48 bits wide, lowest 32 bit
bits : 0 - 31 (32 bit)
access : read-write
Global control register
address_offset : 0x1002C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AEXTENDEDADDRESS_H : Unique device address, 48 bits wide, highest 16 bit
bits : 0 - 31 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10030 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXONDURATION : The time (in symbol periods) the Rx must be on after setting RxEnable to '1'.
bits : 1 - 25 (25 bit)
access : read-write
RXALWAYSON : If set to '1', the receiver shall be always on if RxEnable is set to '1'.
bits : 25 - 50 (26 bit)
access : read-write
PTI_RX : This value will be used during receiving frames, during the auto ACK (when the AR bit is set in the received frame, see [FR0655] and further), a single CCA and ED scan. In TSCH mode this register will be used during the time slot in which frames can be received and consequently an Enhanced ACK can be transmitted.
bits : 27 - 57 (31 bit)
access : read-write
KEEP_PHY_EN : When the transmit or receive action is ready (LmacReady4Sleep is set), the PHY_EN signal is cleared unless the control register keep_phy_en is set to '1'. When the control register keep_phy_en is set to '1', the signal PHY_EN shall remain being set until the keep_phy_en is cleared. This will help control the behavior of the arbiter between the LMAC and the DPHY.
bits : 31 - 62 (32 bit)
access : read-write
Prop delay transmit register
address_offset : 0x10034 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPIPEPROPDELAY : Propagation delay (in us) of the tx pipe, between start of transmission (indicated by setting tx_flag_status) to the DPHY. The reset value is 0 us, which is also the closest value to the real implementation figure.
bits : 0 - 7 (8 bit)
access : read-write
Maximum time to wait for a ACK
address_offset : 0x10038 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACACKWAITDURATION : Maximum time (in symbol periods) to wait for an ACK response after transmitting a frame with the AR bit set to '1'. This value is used in the normal mode for the wait of an ACK response, irrespective if the ACK is a normal ACK or an Enhanced ACK.
bits : 0 - 7 (8 bit)
access : read-write
Maximum time to wait for an enhanced ACK frame
address_offset : 0x1003C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACENHACKWAITDURATION : Maximum time (in us) to wait for an Enhanced ACK response after transmitting a frame with the AR bit set to '1'. This value is used in the LE/CSL mode for the wait of an ACK response (which is always an Enhanced ACK).
bits : 0 - 15 (16 bit)
access : read-write
Lmac control register
address_offset : 0x10040 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYRXATTR_DEM_CCA :
bits : 0 - 1 (2 bit)
access : read-write
PHYRXATTR_DEM_LQI : Select the LQI calculation
bits : 2 - 5 (4 bit)
access : read-write
PHYRXATTR_CN : Channel Number.
bits : 4 - 11 (8 bit)
access : read-write
PHYRXATTR_CALCAP : CalCap value.
bits : 8 - 19 (12 bit)
access : read-write
PHYRXATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 12 - 26 (15 bit)
access : read-write
PHYRXATTR_HSI : HighSide injection.
bits : 15 - 30 (16 bit)
access : read-write
Lmac control register
address_offset : 0x10044 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDSCANENABLE : If set to '1', the Energy Detect scan will be performed when RxEnable is set to '1' rather than starting a receive action. The length of this scan is defined by EdScanDuration.
bits : 0 - 0 (1 bit)
access : read-write
EDSCANDURATION : The length of ED scan in symbol periods.
bits : 8 - 39 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACMAXFRAMETOTALWAITTIME : Max time to wait (in symbol periods) for a requested Data Frame or an announced broadcast frame, triggered by the FP bit in the received frame was set to '1'.
bits : 0 - 15 (16 bit)
access : read-write
CCAIDLEWAIT : Time to wait (in us) after CCA returned medium idle before starting TX-ON. Notes: 1) extra wait times are involved before a packet is really transmitted, see the relevant timing figures. 2) not applicable in TSCH mode since there macTSRxTx shall be used.
bits : 16 - 39 (24 bit)
access : read-write
ADDR_TAB_MATCH_FP_VALUE : In case the received source address matches with one of the Exp_SA registers, the value of the control register Addr_tap_match_FP_value will be inserted on the position of the FP bit. In case there is no match found, the inverse value of Addr_tap_match_FP_value will be inserted.
bits : 24 - 48 (25 bit)
access : read-write
FP_OVERRIDE : In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame.
bits : 25 - 50 (26 bit)
access : read-write
FP_FORCE_VALUE : In case the control register FP_override is set, the value of the control register FP_force_value will always be the value of the FP bit in the automatic ACK response frame.
bits : 26 - 52 (27 bit)
access : read-write
FTDF_LPDP_ENABLE : If set, not only is FP_override and SA matching done on data_request frames but to all command and data frame types (in normal mode)
bits : 27 - 54 (28 bit)
access : read-write
Lmac control register
address_offset : 0x10050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GETGENERATORVAL : If set to '1', the current values of the Wake-up (event) counter/generator (EventCurrVal) and Timestamp (symbol) counter/generator (TimeStampCurrVal and TimeStampCurrPhaseVal) will be captured. Note that this capture actually has been done when getGeneratorVal_e is set (assuming it was cleared in advance).
bits : 0 - 0 (1 bit)
access : write-only
RXENABLE : If set, receiving data may be done
bits : 1 - 2 (2 bit)
access : write-only
SINGLECCA : If set to '1', a single CCA will be performed. This can be used when e.g. the TSCH timing is not performed by the LMAC but completely by software.
bits : 2 - 4 (3 bit)
access : write-only
CSMA_CA_RESUME_SET : If set, Csma_Ca_resume_stat is set
bits : 3 - 6 (4 bit)
access : write-only
CSMA_CA_RESUME_CLEAR : If set, Csma_Ca_resume_stat is cleared
bits : 4 - 8 (5 bit)
access : write-only
Lmac status register
address_offset : 0x10054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMACREADY4SLEEP : If set to '1' this register indicates that the LMAC is ready to go to sleep.
bits : 1 - 2 (2 bit)
access : read-only
CCASTAT : The value of a single CCA, valid when CCAstat_e is set to '1'.
bits : 2 - 4 (3 bit)
access : read-only
WAKEUPTIMERENABLESTATUS : Status of WakeupTimerEnable after being clocked by LP_CLK (showing it's effective value). WakeupTimerEnableStatus can be set by setting the one-shot register WakeupTimerEnable_set and cleared by setting the one-shot register WakeupTimerEnable_clear. When WakeupTimerEnableStatus is set (after being cleared), the event counter will be reset to 0x0. This status can be used by software since WakeupTimerEnable is used in the slow LP_CLK area. Rather than waiting for a certain number of LP_CLK periods, simply scanning this status (or enable the interrupt created by WakeupTimerEnableStatus_e) will allow software to determine if this signal has been effected. Note that the rising edge of WakeupTimerEnable will reset the Wake-up (event) counter.
bits : 6 - 12 (7 bit)
access : read-only
EDSCANVALUE : The result of an ED scan.
bits : 8 - 23 (16 bit)
access : read-only
CSMA_CA_NB_STAT : Current status of the Number of Backoffs.
bits : 16 - 34 (19 bit)
access : read-only
CSMA_CA_RESUME_STAT : In case Csma_Ca_resume_stat is set the LMAC will - use the value of Csma_Ca_NB_val in the CSMA-CA process rather than the initial value 0d. - immediately perform CCA after the sleep, not waiting for the backoff time. - reset Csma_Ca_resume_stat when it resumes CSMA-CA after the sleep.
bits : 19 - 38 (20 bit)
access : read-only
CSMA_CA_BO_STAT : The value of the currently calculated BackOff value. To be used for the sleep time calculation in case of sleep during the BackOff time.
bits : 24 - 55 (32 bit)
access : read-only
Value of event generator
address_offset : 0x10058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EVENTCURRVAL : The value of the captured Event generator (Wake-up counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set).
bits : 0 - 24 (25 bit)
access : read-only
Value of timestamp generator
address_offset : 0x1005C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMESTAMPCURRVAL : The value of captured timestamp generator (symbol counter) (initiated by getGeneratorVal, valid when getGeneratorVal_e is set)
bits : 0 - 31 (32 bit)
access : read-only
Lmac control register
address_offset : 0x10060 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYSLEEPWAIT : The minume time (in us) required between the clear to '0' and set to '1' of PHY_EN. When the signal PHY_EN is deasserted, it will not be asserted within the time phySleepWait.
bits : 0 - 7 (8 bit)
access : read-write
RXPIPEPROPDELAY : The control register RxPipePropDelay indicates the propagation delay in ~s of the Rx pipeline between the last symbol being captured at the DPHY interface and the data valid indication to the LMAC controller.
bits : 8 - 23 (16 bit)
access : read-write
PHYACKATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write
PHYACKATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write
PHYACKATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write
PHYACKATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write
PHYACKATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10064 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACK_RESPONSE_DELAY : In order to have some flexibility the control register Ack_Response_Delay indicates the Acknowledge response time in ~s. The default value shall is 192 ~s (12 symbols).
bits : 0 - 7 (8 bit)
access : read-write
CCASTATWAIT : The output CCASTAT is valid after 8 symbols + phyRxStartup. The 8 symbols are programmable by control registerCcaStatWait (in symbol periods). Default value is 8d.
bits : 8 - 19 (12 bit)
access : read-write
PHYCSMACAATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write
PHYCSMACAATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write
PHYCSMACAATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write
PHYCSMACAATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write
PHYCSMACAATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10068 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIFSPERIOD : The Long IFS period is programmable by LifsPeriod (in symbols). The default is 40 symbols (640 us),
bits : 0 - 7 (8 bit)
access : read-write
SIFSPERIOD : The Short IFS period is programmable by SifsPeriod (in symbols). The default is 12 symbols (192 is).
bits : 8 - 23 (16 bit)
access : read-write
WUIFSPERIOD : The WakeUp IFS period is programmable by WUifsPeriod (in symbols). The default is 12 symbols (192 us).
bits : 16 - 39 (24 bit)
access : read-write
Lmac control register
address_offset : 0x1006C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACRXTOTALCYCLETIME : In CSL mode it can be decided to disable the PHY Rx (Rx-off) after reception of a Wake-up frame and enable the PHY Rx (Rx-on) when the data frame is to be expected, based on the received RZ time. In order to make it easier to calculate if it is efficient to switch to Rx-off and Rx-on again, a control register indicates the time needed to disable and enable the PHY Rx: macRxTotalCycleTime (resolution is 10 symbol periods)
bits : 0 - 15 (16 bit)
access : read-write
MACDISCARXOFFTORZ : The switching off and on of the PHY Rx (see macRxTotalCycleTime) can be disabled whith the control register macDisCaRxOfftoRZ. 0 : Disabled 1 : Enabled
bits : 16 - 32 (17 bit)
access : read-write
CSMA_CA_NB_VAL : Number of backoffs value in case of a CSMA-CA resume action.
bits : 17 - 36 (20 bit)
access : read-write
CSMA_CA_BO_THRESHOLD : If the backoff time calculated in the CSMA-CA procedure as described in [FR3280] is equal to or higher than the control register Csma_Ca_BO_threshold[8] (resolution 320us, see [FR3290]) the event register Csma_Ca_BO_thr_e will be set and an interrupt. In case Csma_Ca_BO_threshold equals 0xFF no check will be performed and consequently Csma_Ca_BO_thr_e will not be set and no interrupt will be generated.
bits : 24 - 55 (32 bit)
access : read-write
Lmac delta control register
address_offset : 0x10070 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMACREADY4SLEEP_D : Delta bit for register LmacReady4sleep. This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3].
bits : 1 - 2 (2 bit)
access : read-write
SYNCTIMESTAMP_E : The SyncTimeStamp_e event is set to '1' when the TimeStampgenerator is loaded with SyncTimeStampVal. This occurs at the rising edge of lp_clk when SyncTimeStampEna is set and the value of the Event generator is equal to the value SyncTimestampThr. This event bit contributes to ftdf_ce[3].
bits : 2 - 4 (3 bit)
access : read-write
SYMBOLTIMETHR_E : Event, set to '1' when the symboltime counter matched SymbolTimeThr This event bit contributes to ftdf_ce[3].
bits : 3 - 6 (4 bit)
access : read-write
SYMBOLTIME2THR_E : Event, set to '1' when the symboltime counter matched SymbolTime2Thr This event bit contributes to ftdf_ce[3].
bits : 4 - 8 (5 bit)
access : read-write
GETGENERATORVAL_E : Event, set to '1' to indicate that the the getGeneratorVal request is completed. This event bit contributes to ftdf_ce[3].
bits : 5 - 10 (6 bit)
access : read-write
WAKEUPTIMERENABLESTATUS_D : Delta which indicates that WakeupTimerEnableStatus has changed This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[3].
bits : 6 - 12 (7 bit)
access : read-write
Value of timestamp generator phase within a symbol
address_offset : 0x10074 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMESTAMPCURRPHASEVAL : Value of captured timestamp generator phase within a symbol (initiated by getGeneratorVal, valid when getGeneratorVal_e is set)
bits : 0 - 7 (8 bit)
access : read-only
Time left until next ACK is sent (us)
address_offset : 0x10078 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACTSTXACKDELAYVAL : The time (in us) left until the ack frame is sent by the lmac. This can be used by software to determine if there is enough time left to send the, by software created, Enhanced ACK frame.
bits : 0 - 15 (16 bit)
access : read-only
Lmac mask control register
address_offset : 0x10080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMACREADY4SLEEP_M : Mask bit for delta bit LmacReady4sleep_d. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
SYNCTIMESTAMP_M : Mask bit for event register SyncTimeStamp_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
SYMBOLTIMETHR_M : Mask for SymbolTimeThr_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
SYMBOLTIME2THR_M : Mask for SymbolTime2Thr_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 4 - 8 (5 bit)
access : read-write
GETGENERATORVAL_M : Mask for getGeneratorVal_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 5 - 10 (6 bit)
access : read-write
WAKEUPTIMERENABLESTATUS_M : Mask for WakeupTimerEnableStatus_d The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 6 - 12 (7 bit)
access : read-write
Lmac event regsiter
address_offset : 0x10090 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDSCANREADY_E : The event EdScanReady_e is set to '1' to notify that the ED scan is ready. This event bit contributes to ftdf_ce[1].
bits : 0 - 0 (1 bit)
access : read-write
CCASTAT_E : If set to '1', the single CCA is ready This event bit contributes to ftdf_ce[1].
bits : 1 - 2 (2 bit)
access : read-write
RXTIMEREXPIRED_E : Set to '1' if one of the timers enabling the Rx-on mode expires without having received any valid frame. This event bit contributes to ftdf_ce[1].
bits : 2 - 4 (3 bit)
access : read-write
CSMA_CA_BO_THR_E : If set, the calculated backoff time is more than Csma_Ca_BO_threshold. This event bit contributes to ftdf_ce[1].
bits : 3 - 6 (4 bit)
access : read-write
Lmac mask register
address_offset : 0x10094 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EDSCANREADY_M : Mask bit for event EdScanReady_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
CCASTAT_M : Mask bit for event CCAstat_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
RXTIMEREXPIRED_M : Mask bit for event RxTimerExpired_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
CSMA_CA_BO_THR_M : Mask bit for event Csma_Ca_BO_thr_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
Lmax manual PHY register
address_offset : 0x100A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMAC_MANUAL_MODE : If the control register lmac_manual_mode is set to '1', the LMAC controller control signals should be controlled by the lmac_manual_control registers
bits : 0 - 0 (1 bit)
access : read-write
LMAC_MANUAL_PHY_EN : lmac_manual_phy_en controls the PHY_EN interface signal when lmac_manual_mode is set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
LMAC_MANUAL_TX_EN : lmac_manual_tx_en controls the TX_EN interface signal when lmac_manual_mode is set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
LMAC_MANUAL_RX_EN : lmac_manual_rx_en controls the RX_EN interface signal when lmac_manual_mode is set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
LMAC_MANUAL_RX_PIPE_EN : lmac_manual_rx_pipe_en controls the rx_enable signal towards the rx pipeline when lmac_manual_mode is set to '1'.
bits : 4 - 8 (5 bit)
access : read-write
LMAC_MANUAL_ED_REQUEST : lmac_manual_ed_request controls the ED_REQUEST interface signal when lmac_manual_mode is set to '1'.
bits : 5 - 10 (6 bit)
access : read-write
LMAC_MANUAL_TX_FRM_NR : lmac_manual_tx_frm_nr controls the entry in the tx buffer to be transmitted when lmac_manual_mode is set to '1'.
bits : 6 - 13 (8 bit)
access : read-write
LMAC_MANUAL_PTI : lmac_manual_pti controls the PTI interface signal when lmac_manual_mode is set to '1'.
bits : 8 - 19 (12 bit)
access : read-write
LMAC_MANUAL_PHY_ATTR_DEM_PTI : DEM packet information.
bits : 16 - 35 (20 bit)
access : read-write
LMAC_MANUAL_PHY_ATTR_CN : Channel Number.
bits : 20 - 43 (24 bit)
access : read-write
LMAC_MANUAL_PHY_ATTR_CALCAP : CalCap value.
bits : 24 - 51 (28 bit)
access : read-write
LMAC_MANUAL_PHY_ATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 28 - 58 (31 bit)
access : read-write
LMAC_MANUAL_PHY_ATTR_HSI : HighSide injection.
bits : 31 - 62 (32 bit)
access : read-write
One shot register triggers transmission in manual mode
address_offset : 0x100A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMAC_MANUAL_TX_START : One shot register which triggers the transmission of a frame from the tx buffer in lmac_manual_mode to '1'.
bits : 0 - 0 (1 bit)
access : write-only
Lmac status register in manual mode
address_offset : 0x100A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMAC_MANUAL_CCA_STAT : lmac_manual_cca_stat shows the status of the CCA_STAT DPHY interface signal.
bits : 0 - 0 (1 bit)
access : read-only
LMAC_MANUAL_ED_STAT : lmac_manual_ed_stat shows the status of the ED_STAT DPHY interface signal.
bits : 8 - 23 (16 bit)
access : read-only
Lmac control register
address_offset : 0x10100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACWUPERIOD : In CSL mode, the Wake-up duration in symbol periods. During this period, Wake-up frames will be transmitted.
bits : 0 - 15 (16 bit)
access : read-write
MACCSLSAMPLEPERIOD : In CSL mode, when performing a idle listening, the receiver is enabled for at least macCSLsamplePeriod (in symbol oeriods).
bits : 16 - 47 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACCSLSTARTSAMPLETIME : In CSL mode, the control register macCSLstartSampleTime indicates the TimeStamp generator time (in symbol periods) when to start listening (called idle listening) or transmitting (when tx_flag_status is set).
bits : 0 - 31 (32 bit)
access : read-write
Lmac control register
address_offset : 0x10108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACCSLDATAPERIOD : In CSL mode, after the wake-up sequence a data frame is expected. The receiver will be enabled for at least a period of macCSLdataPeriod (in symbol periods).
bits : 0 - 15 (16 bit)
access : read-write
MACCSLFRAMEPENDINGWAITT : In CSL mode, if a non Wake-up frame with Frame Pending bit = '1' is received, the receiver is enabled for at least an extra period of macCSLFramePendingWaitT (in symbol periods) after the end of the received frame. The time the Enhanced ACK transmission lasts (if applicable) is included in this time.
bits : 16 - 47 (32 bit)
access : read-write
Lmac control register
address_offset : 0x1010C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACWURZCORRECTION : In CSL mode, this register shall be used if the Wake-up frame to be transmitted is larger than 15 octets. It shall indicate the amount of extra data in a Wake-up frame after the RZ position in the frame (in 10 symbol periods). This correction is needed to make sure that the correct RZ time is filled in by the LMAC.
bits : 0 - 7 (8 bit)
access : read-write
MACCSLMARGINRZ : In CSL mode, the software can set the margin for the expected frame by control register macCSLmarginRZ (in 10 symbol periods). The LMAC will make sure that the receiver is ready to receive data this amount of time earlier than to be expected by the received RZ time.
bits : 16 - 35 (20 bit)
access : read-write
MACRZZEROVAL : In CSL mode, if the current RZtime is less or Equal to macRZzeroVal an RZtime with value zero is inserted in the wakeup frame. So this is by default the last Wake-up frame of a Wake-up sequence.
bits : 28 - 59 (32 bit)
access : read-write
Security register
address_offset : 0x10110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECTXRXN : Encryption/decryption mode: see register secEntry.
bits : 1 - 2 (2 bit)
access : read-write
SECENTRY : Encryption/decryption mode: the software indicates by the control registers secEntry and secTxRxn which entry to use and if it's from the Tx or Rx buffer ('1' resp. '0').
bits : 8 - 19 (12 bit)
access : read-write
SECALENGTH : Encryption/decryption mode: the length of the a_data is indicated by control register secAlength (in bytes). The end of the a_data is the start point of the m_data. So secAlength must also be set if security level==4.
bits : 16 - 38 (23 bit)
access : read-write
SECMLENGTH : Encryption/decryption mode: the length of the m_data is indicated by control register secMlength (in bytes).
bits : 24 - 54 (31 bit)
access : read-write
SECENCDECN : Encryption/decryption mode: the control register secEncDecn indicates whether to encrypt ('1') or decrypt ('0') the data.
bits : 31 - 62 (32 bit)
access : read-write
Security register
address_offset : 0x10114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECAUTHFLAGS : Encryption/decryption mode: register secAuthFlags contains the authentication flags fields. bit[7] is '0' bit[6] is A_data present bit[5:3]: 3-bit security level of m_data bit[2:0]: 3-bit security level of a_data.
bits : 0 - 7 (8 bit)
access : read-write
SECENCRFLAGS : Encryption/decryption mode: register secEncrFlags contains the encryption flags field. Bits [2:0] are the 3-bit encoding flags of a_data, the other bits msut be set to '0'.
bits : 8 - 23 (16 bit)
access : read-write
Seckey register
address_offset : 0x10118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECKEY_0 : Encryption/decryption mode: Registers secKey[0..3] contain the key to be used.
bits : 0 - 31 (32 bit)
access : read-write
Seckey register
address_offset : 0x1011C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECKEY_1 : Encryption/decryption mode: see register secKey_0
bits : 0 - 31 (32 bit)
access : read-write
SecKey register
address_offset : 0x10120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECKEY_2 : Encryption/decryption mode: see register secKey_0
bits : 0 - 31 (32 bit)
access : read-write
Seckey register
address_offset : 0x10124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECKEY_3 : Encryption/decryption mode: see register secKey_0
bits : 0 - 31 (32 bit)
access : read-write
Nonce register used for encryption/decryption
address_offset : 0x10128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECNONCE_0 : Encryption/decryption mode: register secNonce[0..3] contains the Nonce to be used for encryption/decryption.
bits : 0 - 31 (32 bit)
access : read-write
Nonce register used for encryption/decryption
address_offset : 0x1012C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECNONCE_1 : Encryption/decryption mode: see register Nonce_0
bits : 0 - 31 (32 bit)
access : read-write
Nonce register used for encryption/decryption
address_offset : 0x10130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECNONCE_2 : Encryption/decryption mode: see register Nonce_0
bits : 0 - 31 (32 bit)
access : read-write
Nonce register used for encryption/decryption
address_offset : 0x10134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECNONCE_3 : Encryption/decryption mode: see register Nonce_0
bits : 0 - 7 (8 bit)
access : read-write
One shot register to start encryption/decryption
address_offset : 0x10138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECABORT : Encryption/decryption mode: see register Nonce_0
bits : 0 - 0 (1 bit)
access : write-only
SECSTART : Encryption/decryption mode: one_shot register to start the encryption, decryption and authentication support task.
bits : 1 - 2 (2 bit)
access : write-only
Security status register
address_offset : 0x10140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECBUSY : Encryption/decryption mode: register secBusy indicates if the encryption/decryption process is still running.
bits : 0 - 0 (1 bit)
access : read-only
SECAUTHFAIL : Encryption/decryption mode: in case of decryption, the status bit secAuthFail will be set when the authentication has failed.
bits : 1 - 2 (2 bit)
access : read-only
security event register
address_offset : 0x10150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECREADY_E : Encryption/decryption mode: the Event bit secReady_e is set to '1' when the authentication process is ready (i.e. secBusy is cleared). This event bit contributes to ftdf_ce[3].
bits : 0 - 0 (1 bit)
access : read-write
security event mask register
address_offset : 0x10154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECREADY_M : Mask bit for event secReady_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Lmac tsch control register
address_offset : 0x10160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACTSTXACKDELAY : TSCH mode: the time between the end of a Rx frame and the start of an Enhanced Acknowlegde frame.
bits : 0 - 15 (16 bit)
access : read-write
MACTSRXWAIT : TSCH mode: The times to wait for start of frame
bits : 16 - 47 (32 bit)
access : read-write
Lmac tsch control register
address_offset : 0x10164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACTSRXTX : TSCH mode: The time between the CCA and the TX of a frame
bits : 0 - 15 (16 bit)
access : read-write
Lmac tsch control register
address_offset : 0x10168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACTSRXACKDELAY : TSCH mode: End of frame to when the transmitter shall listen for Acknowledgement
bits : 0 - 15 (16 bit)
access : read-write
MACTSACKWAIT : TSCH mode: The minimum time to wait for start of an Acknowledgement
bits : 16 - 47 (32 bit)
access : read-write
Lmac PHY parameter register
address_offset : 0x10180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBITPOS_0 : DPHY interface: control rxBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are rxBitPos_0 = 0, rxBitPos_1 = 1, rxBitPos_2 = 2, etc. Note1 that this is a conversion from rx DPHY interface to the internal data byte So for(n=7 n>=0 n--) rx_data(n) = dphy_bit(tx_BitPos(n)) endfor Note2 that rxBitPos and txBitPos must have inverse functions.
bits : 0 - 2 (3 bit)
access : read-write
RXBITPOS_1 : DPHY interface: see rxBitPos_0
bits : 4 - 10 (7 bit)
access : read-write
RXBITPOS_2 : DPHY interface: see rxBitPos_0
bits : 8 - 18 (11 bit)
access : read-write
RXBITPOS_3 : DPHY interface: see rxBitPos_0
bits : 12 - 26 (15 bit)
access : read-write
RXBITPOS_4 : DPHY interface: see rxBitPos_0
bits : 16 - 34 (19 bit)
access : read-write
RXBITPOS_5 : DPHY interface: see rxBitPos_0
bits : 20 - 42 (23 bit)
access : read-write
RXBITPOS_6 : DPHY interface: see rxBitPos_0
bits : 24 - 50 (27 bit)
access : read-write
RXBITPOS_7 : DPHY interface: see rxBitPos_0
bits : 28 - 58 (31 bit)
access : read-write
Lmac PHY parameter register
address_offset : 0x10184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBITPOS_0 : DPHY interface: control txBitPos(8)(3) controls the position that a bit should have at the DPHY interface. So the default values are txBitPos_0 = 0, txBitPos_1 = 1, txBitPos_2 = 2, etc. Note1 that this is a conversion from internal data byte to the DPHY interface. So for(n=7 n>=0 n--) tx_dphy_bit(n) = tx_data(tx_BitPos(n)) endfor Note2 that txBitPos and rxBitPos must have inverse functions.
bits : 0 - 2 (3 bit)
access : read-write
TXBITPOS_1 : DPHY interface: see txBitPos_0
bits : 4 - 10 (7 bit)
access : read-write
TXBITPOS_2 : DPHY interface: see txBitPos_0
bits : 8 - 18 (11 bit)
access : read-write
TXBITPOS_3 : DPHY interface: see txBitPos_0
bits : 12 - 26 (15 bit)
access : read-write
TXBITPOS_4 : DPHY interface: see txBitPos_0
bits : 16 - 34 (19 bit)
access : read-write
TXBITPOS_5 : DPHY interface: see txBitPos_0
bits : 20 - 42 (23 bit)
access : read-write
TXBITPOS_6 : DPHY interface: see txBitPos_0
bits : 24 - 50 (27 bit)
access : read-write
TXBITPOS_7 : DPHY interface: see txBitPos_0
bits : 28 - 58 (31 bit)
access : read-write
Lmac PHY parameter register
address_offset : 0x10188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYTXSTARTUP : DPHY interface: the phy wait time (in us) before transmission of a frame may start.
bits : 0 - 7 (8 bit)
access : read-write
PHYTXLATENCY : DPHY interface: phy delay (in us) between DPHY interface and air interface.
bits : 8 - 23 (16 bit)
access : read-write
PHYTXFINISH : DPHY interface: Phy wait time (in us) before deasserting TX_EN after deasserting TX_VALID.
bits : 16 - 39 (24 bit)
access : read-write
PHYTRXWAIT : DPHY interface: Phy wait time (in us) between deassertion of TX_EN and assertion of RX_EN or vice versa.
bits : 24 - 55 (32 bit)
access : read-write
Lmac PHY parameter register
address_offset : 0x1018C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PHYRXSTARTUP : DPHY interface: Phy wait time (in us) before receiving of a frame may start.
bits : 0 - 7 (8 bit)
access : read-write
PHYRXLATENCY : DPHY interface: Phy delay (in us) between air and DPHY interface.
bits : 8 - 23 (16 bit)
access : read-write
PHYENABLE : DPHY interface: Asserting the DPHY interface signals TX_EN or RX_EN does not take place within the time phyEnable after asserting the signal PHY_EN. (in us).
bits : 16 - 39 (24 bit)
access : read-write
USE_LEGACY_PHY_EN : If the control register use_legacy_phy_en is set (default), the output signal PHY_TRANSACTION will be sourced by PHY_EN rather than PHY_TRANSACTION.
bits : 24 - 48 (25 bit)
access : read-write
Receive control register
address_offset : 0x10200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGRXTRANSPARENTMODE : If set yo '1', Rx pipe is fully set in transparent mode (for debug purpose).
bits : 0 - 0 (1 bit)
access : read-write
RXBEACONONLY : If set to '1', only Beacons frames are accepted
bits : 1 - 2 (2 bit)
access : read-write
RXCOORDREALIGNONLY : If set to '1', only Coordinator Realignment frames are accepted
bits : 2 - 4 (3 bit)
access : read-write
RX_READ_BUF_PTR : Indication where new data will be read All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values.
bits : 3 - 9 (7 bit)
access : read-write
DISRXFRMPENDINGCA : Whan the control register DisRxFrmPendingCa is set to '1', the notification of the received FP bit to the LMAC Controller is disabled and thus no consequent actions will take place.
bits : 7 - 14 (8 bit)
access : read-write
DISRXACKREQUESTCA : When the control register DisRxAckRequestca is set to '1' all consequent actions for a received Acknowledge Request bit are disabled.
bits : 8 - 16 (9 bit)
access : read-write
MACALWAYSPASSCRCERROR : If set to '1', a FCS error will not drop the frame. However, an FCS error will be reported in the Rx meta data (crc16_error is set to '1').
bits : 9 - 18 (10 bit)
access : read-write
DISDATAREQUESTCA : When the control register DisDataRequestCa is set, the notification of the received Data Request is disabled.
bits : 10 - 20 (11 bit)
access : read-write
MACALWAYSPASSRESFRAMEVERSION : If set to '1', a packet with a reserved FrameVersion shall not be dropped
bits : 11 - 22 (12 bit)
access : read-write
MACALWAYSPASSWRONGDPANID : If register macAlwaysPassWrongDPANId is set to '1', packet with a wrong Destiantion PanID will not be dropped. However, in case of an FCS error, the packet is dropped.
bits : 12 - 24 (13 bit)
access : read-write
MACALWAYSPASSWRONGDADDR : If set to '1', a packet with a wrong DAddr is not dropped
bits : 13 - 26 (14 bit)
access : read-write
MACALWAYSPASSBEACONWRONGPANID : If the control register macAlwaysPassBeaconWrongPANId is set, the frame is not dropped in case of a mismatch in PAN-ID, irrespective of the setting of RxBeaconOnly.
bits : 14 - 28 (15 bit)
access : read-write
MACALWAYSPASSTOPANCOORDINATOR : When the control register macAlwaysPassToPanCoordinator is set to '1', the frame is not dropped due to a span_coord_error. However, in case of an FCS error, the packet is dropped.
bits : 15 - 30 (16 bit)
access : read-write
MACALWAYSPASSFRMTYPE : The control registers macAlwaysPassFrmType[7:0], shall control if this Frame Type shall be dropped. If a bit is set to '1', the Frame Type corresponding with the bit position is not dropped, even in case of a CRC error. Example: if bit 3 is set to '1', Frame Type 3 shall not be dropped. If there is a FCS error, the error shall be reported in the Rx meta data (crc16_error is set to '1').
bits : 16 - 39 (24 bit)
access : read-write
MACALWAYSPASSWAKEUP : In CSL mode, if the control register macAlwaysPassWakeUp is set to '1', received Wake- up frames for this device are put into the Rx packet buffer without notifying the LMAC Controller (part of transparent mode control).
bits : 24 - 48 (25 bit)
access : read-write
MACPASSWAKEUP : In CSL mode, if set to '1', WakeUp frames will be put into the Rx buffer. This can be useful for software to parse the WakeUp frame.
bits : 25 - 50 (26 bit)
access : read-write
MACIMPLICITBROADCAST : If set to '1', Frame Version 2 frames without Daddr or DPANId shall be accepted.
bits : 26 - 52 (27 bit)
access : read-write
DISRXACKRECEIVEDCA : If set to '1', the LMAC controller shall ignore all consequent actions upon a set AR bit in the transmitted frame (e.g. enabling Rx-on mode after the transmission and wait for an ACK).
bits : 27 - 54 (28 bit)
access : read-write
Receive event register
address_offset : 0x10204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXSOF_E : Set to '1' when RX_SOF has been detected. This event bit contributes to ftdf_ce[1].
bits : 0 - 0 (1 bit)
access : read-write
RX_OVERFLOW_E : If set to '1' it indicates that the Rx packet buffer has an overflow. This event bit contributes to ftdf_ce[1].
bits : 1 - 2 (2 bit)
access : read-write
RX_BUF_AVAIL_E : If set to '1' it indicates that a new valid packet has been completely received This event bit contributes to ftdf_ce[1].
bits : 2 - 4 (3 bit)
access : read-write
RXBYTE_E : If set to '1' it indicates that the first byte of a new packet has been received This event bit contributes to ftdf_ce[1].
bits : 3 - 6 (4 bit)
access : read-write
Receive event mask register
address_offset : 0x10208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXSOF_M : Mask bit for event RxSof_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
RX_OVERFLOW_M : Mask bit for event rx_overflow_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
RX_BUF_AVAIL_M : Mask bit for event rx_buf_avail_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 2 - 4 (3 bit)
access : read-write
RXBYTE_M : Mask bit for event rxbyte_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 3 - 6 (4 bit)
access : read-write
Receive status register
address_offset : 0x1020C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_BUFF_IS_FULL : If set to '1', it indicates that the Rx packet buffer is full
bits : 0 - 0 (1 bit)
access : read-only
RX_WRITE_BUF_PTR : Indication where new data will be written. All four bits shall be used when using these pointer values (0d - 15d). However, the Receive Packet buffer has a size of 8 entries. So reading the Receive Packet buffer entries shall use the mod8 of the pointer values.
bits : 1 - 5 (5 bit)
access : read-only
Value timestamp generator
address_offset : 0x10210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYMBOLTIMESNAPSHOTVAL : The Status register SymbolTimeSnapshotVal indicates the actual value of the TimeStamp generator. This can be useful for software to use e.g. in CSL mode at creating an Enhanced ACK to calculate the CSL phase and period.
bits : 0 - 31 (32 bit)
access : read-only
Receive status delta register
address_offset : 0x10220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_BUFF_IS_FULL_D : Delta bit of status rx_buff_is_full. This delta bit is set to '1' on each change of this status, contributes to ftdf_ce[1].
bits : 0 - 0 (1 bit)
access : read-write
Receive status delta mask register
address_offset : 0x10224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_BUFF_IS_FULL_M : Mask bit for delta bit rx_buff_is_full_d The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Transmit control register
address_offset : 0x10240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBGTXTRANSPARENTMODE : If set to '1', the MPDU octets pass transparently through the MAC in the transmit direction (for debug purpose).
bits : 0 - 0 (1 bit)
access : read-write
MACMAXBE : CSMA-CA: Maximum Backoff Exponent (range 3-8)
bits : 4 - 11 (8 bit)
access : read-write
MACMINBE : CSMA-CA: Minimum Backoff Exponent (range 0-macMaxBE)
bits : 8 - 19 (12 bit)
access : read-write
MACMAXCSMABACKOFFS : CSMA-CA: Maximum number of CSMA-CA backoffs (range 0-5)
bits : 12 - 26 (15 bit)
access : read-write
Selection register events
address_offset : 0x10250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTDF_CE : Composite service request from ftdf macro (see FR0400 in v40.100.2.41.pdf), set to '1' if the branch currently contributes to the interrupt. Bit 0 = unused Bit 1 = rx interrupts Bit 2 = unused Bit 3 = miscelaneous interrupts Bit 4 = tx interrupts Bit 5 = Reserved Upon an interrupt, using the ftdf_ce bits it can be checked which interrupt branch creates this interrupt.
bits : 0 - 5 (6 bit)
access : read-only
Mask selection register events
address_offset : 0x10254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FTDF_CM : mask bits for ftf_ce. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 5 (6 bit)
access : read-write
Threshold timestamp generator
address_offset : 0x10304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTIMESTAMPTHR : Threshold for synchronize the timestamp counter: at this value of the event counter the synchronization of the timestamp (symbol) counter is done (if SyncTimeStampEna is set to '1'). If SyncTimeStamp_e is set to '1' the synchronization has taken place.
bits : 0 - 24 (25 bit)
access : read-write
Value timestamp generator
address_offset : 0x10308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTIMESTAMPVAL : Value to synchronize the timestamp counter with at the moment indicated by SyncTimeStampThr.
bits : 0 - 31 (32 bit)
access : read-write
Timer control register
address_offset : 0x1030C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTIMESTAMPENA : If set to '1', the synchronization of the timestamp counter after a deep-sleep cycle will be performed when SyncTimeStampThr matches the value of the event (wake-up) counter.
bits : 1 - 2 (2 bit)
access : read-write
Transmitted acknowledgment frames
address_offset : 0x10310 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACTXSTDACKFRMCNT : Traffic counter: the number of standard Acknowledgment frames transmitted after the last deep-sleep cycle.
bits : 0 - 31 (32 bit)
access : read-only
Received acknowledgment frames
address_offset : 0x10314 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACRXSTDACKFRMOKCNT : Traffic counter: the number of Standard Acknowledgment frames received after the last deep-sleep cycle.
bits : 0 - 31 (32 bit)
access : read-only
Discarded frames register
address_offset : 0x10318 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACRXADDRFAILFRMCNT : Traffic counter: the number of frames discarded due to incorrect address or PAN Id after the last deep-sleep cycle.
bits : 0 - 31 (32 bit)
access : read-only
Unsupported frames register
address_offset : 0x1031C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACRXUNSUPFRMCNT : Traffic counter: the number of frames which do pass the checks but are not supported after the last deep-sleep cycle.
bits : 0 - 31 (32 bit)
access : read-only
Timestamp phase value regsiter
address_offset : 0x10320 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYNCTIMESTAMPPHASEVAL : Value to synchronize the timestamp counter phase with at the moment indicated by SyncTimeStampThr. Please note the +1 correction needed for most accurate result (+0.5 is than the average error, resulting is a just too fast clock).
bits : 0 - 7 (8 bit)
access : read-write
Lmac FCS error register
address_offset : 0x10340 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACFCSERRORCOUNT : metrics counter: the number of received frames that were discarded due to an incorrect FCS after the last deep-sleep cycle.
bits : 0 - 31 (32 bit)
access : read-only
Lmax reset register
address_offset : 0x10360 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LMACRESET_CONTROL : LmacReset_control: A '1' resets LMAC Controller (for debug and MLME-reset)
bits : 0 - 0 (1 bit)
access : write-only
LMACRESET_RX : LmacReset_rx: A '1' resets LMAC rx pipeline (for debug and MLME-reset)
bits : 1 - 2 (2 bit)
access : write-only
LMACRESET_TX : LmacReset_tx: A '1' resets LMAC tx pipeline (for debug and MLME-reset)
bits : 2 - 4 (3 bit)
access : write-only
LMACRESET_AHB : LmacReset_ahb: A '1' resets LMAC ahb interface (for debug and MLME-reset)
bits : 3 - 6 (4 bit)
access : write-only
LMACRESET_OREG : LmacReset_oreg: A '1' resets LMAC on_off regmap (for debug and MLME-reset) #$LmacReset_areg@on_off_regmap #LmacReset_areg: A '1' Resets LMAC always_on regmap (for debug and MLME-reset)
bits : 4 - 8 (5 bit)
access : write-only
LMACRESET_TSTIM : LmacReset_tstim: A '1' resets LMAC timestamp timer (for debug and MLME-reset)
bits : 6 - 12 (7 bit)
access : write-only
LMACRESET_SEC : LmacReset_sec: A '1' resets LMAC security (for debug and MLME-reset) #$LmacReset_wutim@on_off_regmap #LmacReset_wutim: A '1' Resets LMAC wake-up timer (for debug and MLME-reset)
bits : 7 - 14 (8 bit)
access : write-only
LMACRESET_COUNT : LmacReset_count: A '1' resets LMAC mac counters (for debug and MLME-reset)
bits : 9 - 18 (10 bit)
access : write-only
LMACRESET_TIMCTRL : LmacReset_count: A '1' resets LMAC timing control block (for debug and MLME-reset)
bits : 10 - 20 (11 bit)
access : write-only
LMACGLOBRESET_COUNT : If set, the LMAC performance and traffic counters will be reset. Use this register for functionally reset these counters.
bits : 16 - 32 (17 bit)
access : write-only
address_offset : 0x10364 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUPTIMERENABLE_SET : If set, WakeupTimerEnableStatus will be set.
bits : 0 - 0 (1 bit)
access : write-only
WAKEUPTIMERENABLE_CLEAR : If set, WakeupTimerEnableStatus will be cleared.
bits : 1 - 2 (2 bit)
access : write-only
Symboltime threshold register 1
address_offset : 0x10380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYMBOLTIMETHR : Symboltime Threshold to generate a general interrupt when this value matches the symbol counter value.
bits : 0 - 31 (32 bit)
access : read-write
Symboltime threshold register 2
address_offset : 0x10384 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYMBOLTIME2THR : Symboltime 2 Threshold to generate a general interrupt when this value matches the symbol counter value.
bits : 0 - 31 (32 bit)
access : read-write
Debug control register
address_offset : 0x10390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DBG_RX_INPUT : If set to '1', the Rx debug interface will be selected as input for the Rx pipeline rather than the DPHY interface signals. Note that in this mode, DBG_RX_DATA[3:0] and DBG_RX_SOF are sourced by another source (outside the scope of the LMAC) while the other Rx inputs (CCA_STAT, LQI[7:0] and ED_STAT[7:0]) are forced to 0x00.
bits : 8 - 16 (9 bit)
access : read-write
Transmit first byte register
address_offset : 0x10394 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBYTE_E : If set to '1', it indicates the first byte of a frame is transmitted This event bit contributes to ftdf_ce[4].
bits : 0 - 0 (1 bit)
access : read-write
TX_LAST_SYMBOL_E : If set to '1', it indicates the last symbol of a frame is transmitted This event bit contributes to ftdf_ce[4].
bits : 1 - 2 (2 bit)
access : read-write
Transmit first byte mask register
address_offset : 0x10398 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBYTE_M : Mask bit for event txbyte_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
TX_LAST_SYMBOL_M : Mask bit for event tx_last_symbol_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 1 - 2 (2 bit)
access : read-write
Transmit packet ready for transmission register 0
address_offset : 0x10400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_STAT : Tx meta data per entry: if set to '1', the packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only
Clear flag register 0
address_offset : 0x10404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_E : Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. This event bit contributes to ftdf_ce[4].
bits : 0 - 0 (1 bit)
access : read-write
Mask flag register 0
address_offset : 0x10408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_M : Tx meta data per entry: Mask bit for event tx_flag_clear_e. The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Transmit priority register 0
address_offset : 0x10410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PRIORITY : Tx meta data per entry: Priority of packet
bits : 0 - 3 (4 bit)
access : read-write
ISWAKEUP : Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame.
bits : 4 - 8 (5 bit)
access : read-write
PTI_TX : This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data.
bits : 8 - 19 (12 bit)
access : read-write
Transmit packet ready for transmission register 1
address_offset : 0x10420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_STAT : Tx meta data per entry: if set to '1', the packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only
Clear flag register 1
address_offset : 0x10424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_E : Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. This event bit contributes to ftdf_ce[4].
bits : 0 - 0 (1 bit)
access : read-write
Mask flag register 1
address_offset : 0x10428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_M : Tx meta data per entry: Mask bit for event tx_flag_clear_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Transmit priority register 1
address_offset : 0x10430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PRIORITY : Tx meta data per entry: Priority of packet
bits : 0 - 3 (4 bit)
access : read-write
ISWAKEUP : Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame.
bits : 4 - 8 (5 bit)
access : read-write
PTI_TX : This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data.
bits : 8 - 19 (12 bit)
access : read-write
Transmit packet ready for transmission register 2
address_offset : 0x10440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_STAT : Tx meta data per entry: if set to '1', the packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only
Clear flag register 2
address_offset : 0x10444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_E : Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. This event bit contributes to ftdf_ce[4].
bits : 0 - 0 (1 bit)
access : read-write
Clear flag register 2
address_offset : 0x10448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_M : Tx meta data per entry: Mask bit for event tx_flag_clear_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Transmit priority register 2
address_offset : 0x10450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PRIORITY : Tx meta data per entry: Priority of packet
bits : 0 - 3 (4 bit)
access : read-write
ISWAKEUP : Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame.
bits : 4 - 8 (5 bit)
access : read-write
PTI_TX : This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data.
bits : 8 - 19 (12 bit)
access : read-write
Transmit packet ready for transmission register 3
address_offset : 0x10460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_STAT : Tx meta data per entry: if set to '1', the packet is ready for transmission
bits : 0 - 0 (1 bit)
access : read-only
Clear flag register 3
address_offset : 0x10464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_E : Tx meta data per entry: if set to '1' the LMAC hardware has cleared the tx_flag_stat status. This event bit contributes to ftdf_ce[4].
bits : 0 - 0 (1 bit)
access : read-write
Clear flag register 3
address_offset : 0x10468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR_M : Tx meta data per entry: Mask bit for event tx_flag_clear_e The mask bit is masking when cleared to '0' (default value) and will enable the contribution to the interrupt when set to '1'.
bits : 0 - 0 (1 bit)
access : read-write
Transmit priority register 3
address_offset : 0x10470 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_PRIORITY : Tx meta data per entry: Priority of packet
bits : 0 - 3 (4 bit)
access : read-write
ISWAKEUP : Tx meta data per entry: A basic wake-up frame can be generated by the UMAC in the Tx buffer. The meta data control bit IsWakeUp must be set to indicate that this is a Wake-up frame.
bits : 4 - 8 (5 bit)
access : read-write
PTI_TX : This register has 4 entries, belonging to the entry of the Tx frame to send, to be used during transmitting frames and the CMSA-CA phase before (when requested). In TSCH mode this register shall be used during the time slot in which frames can be transmitted and consequently an Enhanced ACK can be received. Since pti_tx belongs to a certain frame to be transmitted, pti_tx can be considered as extra Tx meta data.
bits : 8 - 19 (12 bit)
access : read-write
One shot register to set flag
address_offset : 0x10480 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_SET : Tx meta data per entry: if set to '1', the tx_flag_stat will be set to '1'.
bits : 0 - 3 (4 bit)
access : write-only
One shot register to clear flag
address_offset : 0x10484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FLAG_CLEAR : Tx meta data per entry: if set to '1', the tx_flag_stat will be cleared to '0'.
bits : 0 - 3 (4 bit)
access : write-only
Wakeup timer vcontrol register
address_offset : 0x11000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUPINTTHR : Threshold for wake-up interrupt. When WakeUpEnable is set to '1' and the Wake-up (event) counter matches this value, the interrupt WAKEUP_IRQ is set to '1' for the duration of one LP_CLK period.
bits : 0 - 24 (25 bit)
access : read-write
WAKEUPENABLE : If set to '1', the WakeUpIntThr is enabled to generate an WAKEUP_IRQ interrupt.
bits : 29 - 58 (30 bit)
access : read-write
WAKEUP_MODE : The Control register WakeUp_mode controls the behavior of the Event counter: 0d = off, 1d = free running (default), 2d = one shot with auto clear, 3d = configurable period (timer mode).
bits : 30 - 61 (32 bit)
access : read-write
address_offset : 0x12000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXP_SA_L : Lowest part of the 64 bits long source address or SA entry 1 resp. SA entry 0 in case of short source address.
bits : 0 - 31 (32 bit)
access : read-write
address_offset : 0x12004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXP_SA_H : Highest part of the 64 bits long source address or SA entry 3 resp. SA entry 2 in case of short source address.
bits : 0 - 31 (32 bit)
access : read-write
address_offset : 0x12008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VALID_SA : Indication which SA entry is valid (if set). In case of 4 short SA Valid bit 3 belongs to SA entry 3 etc. In case of a long SA Valid bit 0 is the valid indication.
bits : 0 - 3 (4 bit)
access : read-write
SHORT_LONGNOT : A '1' indicates that Exp_SA contains four short SA's, a '0' indicates one long SA.
bits : 4 - 8 (5 bit)
access : read-write
Address transmit fifo 3
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep!
bits : 0 - 31 (32 bit)
access : read-write
Transmit metadata register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME_LENGTH : Tx meta data per entry: Frame length (in bytes)
bits : 0 - 6 (7 bit)
access : read-write
PHYATTR_DEM_PTI : DEM packet information.
bits : 7 - 17 (11 bit)
access : read-write
PHYATTR_CN : Channel Number.
bits : 11 - 25 (15 bit)
access : read-write
PHYATTR_CALCAP : CalCap value.
bits : 15 - 33 (19 bit)
access : read-write
PHYATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 19 - 40 (22 bit)
access : read-write
PHYATTR_HSI : HighSide injection.
bits : 22 - 44 (23 bit)
access : read-write
FRAMETYPE : Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.).
bits : 23 - 48 (26 bit)
access : read-write
CSMACA_ENA : Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet.
bits : 26 - 52 (27 bit)
access : read-write
ACKREQUEST : Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet.
bits : 28 - 56 (29 bit)
access : read-write
CRC16_ENA : Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16
bits : 30 - 60 (31 bit)
access : read-write
Transmit metadata register 0
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACSN : Tx meta data per entry: Sequence Number of this packet.
bits : 0 - 7 (8 bit)
access : read-write
Transmit metadata register 1
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME_LENGTH : Tx meta data per entry: Frame length (in bytes)
bits : 0 - 6 (7 bit)
access : read-write
PHYATTR_DEM_PTI : DEM packet information.
bits : 7 - 17 (11 bit)
access : read-write
PHYATTR_CN : Channel Number.
bits : 11 - 25 (15 bit)
access : read-write
PHYATTR_CALCAP : CalCap value.
bits : 15 - 33 (19 bit)
access : read-write
PHYATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 19 - 40 (22 bit)
access : read-write
PHYATTR_HSI : HighSide injection.
bits : 22 - 44 (23 bit)
access : read-write
FRAMETYPE : Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.).
bits : 23 - 48 (26 bit)
access : read-write
CSMACA_ENA : Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet.
bits : 26 - 52 (27 bit)
access : read-write
ACKREQUEST : Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet.
bits : 28 - 56 (29 bit)
access : read-write
CRC16_ENA : Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16
bits : 30 - 60 (31 bit)
access : read-write
Transmit metadata register 1
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACSN : Tx meta data per entry: Sequence Number of this packet.
bits : 0 - 7 (8 bit)
access : read-write
Transmit metadata register 2
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME_LENGTH : Tx meta data per entry: Frame length (in bytes)
bits : 0 - 6 (7 bit)
access : read-write
PHYATTR_DEM_PTI : DEM packet information.
bits : 7 - 17 (11 bit)
access : read-write
PHYATTR_CN : Channel Number.
bits : 11 - 25 (15 bit)
access : read-write
PHYATTR_CALCAP : CalCap value.
bits : 15 - 33 (19 bit)
access : read-write
PHYATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 19 - 40 (22 bit)
access : read-write
PHYATTR_HSI : HighSide injection.
bits : 22 - 44 (23 bit)
access : read-write
FRAMETYPE : Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.).
bits : 23 - 48 (26 bit)
access : read-write
CSMACA_ENA : Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet.
bits : 26 - 52 (27 bit)
access : read-write
ACKREQUEST : Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet.
bits : 28 - 56 (29 bit)
access : read-write
CRC16_ENA : Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16
bits : 30 - 60 (31 bit)
access : read-write
Transmit metadata register 2
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACSN : Tx meta data per entry: Sequence Number of this packet.
bits : 0 - 7 (8 bit)
access : read-write
Transmit metadata register 3
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME_LENGTH : Tx meta data per entry: Frame length (in bytes)
bits : 0 - 6 (7 bit)
access : read-write
PHYATTR_DEM_PTI : DEM packet information.
bits : 7 - 17 (11 bit)
access : read-write
PHYATTR_CN : Channel Number.
bits : 11 - 25 (15 bit)
access : read-write
PHYATTR_CALCAP : CalCap value.
bits : 15 - 33 (19 bit)
access : read-write
PHYATTR_RF_GPIO_PINS : Slot-basis signals mapped on GPIO via PPA.
bits : 19 - 40 (22 bit)
access : read-write
PHYATTR_HSI : HighSide injection.
bits : 22 - 44 (23 bit)
access : read-write
FRAMETYPE : Tx meta data per entry: the frame type of the data to be transmitted (Data/Cmd/Ack/wakeup frame/etc.).
bits : 23 - 48 (26 bit)
access : read-write
CSMACA_ENA : Tx meta data per entry: '1' indicates that a CSMA-CA is required for the transmission of this packet.
bits : 26 - 52 (27 bit)
access : read-write
ACKREQUEST : Tx meta data per entry: '1' indicates that an acknowledge is expected from the recipient of this packet.
bits : 28 - 56 (29 bit)
access : read-write
CRC16_ENA : Tx meta data per entry: Indicates whether CRC16 insertion must be enabled or not. 0 : No hardware inserted CRC16 1 : Hardware inserts CRC16
bits : 30 - 60 (31 bit)
access : read-write
Transmit metadata register 3
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MACSN : Tx meta data per entry: Sequence Number of this packet.
bits : 0 - 7 (8 bit)
access : read-write
Transmit status register 0
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXTIMESTAMP : Tx return status per entry: Transmit Timestamp The Timestamp of the transmitted packet.
bits : 0 - 31 (32 bit)
access : read-only
Transmit status register 0
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKFAIL : Tx return status per entry: Acknowledgement status 0 : SUCCESS 1 : FAIL
bits : 0 - 0 (1 bit)
access : read-only
CSMACAFAIL : Tx return status per entry: CSMA-CA status 0 : SUCCESS 1 : FAIL
bits : 1 - 2 (2 bit)
access : read-only
CSMACANRRETRIES : Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted
bits : 2 - 6 (5 bit)
access : read-only
Transmit status register 1
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXTIMESTAMP : Tx return status per entry: Transmit Timestamp The Timestamp of the transmitted packet.
bits : 0 - 31 (32 bit)
access : read-only
Transmit status register 1
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKFAIL : Tx return status per entry: Acknowledgement status 0 : SUCCESS 1 : FAIL
bits : 0 - 0 (1 bit)
access : read-only
CSMACAFAIL : Tx return status per entry: CSMA-CA status 0 : SUCCESS 1 : FAIL
bits : 1 - 2 (2 bit)
access : read-only
CSMACANRRETRIES : Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted
bits : 2 - 6 (5 bit)
access : read-only
Transmit status register 2
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXTIMESTAMP : Tx return status per entry: Transmit Timestamp The Timestamp of the transmitted packet.
bits : 0 - 31 (32 bit)
access : read-only
Transmit status register 2
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKFAIL : Tx return status per entry: Acknowledgement status 0 : SUCCESS 1 : FAIL
bits : 0 - 0 (1 bit)
access : read-only
CSMACAFAIL : Tx return status per entry: CSMA-CA status 0 : SUCCESS 1 : FAIL
bits : 1 - 2 (2 bit)
access : read-only
CSMACANRRETRIES : Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted
bits : 2 - 6 (5 bit)
access : read-only
Transmit status register 3
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXTIMESTAMP : Tx return status per entry: Transmit Timestamp The Timestamp of the transmitted packet.
bits : 0 - 31 (32 bit)
access : read-only
Transmit status register 3
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ACKFAIL : Tx return status per entry: Acknowledgement status 0 : SUCCESS 1 : FAIL
bits : 0 - 0 (1 bit)
access : read-only
CSMACAFAIL : Tx return status per entry: CSMA-CA status 0 : SUCCESS 1 : FAIL
bits : 1 - 2 (2 bit)
access : read-only
CSMACANRRETRIES : Tx return status per entry: Number of CSMA-CA retries before this frame has been transmitted
bits : 2 - 6 (5 bit)
access : read-only
Receive metadata register 0
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 0
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 1
address_offset : 0x290 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 1
address_offset : 0x294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 2
address_offset : 0x2A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 2
address_offset : 0x2A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 3
address_offset : 0x2B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 3
address_offset : 0x2B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 4
address_offset : 0x2C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 4
address_offset : 0x2C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 5
address_offset : 0x2D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 5
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 6
address_offset : 0x2E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 6
address_offset : 0x2E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Receive metadata register 7
address_offset : 0x2F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_TIMESTAMP : Rx meta data per entry: Timestamp taken when frame was received
bits : 0 - 31 (32 bit)
access : read-only
Receive metadata register 7
address_offset : 0x2F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRC16_ERROR : Rx meta data per entry: if set, a CRC error has occurred in this frame, applicable for transparent mode only
bits : 0 - 0 (1 bit)
access : read-only
RES_FRM_TYPE_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame type, applicable when frame is not discarded
bits : 2 - 4 (3 bit)
access : read-only
RES_FRM_VERSION_ERROR : Rx meta data per entry: if set to '1' this frame is a not supported frame version, applicable when frame is not discarded.
bits : 3 - 6 (4 bit)
access : read-only
DPANID_ERROR : Rx meta data per entry: if set to '1', a destination PAN ID error has occurred, applicable when frame is not discarded
bits : 4 - 8 (5 bit)
access : read-only
DADDR_ERROR : Rx meta data per entry: if set to '1', a destination Address error has occurred, applicable when frame is not discarded
bits : 5 - 10 (6 bit)
access : read-only
SPANID_ERROR : Rx meta data per entry: if set to '1', a PAN ID error has occurred, applicable when frame is not discarded
bits : 6 - 12 (7 bit)
access : read-only
ISPANID_COORD_ERROR : Rx meta data per entry: if set to '1', the received frame is not for PAN coordinator, applicable when frame is not discarded
bits : 7 - 14 (8 bit)
access : read-only
QUALITY_INDICATOR : Rx meta data per entry: the Link Quality Indication value during reception of this frame. # $software_scratch@retention_ram # TX ram not used by hardware, can be used by software as scratch ram with retention.
bits : 8 - 23 (16 bit)
access : read-only
Address transmit fifo 1
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX_FIFO : Transmit fifo buffer, contains 32 addresses per entry (32b x 32a = 128B). There are 4 entries supported. Note that, despite the name, this fifo is NOT retained when the LMAC is put into deep-sleep!
bits : 0 - 31 (32 bit)
access : read-write
Address receive fifo 0
address_offset : 0x8000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 1
address_offset : 0x8080 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 2
address_offset : 0x8100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 3
address_offset : 0x8180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 4
address_offset : 0x8200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 5
address_offset : 0x8280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 6
address_offset : 0x8300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
Address transmit fifo 7
address_offset : 0x8380 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX_FIFO : Receive fifo ram, contains 32 addresses per entry (32b x 32a = 128B). There are 8 entries supported.
bits : 0 - 31 (32 bit)
access : read-write
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