\n
address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection :
TRNG control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNG_ENABLE : 0: Disable the TRNG 1: Enable the TRNG this signal is ignored when the FIFO is full
bits : 0 - 0 (1 bit)
access : read-write
TRNG_MODE : 0: select the TRNG with asynchronous free running oscillators (default) 1: select the pseudo-random generator with synchronous oscillators (for simulation purpose only)
bits : 1 - 2 (2 bit)
access : read-write
TRNG FIFO level register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNG_FIFOLVL : Number of 32 bit words of random data in the FIFO (max 31) until the FIFO is full. When it is 0 and TRNG_FIFOFULL is 1, it means the FIFO is full.
bits : 0 - 4 (5 bit)
access : read-only
TRNG_FIFOFULL : 1:FIFO full indication. This bit is cleared if the FIFO is read.
bits : 5 - 10 (6 bit)
access : read-only
TRNG Version register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TRNG_SVN : SVN revision number
bits : 0 - 15 (16 bit)
access : read-only
TRNG_MIN : Minor version number
bits : 16 - 39 (24 bit)
access : read-only
TRNG_MAJ : Major version number
bits : 24 - 55 (32 bit)
access : read-only
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