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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

CLK_REF_SEL_REG

CLK_REF_CNT_REG

CLK_REF_VAL_REG


CLK_REF_SEL_REG

Select clock for oscillator calibration
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_SEL_REG CLK_REF_SEL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REF_CLK_SEL REF_CAL_START EXT_CNT_EN_SEL CAL_CLK_SEL

REF_CLK_SEL : Select clock input for calibration: 0x0 : RC32K 0x1 : RC32M 0x2 : XTAL32K 0x3 : RCX 0x4 : RCOSC
bits : 0 - 2 (3 bit)
access : read-write

REF_CAL_START : Writing a '1' starts a calibration. This bit is cleared when calibration is finished, and CLK_REF_VAL is ready.
bits : 3 - 6 (4 bit)
access : read-write

EXT_CNT_EN_SEL : 0 : Enable XTAL_CNT counter by the REF_CLK selected by REF_CLK_SEL. 1 : Enable XTAL_CNT counter from an external input.
bits : 4 - 8 (5 bit)
access : read-write

CAL_CLK_SEL : Select reference clock input to be used in calibration: 0x0 : DIVN clock 0x1 : RC32K 0x2 : RC32M 0x3 : XTAL32K 0x4 : RCOSC 0x5, 0x6, 0x7: Reserved
bits : 5 - 12 (8 bit)
access : read-write


CLK_REF_CNT_REG

Count value for oscillator calibration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_CNT_REG CLK_REF_CNT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REF_CNT_VAL

REF_CNT_VAL : Indicates the calibration time, with a decrement counter to 1.
bits : 0 - 15 (16 bit)
access : read-write


CLK_REF_VAL_REG

DIVN reference cycles, lower 16 bits
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_REF_VAL_REG CLK_REF_VAL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_CNT_VAL

XTAL_CNT_VAL : Returns the number of DIVN clock cycles counted during the calibration time, defined with REF_CNT_VAL
bits : 0 - 31 (32 bit)
access : read-only



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