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address_offset : 0x0 Bytes (0x0)
size : 0x54 byte (0x0)
mem_usage : registers
protection :
Cache control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_FLUSH : Writing a '1' into this bit, flushes the contents of the tag memories which invalidates the content of the cache memory. The read of this bit is always '0'. Note: The flushing of the cache TAG memory takes 0x100 or 0x200 HCLK cycles for a Cache Data RAM size of 8 KB resp. 16 KB.
bits : 0 - 0 (1 bit)
access : write-only
CACHE_RES1 : Reserved. Always keep 0.
bits : 1 - 2 (2 bit)
access : read-write
Cache control register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_LEN : Length of QSPI FLASH cacheable memory. N*64 KByte. N = 0 to 512 (max. of 32 Mbyte). Setting CACHE_LEN=0 disables the cache. Note 1: The max. relevant CACHE_LEN setting depends on the chosen Flash region (program) size. Note 2: The first block (CACHE_LEN=1) includes the memory space specified by CACHE_FLASH_REG[FLASH_REGION_OFFSET].
bits : 0 - 8 (9 bit)
access : read-write
CACHE_WEN : 0: Cache Data and TAG memory read only. 1: Cache Data and TAG memory read/write. The TAG and Data memory are only updated by the cache controller. There is no HW protection to prevent unauthorized access by the ARM. Note: When accessing the memory mapped Cache Data and TAG memory (for debugging purposes) only 32 bits access is allowed to the Cache Data memory and only 16 bits access is allowed to the Cache TAG memory.
bits : 9 - 18 (10 bit)
access : read-write
CACHE_CGEN : 0: Cache controller clock gating is not enabled. 1: Cache controller clock gating is enabled (enabling power saving). Note: This bit must be set to '0' (default) when setting the CACHE_FLUSH bit while executing from other than QSPI FLASH cached, e.g. from Booter or SYSRAM.
bits : 10 - 20 (11 bit)
access : read-write
Cache MRM (Miss Rate Monitor) HITS register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_HITS : Contains the amount of cache hits.
bits : 0 - 31 (32 bit)
access : read-write
Cache MRM (Miss Rate Monitor) MISSES register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_MISSES : Contains the amount of cache misses.
bits : 0 - 31 (32 bit)
access : read-write
Cache MRM (Miss Rate Monitor) CONTROL register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_START : 0: Freeze the misses/hits counters and reset the time interval counter to the programmed value in CACHE_MRM_TINT_REG. 1: Enables the counters. Note: In case CACHE_MRM_CTRL_REG[MRM_START] is set to '1' and CACHE_MRM_TINT_REG (!=0) is used for the MRM interrupt generation, the time interval counter counts down (on a fixed reference clock of 16 MHz) until it's '0'. At that time CACHE_MRM_CTRL_REG[MRM_START] will be reset automatically to '0' by the MRM hardware and the MRM interrupt will be generated.
bits : 0 - 0 (1 bit)
access : read-write
MRM_IRQ_MASK : 0: Disables interrupt generation. 1: Enables interrupt generation. Note: The Cache MRM generates a pulse-sensitive interrupt towards the ARM processor,
bits : 1 - 2 (2 bit)
access : read-write
MRM_IRQ_TINT_STATUS : 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the time interval counter reached the end (time interval != 0).
bits : 2 - 4 (3 bit)
access : read-write
MRM_IRQ_MISSES_THRES_STATUS : 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the number of cache misses reached the programmed threshold (threshold != 0).
bits : 3 - 6 (4 bit)
access : read-write
MRM_IRQ_HITS_THRES_STATUS : 0: No interrupt is generated. 1: Interrupt (pulse-sensitive) is generated because the number of cache hits reached the programmed threshold (threshold != 0).
bits : 4 - 8 (5 bit)
access : read-write
Cache MRM (Miss Rate Monitor) TIME INTERVAL register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_TINT : Defines the time interval for the monitoring in 32 MHz clock cycles. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_TINT_STATUS]. Note: When MRM_TINT=0 (unrealistic value), no interrupt will be generated.
bits : 0 - 18 (19 bit)
access : read-write
Cache MRM (Miss Rate Monitor) THRESHOLD register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_MISSES_THRES : Defines the misses threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_MISSES_THRES_STATUS]. Note: When MRM_MISSES_THRES=0 (unrealistic value), no interrupt will be generated.
bits : 0 - 31 (32 bit)
access : read-write
Cache MRM (Miss Rate Monitor) HITS THRESHOLD register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MRM_HITS_THRES : Defines the hits threshold to trigger the interrupt generation. See also the description of CACHE_MRM_CTRL_REG[MRM_IRQ_HITS_THRES_STATUS]. Note: When MRM_HITS_THRES=0 (unrealistic value), no interrupt will be generated.
bits : 0 - 31 (32 bit)
access : read-write
Cache line size configuration register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_LINE : Cache line size: 0: 8 bytes, 1: 16 bytes, 2: 32 bytes, 3: reserved. Note: Flush the cache just after the dynamic (run-time) reconfiguration of the cache with an 8 bytes cache line size: write the value 01 into the cache control register CACHE_CTRL1_REG just after the write of the value 00 into the cache line size configuration register CACHE_LNSIZECFG_REG.
bits : 0 - 1 (2 bit)
access : read-write
Cache Flash program size and base address register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FLASH_REGION_SIZE : Flash region size. Default value is '6' (0.5 MBytes). 0 = 32 MBytes, 1 = 16 MBytes, 2 = 8 MBytes, 3 = 4 MBytes, 4 = 2 MBytes, 5 = 1 MBytes, 6 = 0.5 MBytes, 7 = 0.25 MBytes. These register bits are retained. Note 1: The updated value takes effect only after a software reset. Note 2: See for the max. region (program) size the memory map.
bits : 0 - 2 (3 bit)
access : read-write
FLASH_REGION_OFFSET : Flash region offset address (in words). This value is added to the Flash (CPU) address bits [13:2]. These register bits are retained. Note 1: The updated value takes effect only after a software reset.
bits : 4 - 19 (16 bit)
access : read-write
FLASH_REGION_BASE : These bits corresponds with the Flash region base address bits [31:16]. Default value is '0x1600'. The Flash region base address bits [31:25] are fixed to '0x16' and bits [17:16] are fixed to '0x0'. These register bits are retained. Note 1: The updated value takes effect only after a software reset. Note 2 The Flash region base address setting depends on the chosen Flash region size.
bits : 16 - 47 (32 bit)
access : read-write
SWD HW reset control register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWD_HW_RESET_REQ : 0: default. 1: HW reset request (from the debugger tool). The register is automatically reset with a HW_RESET. This bit can only be accessed by the debugger software and not by the application.
bits : 0 - 0 (1 bit)
access : write-only
Cache associativity configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CACHE_ASSOC : Cache associativity: 0: 1-way (direct mapped) 1: 2-way 2: 4-way 3: reserved.
bits : 0 - 1 (2 bit)
access : read-write
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