CTRL_REG

CURRENT_PARAM_REG

TEMPSET_PARAM_REG

PRE_CHARGE_TIMER_REG

CC_CHARGE_TIMER_REG

CV_CHARGE_TIMER_REG

TOTAL_CHARGE_TIMER_REG

JEITA_V_CHARGE_REG

JEITA_V_PRECHARGE_REG

JEITA_V_REPLENISH_REG

JEITA_V_OVP_REG

JEITA_CURRENT_REG

VBAT_COMP_TIMER_REG

VOVP_COMP_TIMER_REG

TDIE_COMP_TIMER_REG

TBAT_MON_TIMER_REG

TBAT_COMP_TIMER_REG

THOT_COMP_TIMER_REG

PWR_UP_TIMER_REG

STATE_IRQ_MASK_REG

ERROR_IRQ_MASK_REG

STATE_IRQ_STATUS_REG

ERROR_IRQ_STATUS_REG

STATE_IRQ_CLR_REG

ERROR_IRQ_CLR_REG

STATUS_REG

VOLTAGE_PARAM_REG

CHARGER_ENABLE : 0 = Charger's analogue circuitry is powered-down 1 = Charger's analogue circuitry is being powered-up and will be available after a certain settling time (in ms). As soon as this bit-field is set, the Charger's FSM waits for this settling time, before proceeding into DISABLED state, where it checks the Vbat level, as well as the Die temperature and the Battery temperature states. This is mandatory, before the actual charging begins, so before the FSM moves to PRE_CHARGE state. It is finally noted that the settling time is configurable via CHARGER_PWR_UP_TIMER_REG, counting with the 1Khz clock. Note: The Charger clocks must have been enabled first, by setting the CLK_SYS_REG[CLK_CHG_EN] bit-field to '1', in order to let the FSM proceed.
bits : 0 - 0 (1 bit)
access : read-write

CHARGE_START : 0 = Charger's FSM is disabled, FSM stays at DISABLED state 1 = Charger's FSM is enabled, so FSM's state can move from DISABLED to the actual charge states, starting from PRE_CHARGE .
bits : 1 - 2 (2 bit)
access : read-write

CHARGER_BYPASS : 0 = Charger's FSM is active and running, notifying SW upon switching between its states 1 = Charger's FSM is bypassed, so its state stays to BYPASS , so SW should take over the monitoring of the battery voltage and control of the charger.
bits : 2 - 4 (3 bit)
access : read-write

CHARGER_RESUME : 0 = Charger's FSM is not enable to resume from a charge timeout error or a Vbat OVP (Over-Voltage Protection) error. Consequently, FSM stays in ERROR state. 1 = Charger's FSM will resume from a charge timeout or from an OVP error, thus its state will move from ERROR to DISABLED state, so that the charge cycle starts-over. It is noted that in the case of a Vbat OVP error, the FSM will leave ERROR state, as soon as the Vbat comparator for the OVP level shows that Vbat is again OK (so lower than the OVP setting).
bits : 3 - 6 (4 bit)
access : read-write

TDIE_PROT_ENABLE : 0 = Die temperature protection is disabled, thus charging will not be disabled by the Charger's FSM in case of a Die temperature error. 1 = Die temperature protection is enabled, thus the Charger's FSM will move to TDIE_PROT state, disabling charging at the same time. It is noted that the Die temperature error event will be logged in the respective status bit of CHARGER_IRQ_ERROR_STATUS_REG and an IRQ will be generated, if and only if the corresponding mask bit of CHARGER_IRQ_MASK_REG is set.
bits : 4 - 8 (5 bit)
access : read-write

TDIE_ERROR_RESUME : 0 = FSM will not resume from a Die temperature error. Consequently, its state will be staying to TDIE_PROT , for as long as this bit-field is kept low, regardless of the status of the die tempeture comparator. Also, disabling the specific bit-field will reset the Die temperature error debounce counter, when the Charger's FSM is in TDIE_PROT state (so when a Die temperature error has been already detected) and the specific counter will remain frozen to 0 until the TDIE_ERROR_RESUME bit-field is set (see also the TDIE_ERROR_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG). 1 = FSM will resume from a Die temperature error, as soon as the respective analogue compator confirms that die temperature is again below the maximum allowed level. It is noted that the maximum Die temperature level is programmable via the CHARGER_TEMPSET_PARAM_REG register's respective bit-field (T_DIE_MAX).
bits : 5 - 10 (6 bit)
access : read-write

TBAT_PROT_ENABLE : 0 = Battery temperature protection disabled 1 = Battery temperature protection enabled. Charging will be stopped in case Battery temperature reaches Hot zone. It will also be disabled when reaching Cold zone, provided that CHARGER_CTRL_REG.NTC_LOW_DISABLE is not set. This is handled by the Charger's FSM, which moves directly to the respective error state (TBAT_PROT), also generating an Error IRQ if the respective IRQ mask bit is set (see also CHARGER_ERROR_IRQ_MASK_REG).
bits : 6 - 12 (7 bit)
access : read-write

NTC_LOW_DISABLE : 0 = Charging is disabled when the battery temperature is found to have reached the COLD region. Therefore, the Charger's FSM moves directly to TBAT_PROT error and generates an IRQ to notify the system accordingly, in case the respective IRQ mask bit of CHARGER_ERROR_IRQ_MASK_REG is set. Also, CHARGER_ERROR_IRQ_STATUS_REG. TBAT_ERROR_IRQ field is updated accordingly. 1 = Charging is allowed to continue, even when the battery temperature pack reaches the COLD region. Consequently, the FSM continues charging and no battery temperature error event is generated.
bits : 7 - 14 (8 bit)
access : read-write

CHARGE_TIMERS_HALT_ENABLE : 0 = Charge timeout timers continue running when charging is disabled because of a Die or of a Battery temperature error. 1 = Charge timeout timers are halted in case of a Die or of a Battery temperature error. In that case, the global charge timer is stopped as soon as the Charger's FSM moves to TDIE_PROT or TBAT_PROT state. Also, either the Pre-Charge, the CC_CHARGE or the CV_CHARGE timer is also stopped, depending on the charging state of the FSM when the Die/Battery temperature error has been detected.
bits : 9 - 18 (10 bit)
access : read-write

TBAT_MONITOR_MODE : Battery temperature pack monitoring modes, according to the following encoding: 00 = Battery temperature state checked and updated once, as soon as the charger is powered-up and settled. 01 = Battery temperature state checked periodically, depeding on TBAT_MON_TIMER_REG.TBAT_MON_INTERVAL and provided that Charger has been powered-up and charger's FSM is enabled. 10 = Battery temperature state checked periodically depending on TBAT_MON_TIMER_REG.TBAT_MON_INTERVAL, provided that Charger is powered-up and regardless if the Charger's FSM is enabled or not. Hence, this mode can be effective regardless of the state of CHARGE_START bit-field of CHARGER_CTRL_REG. 11 = When selected, it freezes the Battery temperature monitor FSM, as soon as the latter reaches the CHECK_IDLE state (see also CHARGER_STATUS_REG.CHARGER_JEITA_STATE bit-field's description for the states of this FSM). In this mode, the monitoring of Battery temperature is possible only by checking the status of TBAT_HOT_COMP_OUT and MAIN_TBAT_COMP_OUT bit-fields of CHARGER_STATUS_REG, thus by letting SW take over monitoring. This setting may be used in conjunction with Bypass mode (by setting CHARGER_BYPASS of CHARGER_CTRL_REG), so that both charging and battery temperature status monitoring are controlled by SW.
bits : 10 - 21 (12 bit)
access : read-write

JEITA_SUPPORT_DISABLED : 0 = Charger's JEITA FSM monitoring the battery temperature checks also if battery temperature is in the Warm or Cool zones. In that case, it updates accordingly all the Charger's voltage levels (Charge, Pre-Charge, Replenish and OVP) programmed in CHARGER_VOLTAGE_PARAM_REG, as well as the charge and pre-charge current settings of CHARGER_CURRENT_PARAM_REG, depending on the temperature zone determined by the analogue circuitry of the Charger (see also the JEITA registers of the Charger's register file for the Voltage/Current levels in Warm and Cool temperature zones). 1 = Charger's JEITA FSM monitoring the battery temperature checks only if battery temperature is either in the Hot or Cold zones. In that case, it notifies the main Charger FSM to stop charging automatically, when in Hot zone. The same will happen also for the case of Cold, unless the NTC_LOW_DISABLE bit-field of CHARGER_CTRL_REG is set. Note : It is not recommended to have the specific bit-field kept to '0' (and thus the JEITA support enabled), if at the same time the bit-field TBAT_PROT_ENABLE of the same register is also '0'. Thus, JEITA support should be coupled with the Battery's temperature protection.
bits : 12 - 24 (13 bit)
access : read-write

CHARGE_LOOP_HOLD : When set, this bit-field disables charging, provided that the Charger's FSM has switched to the BYPASSED state. This is possible only by setting the CHARGER_BYPASS bit-field of this register. Thus, as soon as the Charger's FSM is bypassed, the respective signal driven by the FSM is overruled by this bit-field, making the analogue part of the Charger controllable also in this mode. If the Charger's FSM is not bypassed, this bit-field is don't care.
bits : 13 - 26 (14 bit)
access : read-write

PRE_CHARGE_MODE : When set, this bit-field enables a signal of the same name with the bit-field, driven from the Charger's digital part towards the analogue circuitry, in order to determine the current in Pre-Charge mode. If the Charger's FSM is active and operational, the specific bit-field is don't care. Hence, it is considered only when the Charger's FSM has reached the BYPASSED state (thus, in Bypass mode). With the Charger's FSM being bypassed, SW should take over control and set the specific bit-field, in order to deliver the Pre-Charge instead of the normal Charge current to the Charger's analogue circuitry, during the Pre-Charge phase. Note: See also the description of CHARGER_CURRENT_PARAM_REG register for the Pre-Charge and normal Charge current levels supported.
bits : 14 - 28 (15 bit)
access : read-write

REPLENISH_MODE : When this bit-field is set and the Charger's FSM is in the BYPASSED state (thus, in Bypass mode), the internal multiplexer inside the digital part of the charger selects the Replenish, instead of the Pre-charge setting to be driven to the main Vbat comparator of the Charger's analogue circuitry. By this way, SW can read the respective analogue comparator's output in CHARGER_STATUS_REG (bit-field MAIN_VBAT_COMP_OUT), after the battery's volrtage has reached the End-of-Charge level, and determine if the battery voltage has dropped below the Replenish level, re-starting the battery charging accordingly. Note: When the Charger's FSM is active and operational, this bit-field is don't care and the FSM determines which level (Pre-charge or Replenish) will be selected and driven to the analogue, depending on the current state. It is also noted that the supported Pre-charge and Replenish levels can be viewed in the respective bit-fields defined in CHARGER_VOLTAGE_PARAM_REG register.
bits : 15 - 30 (16 bit)
access : read-write

EOC_INTERVAL_CHECK_THRES : This bit-field determines the periodic interval of checking the End-of-Charge signal, when the Charger's FSM is either in CC_CHARGE or in CV_CHARGE state. To implement this, a dedicated timer has been used, counting from zero up to the value programmed into this bit-field (see also EOC_INTERVAL_CHECK_TIMER field's description). As soon as this timer reaches the programmed value, the End-of-Charge signal is sampled and depending on its status (high or low), another counter, keeping the number of consecutive End-of-Charge events, is increased or not. See also the description of the EOC_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG, for this counter. Note: The specific bit-field should always be programmed to a non-zero value.
bits : 16 - 37 (22 bit)
access : read-write

EOC_INTERVAL_CHECK_TIMER : The specific bit-field determines the current state of the timer used to periodically check the End-of-Charge signal, as soon as the Charger's FSM is either in CC_CHARGE or CV_CHARGE state. Thus, as soon as the Charger's FSM enters the CC_CHARGE state: - The timer starts increasing when a positive edge detection on End-of-Charge signal occurs. - It keeps increasing until reaching the programmed EOC_INTERVAL_CHECK_THRES value, if and only if there is no detection of a negative edge on End-of-Charge signal. If this happens, the timer resets and starts over with a new End-of-Charge positive edge. - The timer also resets after having reached its programmed threshold or when the Charger's FSM next state is END_OF_CHARGE. This happens only after having found End-of-Charge signal asserted for 4 consecutive checks and provided that the specific signal has not de-asserted during the timer's interval. Note: It must be noted that out of these two states, the specific timer is kept to zero. It is also noted that this timer runs at the 1Mhz clock of the Charger's block and its value always ranges from 0 to the EOC_INTERVAL_CHECK_THRES value set in the respective bit-field of CHARGER_CTRL_REG.
bits : 22 - 49 (28 bit)
access : read-only

I_CHARGE : This bit-field determines the charge current range, in mA. The range is from 5mA to 560mA, according to the following encoding: 0 : 5 mA 1 : 10 mA 2 : 15 mA 3 : 20 mA 4 : 25 mA 5 : 30 mA 6 : 35 mA 7 : 40 mA 8 : 45 mA 9 : 50 mA 10 : 55 mA 11 : 60 mA 12 : 65 mA 13 : 70 mA 14 : 75 mA 15 : 80 mA 16 : 90 mA 17 : 100 mA 18 : 110 mA 19 : 120 mA 20 : 130 mA 21 : 140 mA 22 : 150 mA 23 : 160 mA 24 : 170 mA 25 : 180 mA 26 : 190 mA 27 : 200 mA 28 : 210 mA 29 : 220 mA 30 : 230 mA 31 : 240 mA 32 : 260 mA 33 : 280 mA 34 : 300 mA 35 : 320 mA 36 : 340 mA 37 : 360 mA 38 : 380 mA 39 : 400 mA 40 : 420 mA 41 : 440 mA 42 : 460 mA 43 : 480 mA 44 : 500 mA 45 : 520 mA 46 : 540 mA 47 : 560 mA 48 : 560 mA 49 : 560 mA 50 : 560 mA 51 : 560 mA 52 : 560 mA 53 : 560 mA 54 : 560 mA 55 : 560 mA 56 : 560 mA 57 : 560 mA 58 : 560 mA 59 : 560 mA 60 : 560 mA 61 : 560 mA 62 : 560 mA 63 : 560 mA Note: It has to be noted that the specific values correspond to the normal battery temperature zone. However, the specific register field may be updated by the JEITA FSM (which checks the battery temperature either once or periodically), in order to adapt the Charge current to the new battery temperature zone (see also CHARGER_CTRL_REG.TBAT_MONITOR_MODE field as well). This is valid also for the Pre-Charge current field of this register and provided that JEITA support is enabled in CHARGER_CTRL_REG. Consequently, in that case the register return the Charge current settings that abide to the JEITA requirements for the battery (either COOL, WARM or NORMAL).
bits : 0 - 5 (6 bit)
access : read-write

I_PRECHARGE : This bit-field determines the Pre-Charge current, in mA, ranging from 0.5 to 56mA, according to the following encoding: 0 : 0.5 mA 1 : 1 mA 2 : 1.5mA 3 : 2 mA 4 : 2.5mA 5 : 3 mA 6 : 3.5mA 7 : 4 mA 8 : 4.5mA 9 : 5 mA 10 : 5.5mA 11 : 6 mA 12 : 6.5mA 13 : 7 mA 14 : 7.5mA 15 : 8 mA 16 : 9 mA 17 : 10 mA 18 : 11 mA 19 : 12 mA 20 : 13 mA 21 : 14 mA 22 : 15 mA 23 : 16 mA 24 : 17 mA 25 : 18 mA 26 : 19 mA 27 : 20 mA 28 : 21 mA 29 : 22 mA 30 : 23 mA 31 : 24 mA 32 : 26 mA 33 : 28 mA 34 : 30 mA 35 : 32 mA 36 : 34 mA 37 : 36 mA 38 : 38 mA 39 : 40 mA 40 : 42 mA 41 : 44 mA 42 : 46 mA 43 : 48 mA 44 : 50 mA 45 : 52 mA 46 : 54 mA 47 : 56 mA 48 : 56 mA 49 : 56 mA 50 : 56 mA 51 : 56 mA 52 : 56 mA 53 : 56 mA 54 : 56 mA 55 : 56 mA 56 : 56 mA 57 : 56 mA 58 : 56 mA 59 : 56 mA 60 : 56 mA 61 : 56 mA 62 : 56 mA 63 : 56 mA
bits : 6 - 17 (12 bit)
access : read-write

I_END_OF_CHARGE : End-of-Charge current setting, ranging from 4 percent( 000 ) to 14.5 percent ( 111 ) of the charge current set, with a step size of 1.5 percent, as follows (when I_EOC_DOUBLE_RANGE = 0): 000 : 4 percent 001 : 5.5 percent 010 : 7 percent 011 : 8.5 percent 100 : 10 percent 101 : 11.5 percent 110 : 13 percent 111 : 14.5 percent When I_EOC_DOUBLE_RANGE = 1, The range is: 000 : 8 percent 001 : 11.5 percent 010 : 15 percent 011 : 18.5 percent 100 : 22 percent 101 : 25.5 percent 110 : 29 percent 111 : 32.5 percent
bits : 12 - 26 (15 bit)
access : read-write

I_EOC_DOUBLE_RANGE : When set, the specific bit-field enables the doubling of the ( percent) range of End-of-Charge current setting. Consequently, the default lower and upper limits of 6 percent of I_CHARGE (value 0x0 of I_END_OF_CHARGE bit-field) and 20 percent (value 0x7 of the same bit-field) are increased to 12 percent and 40 percent respectively, as soon as the I_EOC_DOUBLE_RANGE field is set.
bits : 15 - 30 (16 bit)
access : read-write

TBAT_COLD : This bit-field determines the battery temperature below which the charge current is zero, defining the Cold temperature zone. It ranges from minus 10C to 53C, according to the following encoding: 0 : -10 C 1 : -9 C 2 : -8 C 3 : -7 C 4 : -6 C 5 : -5 C 6 : -4 C 7 : -3 C 8 : -2 C 9 : -1 C 10 : 0 C 11 : 1 C 12 : 2 C 13 : 3 C 14 : 4 C 15 : 5 C 16 : 6 C 17 : 7 C 18 : 8 C 19 : 9 C 20 : 10 C 21 : 11 C 22 : 12 C 23 : 13 C 24 : 14 C 25 : 15 C 26 : 16 C 27 : 17 C 28 : 18 C 29 : 19 C 30 : 20 C 31 : 21 C 32 : 22 C 33 : 23 C 34 : 24 C 35 : 25 C 36 : 26 C 37 : 27 C 38 : 28 C 39 : 29 C 40 : 30 C 41 : 31 C 42 : 32 C 43 : 33 C 44 : 34 C 45 : 35 C 46 : 36 C 47 : 37 C 48 : 38 C 49 : 39 C 50 : 40 C 51 : 41 C 52 : 42 C 53 : 43 C 54 : 44 C 55 : 45 C 56 : 46 C 57 : 47 C 58 : 48 C 59 : 49 C 60 : 50 C 61 : 51 C 62 : 52 C 63 : 53 C
bits : 0 - 5 (6 bit)
access : read-write

TBAT_COOL : This bit-field determines the battery temperature below which the charge current is reduced, defining the Cool temperature zone. It ranges from minus 10C to 53C and the range is the same with the one defined in TBAT_COLD bit-field.
bits : 6 - 17 (12 bit)
access : read-write

TBAT_WARM : This bit-field determines the battery temperature above which the charge current is reduced, defining the Warm temperature zone. It ranges from minus 10C to 53C. The range is the same with the one defined in detail in TBAT_COLD bit-field.
bits : 12 - 29 (18 bit)
access : read-write

TBAT_HOT : This bit-field determines the battery temperature above which the charge current is zero, defining the Hot battery temperature zone. It ranges from minus 10C to 53C. The range is the same with the one defined in detail in TBAT_COLD bit-field.
bits : 18 - 41 (24 bit)
access : read-write

TDIE_MAX : This bit-field determines the maximum Die temperature level limit, ranging from 0C to 130C, according to the following encoding: 000: 0 C (mainly for test purposes) 001: 50 C 010: 80 C 011: 90 C 100: 100 C 101: 110 C 110: 120 C 111: 130 C
bits : 24 - 50 (27 bit)
access : read-write

MAX_PRE_CHARGE_TIME : This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the Pre-Charge stage. If this is exceeded, a Pre-Charge time-out error will be captured by the Charger's control unit and its FSM will move to the respective state (ERROR). In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 14 (15 bit)
access : read-write

PRE_CHARGE_TIMER : Returns the current value of the Pre-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the CC-Charge and the CV-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_PRE_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state.
bits : 16 - 46 (31 bit)
access : read-only

MAX_CC_CHARGE_TIME : This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CC (Constant Current) charging stage. If this is exceeded, a CC charge time-out error will be captured by the Charger's control unit and its FSM will move to the ERROR state. In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 14 (15 bit)
access : read-write

CC_CHARGE_TIMER : Returns the current value of the CC-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the Pre-Charge and the CV-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_CC_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state.
bits : 16 - 46 (31 bit)
access : read-only

MAX_CV_CHARGE_TIME : This bit-field determines the maximum time (measured in ticks of the Charger's 1Hz clock) allowed for the CV (Constant Voltage) charging stage. If this is exceeded, a CV charge time-out error will be captured by the Charger's control unit and its FSM will move to the ERROR state. In order to exit this state and re-start charging, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 14 (15 bit)
access : read-write

CV_CHARGE_TIMER : Returns the current value of the CV-Charge timeout counter, running at a 1Hz clock. The range of the specific timer is identical to the one of the Pre-Charge and the CC-Charge timers, so it may count up to 6 hours, ranging from 0 to MAX_CV_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state.
bits : 16 - 46 (31 bit)
access : read-only

MAX_TOTAL_CHARGE_TIME : This bit-field determines the maximum overall charging time allowed (measured in ticks of the 1Hz clock). If this is exceeded, a total charge time-out error will be captured by the Charger's controller and its FSM will move to the ERROR state. An IRQ will be also generated if the respective IRQ mask bit of CHARGER_ERROR_IRQ_MASK_REG is already set. In order to to exit this state, the CHARGER_RESUME bit-field of CHARGER_CTRL_REG must be set, to enable the Charger's FSM switch from ERROR to DISABLED state and start-over. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 15 (16 bit)
access : read-write

TOTAL_CHARGE_TIMER : Returns the current value of the overall charge timeout counter, running at a 1Hz clock. This timer has been set to 16 bits, so that it can count up to 10.5 hours, and ranges from 0 to MAX_TOTAL_CHARGE_TIME. It is reset to 0 when the Charger's FSM is either in DISABLED or in END_OF_CHARGE state.
bits : 16 - 47 (32 bit)
access : read-only

V_CHARGE_TCOOL : Charge voltage setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register.
bits : 0 - 5 (6 bit)
access : read-write

V_CHARGE_TWARM : Charge voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register.
bits : 6 - 17 (12 bit)
access : read-write

V_PRECHARGE_TCOOL : Pre-Charge current setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register.
bits : 0 - 5 (6 bit)
access : read-write

V_PRECHARGE_TWARM : Pre-Charge voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG register.
bits : 6 - 17 (12 bit)
access : read-write

V_REPLENISH_TCOOL : Replenish voltage setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG.
bits : 0 - 5 (6 bit)
access : read-write

V_REPLENISH_TWARM : Replenish voltage setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG.
bits : 6 - 17 (12 bit)
access : read-write

V_OVP_TCOOL : VBAT Over-voltage Protection (OVP) setting for the Cool battery temperature zone.Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG.
bits : 0 - 5 (6 bit)
access : read-write

V_OVP_TWARM : VBAT Over-voltage Protection (OVP) setting for the Warm battery temperature zone.Regarding the range of values of this bit-field, see also the description of V_CHARGE field of CHARGER_VOLTAGE_PARAM_REG.
bits : 6 - 17 (12 bit)
access : read-write

I_CHARGE_TCOOL : Charge current setting for the COOL battery temperature level. Regarding the range of values of this bit-field, see also the description of I_CHARGE field of CHARGER_CURRENT_PARAM_REG register.
bits : 0 - 5 (6 bit)
access : read-write

I_CHARGE_TWARM : Charge current setting for the Warm battery temperature pack zone. Regarding the range of values of this bit-field, see also the description of I_CHARGE field of CHARGER_CURRENT_PARAM_REG register.
bits : 6 - 17 (12 bit)
access : read-write

I_PRECHARGE_TCOOL : Pre-Charge current setting for the Cool battery temperature zone. Regarding the range of values of this bit-field, see also the description of I_PRECHARGE field of CHARGER_CURRENT_PARAM_REG register.
bits : 12 - 29 (18 bit)
access : read-write

I_PRECHARGE_TWARM : Pre-Charge current setting for the Warm battery temperature zone. Regarding the range of values of this bit-field, see also the description of I_PRECHARGE field of CHARGER_CURRENT_PARAM_REG register.
bits : 18 - 41 (24 bit)
access : read-write

VBAT_COMP_SETTLING : Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Pre-Charge and Replenish levels. The settings (voltage levels) of the comparator are controlled by the digital block of the Charger and they are driven based on the state of the main FSM (PRE_CHARGE, END_OF_CHARGE).
bits : 0 - 9 (10 bit)
access : read-write

VBAT_COMP_TIMER : Returns the current value of the timer used to determine when the output of the Vbat comparator (checking Vbat vs Pre_Charge and Replenish levels) must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from the value set in VBAT_COMP_SETTLING), the comparator's output is latched by the Charger's digital block and used by the FSM. Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over. In this mode, the specific comparator checks the level of Vbat against the Pre-Charge level. Hence, SW can periodically sample the status of this comparator by reading the MAIN_VBAT_COMP_OUT bit-field of CHARGER_STATUS_REG, to determine if Vbat has exceeded the Pre-Charge level or not.
bits : 16 - 41 (26 bit)
access : read-only

VBAT_OVP_COMP_SETTLING : Settling time threshold (in us) for the Vbat comparator checking Vbat vs the programmed Over-Voltage level.
bits : 0 - 9 (10 bit)
access : read-write

OVP_INTERVAL_CHECK_THRES : This bit-field determines the periodic interval of checking the dedicated Vbat OVP comparator's output, when the Charger's FSM is in any of the charging states (PRE/CC/CV_CHARGE). The implementation is based on a dedicated timer, counting from zero up to the value programmed into this bit-field (see also OVP_INTERVAL_CHECK_TIMER field's description) and only when the FSM is in any of the three charging states. Out of these states, the timer is kept frozen to zero. As soon as this timer reaches the programmed threshold, the Vbat OVP comparator's output is sampled and depending on its level, (high or low), another counter, keeping the number of consecutive OVP events, is increased or not. The programmed threshold value should always be non-zero. Note: See also the OVP_DEBOUNCE_CNT bit-field of CHARGER_STATUS_REG, for the consecutive OVP events counter.
bits : 10 - 25 (16 bit)
access : read-write

VBAT_OVP_COMP_TIMER : Returns the current value of the timer used to determine when the Vbat Over-Voltage protection (OVP) comparator's output must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from VBAT_OVP_COMP_SETTLING), the comparator's output is latched by the Charger's digital block and used by the main FSM. Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over, sampling the status of the VBAT_OVP_COMP_OUT bit-field of CHARGER_STATUS_REG to determine if the Vbat has exceeded the OVP limit.
bits : 16 - 41 (26 bit)
access : read-only

OVP_INTERVAL_CHECK_TIMER : The specific bit-field determines the current state of the timer used to periodically check the output of the Over-Voltage Protection comparator's output signal, as soon as the Charger's FSM reaches any of the charging states (PRE/CC/CV_CHARGE). When this happens, the timer starts ticking with the 1Mhz clock, ranging from 0 up to the programmed interval threshold (see also OVP_INTERVAL_CHECK_THRES field). As soon as this timer reaches the programmed threshold value, the Vbat OVP comparator's output is evaluated, increasing or not the counter keeping the consecutive OVP events. It is noted that out of the charging states, the specific timer is kept frozen to zero, not counting. Note : See also the OVP_OCCURRENCES_CNT bit-field of CHARGER_STATUS_REG for the consecutive OVP events counter.
bits : 26 - 57 (32 bit)
access : read-only

TDIE_COMP_SETTLING : Settling time threshold (in us) for the Die temperature comparator.
bits : 0 - 9 (10 bit)
access : read-write

TDIE_COMP_TIMER : Returns the current value of the timer used to determine when the Die temperature comparator's output must be sampled by the digital. As soon as the timer expires (down-counting to 0, starting from TDIE_COMP_SETTLING) the comparator's output is latched by the Charger's digital block and used by the main FSM. After expiring, the timer starts-over again, down-counting, to enable the continuous monitoring of Die temperature by the digital. Note: When the Charger's FSM is in BYPASSED state, this timer is kept to zero and the SW takes over, sampling the status of the TDIE_PROT_COMP_OUT bit-field of CHARGER_STATUS_REG to determine if the Die temperature limit has been exceeded.
bits : 16 - 41 (26 bit)
access : read-only

TBAT_MON_INTERVAL : Timing interval (in ms) for the Battery temperature monitoring. This interval determines how often the JEITA FSM will be checking and potentially refreshing the Battery temperature status, by selecting accordingly the proper level (Hot, Cold, Warm, Cool or Normal), based on the feedback of the two battery temperature comparators being present in the Charger's analogue circuitry (one for the Hot level and one for Cold, Cool and Warm, to support JEITA). Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 9 (10 bit)
access : read-write

TBAT_MON_TIMER : This is the battery temperature monitoring timer, counting with the Charger's 1KHz clock. If the battery monitor mode is accordingly set in the TBAT_MONITOR_MODE bit-field of CHARGER_CTRL_REG (so either to 0x1 or 0x2), this timer is initially loaded with the value set in TBAT_MON_INTERVAL bit-field in the subsequent 1khz cycles starts down-counting to 0. As soon as the specific timer expires,the JEITA FSM starts-over again, to refresh the battery temperature status.
bits : 16 - 41 (26 bit)
access : read-only

TBAT_COMP_SETTLING : Settling time (specified in us) for the main battery temperature comparator, checking for the COOL , COLD and WARM levels. The charger's digital block uses a dedicated timer to sample the specific comparator's output. The comparator's output is latched as soon as the timer expires, reaching 0. Then, the timer is reloaded with the settling time value and starts-over, down-counting to 0. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 9 (10 bit)
access : read-write

TBAT_COMP_TIMER : Returns the main battery temperature comparator's timer, used for the latching of the comparator's output. The output of the comparator is used by the JEITA FSM, to determine the current battery temperature pack's status.
bits : 16 - 41 (26 bit)
access : read-only

THOT_COMP_SETTLING : Charger's battery temperature comparator settling time (specified in us), specifically for the Hot temperature zone. The charger's digital block uses a dedicated timer to sample the specific comparator's output. The comparator's output is latched as soon as the timer expires, reaching 0. Then, the timer is reloaded with the settling time value and starts-over again Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 9 (10 bit)
access : read-write

THOT_COMP_TIMER : Returns the battery temperature comparator's timer dedicated for the Hot level.
bits : 16 - 41 (26 bit)
access : read-only

CHARGER_PWR_UP_SETTLING : This bit-field determines the charger's power-up (settling) time, required for the analogue circuitry of the charger. As soon as the charger is powered-on by setting the CHARGER_ENABLE bit-field of CHARGER_CTRL_REG, the charger's FSM loads a dedicated timer with this value and waits for this timer to expire, before proceeding to the next states. Note: The specific bit-field should be always set to a non-zero value.
bits : 0 - 9 (10 bit)
access : read-write

CHARGER_PWR_UP_TIMER : Returns the current value of the charger's power-up timer, running with the 1Khz clock. Note: The specific timer is reset to the value programmed to CHARGER_PWR_UP_SETTLING bit-field, when the Charger's analogue circuitry has been enabled, after being disabled initially. By setting CHARGER_CTRL_REG[CHARGER_ENABLE] to '0', the analogue part is disabled and in order to be properly enable, SW has to wait for 1ms (one 1Khz clock period) time. The latter is is needed to ensure that the power-up timer's control signals in the Charger's digital part will be cleared when the analogue part is again enabled, so that a proper new start-up of the Charger's FSM is possible.
bits : 16 - 41 (26 bit)
access : read-only

DISABLED_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from DISABLED to PRE_CHARGE state.
bits : 0 - 0 (1 bit)
access : read-write

PRECHARGE_TO_CC_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from PRE_CHARGE to CC_CHARGE state..
bits : 1 - 2 (2 bit)
access : read-write

CC_TO_CV_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to CV_CHARGE state.
bits : 2 - 4 (3 bit)
access : read-write

CC_TO_EOC_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to END_OF_CHARGE state.
bits : 3 - 6 (4 bit)
access : read-write

CV_TO_EOC_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to END_OF_CHARGE state.
bits : 4 - 8 (5 bit)
access : read-write

EOC_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the Charger's State IRQ generation as soon as the Charger's FSM switches from END_OF_CHARGE again to PRE_CHARGE state. This happens when the Vbat voltage level is detected to be below the Replenish level set.
bits : 5 - 10 (6 bit)
access : read-write

TDIE_PROT_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Die temperature protection state (TDIE_PROT) to PRE_CHARGE, resuming charging.
bits : 6 - 12 (7 bit)
access : read-write

TBAT_PROT_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the Charger's state IRQ generation as soon as the Charger's FSM switches from the Battery temperature protection state (TBAT_PROT) to PRE_CHARGE, resuming charging.
bits : 7 - 14 (8 bit)
access : read-write

TBAT_STATUS_UPDATE_IRQ_EN : When set, this bit-field enables the generation of the Charger's state IRQ as soon as the battery temperature status is refreched by the Charger's Battery temperature monitor (JEITA) FSM. As soon as the specific FSM checks the current battery temperature level, it notifies the main Charger FSM that it has run and that the Battery temperature pack state is checked (and potentially refreshed with a new status).
bits : 8 - 16 (9 bit)
access : read-write

CV_TO_CC_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to CC_CHARGE state.
bits : 9 - 18 (10 bit)
access : read-write

CC_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CC_CHARGE to PRE_CHARGE state.
bits : 10 - 20 (11 bit)
access : read-write

CV_TO_PRECHARGE_IRQ_EN : When set, this bit-field enables the IRQ generation as soon as the Charger's FSM switches from CV_CHARGE to PRE_CHARGE state.
bits : 11 - 22 (12 bit)
access : read-write

PRECHARGE_TIMEOUT_IRQ_EN : When set, it enables the Pre-Charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer expires, reaching 0.
bits : 0 - 0 (1 bit)
access : read-write

CC_CHARGE_TIMEOUT_IRQ_EN : When set, it enables the CC charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer, expires, reaching 0.
bits : 1 - 2 (2 bit)
access : read-write

CV_CHARGE_TIMEOUT_IRQ_EN : When set, it enables the CV charge timeout IRQs. The IRQ is generated as soon as the Charger's state timer expires, reaching 0 when the FSM is in the CV_CHARGE state.
bits : 2 - 4 (3 bit)
access : read-write

TOTAL_CHARGE_TIMEOUT_IRQ_EN : When set, it enables the total charge timeout IRQs. The IRQ is generated as soon as the Charger's global charge timer expires, reaching 0.
bits : 3 - 6 (4 bit)
access : read-write

VBAT_OVP_ERROR_IRQ_EN : When set, it enables the generation of VBAT_OVP IRQs. The IRQ is generated as soon as the dedicated Vbat comparator shows that Vbat has exceeded the OVP level and the Charger's FSM has switched to the respective error state ( ERROR ).
bits : 4 - 8 (5 bit)
access : read-write

TDIE_ERROR_IRQ_EN : When set, it enables the generation of Die temperature error IRQs. The IRQ is generated as soon as a Die temperature error is captured, so as soon as the Charger's FSM moves to the TDIE_PROT state. For this to happen, the Die temperature comparator should indicate that Die temperature has exceeded the limit defined in CHARGER_TEMPSET_PARAM_REG.TDIE_MAX.
bits : 5 - 10 (6 bit)
access : read-write

TBAT_ERROR_IRQ_EN : When set, it enables the generation of Battery temperature IRQs.The IRQ is generated as soon as the JEITA FSM detects that the battery temperature is either in the Hot or in the Cold temperature region, by sampling the respective comparators' output.
bits : 6 - 12 (7 bit)
access : read-write

DISABLED_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from DISABLED to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from DISABLED to PRE_CHARGE state
bits : 0 - 0 (1 bit)
access : read-only

PRECHARGE_TO_CC_IRQ : 0 = No transition of the Charger's FSM from PRE_CHARGE to CC_CHARGE state has been captured 1 = Charger's FSM has switched from PRE_CHARGE to CC_CHARGE state
bits : 1 - 2 (2 bit)
access : read-only

CC_TO_CV_IRQ : 0 = No transition of the Charger's FSM from CC_CHARGE to CV_CHARGE state has been captured 1 = Charger's FSM has switched from CC_CHARGE to CV_CHARGE state
bits : 2 - 4 (3 bit)
access : read-only

CC_TO_EOC_IRQ : 0 = No transition of the Charger's FSM from CC_CHARGE to END_OF_CHARGE state has been captured 1 = Charger's FSM has switched from CC_CHARGE to END_OF_CHARGE state
bits : 3 - 6 (4 bit)
access : read-only

CV_TO_EOC_IRQ : 0 = No transition of the Charger's FSM from CV_CHARGE to END_OF_CHARGE state has been captured 1 = Charger's FSM has switched from CV_CHARGE to END_OF_CHARGE state
bits : 4 - 8 (5 bit)
access : read-only

EOC_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from END_OF_CHARGE to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from END_OF_CHARGE to PRE_CHARGE state
bits : 5 - 10 (6 bit)
access : read-only

TDIE_PROT_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from TDIE_PROT to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from TDIE_PROT to PRE_CHARGE state, resuming charging after having recovered from a Die temperature error.
bits : 6 - 12 (7 bit)
access : read-only

TBAT_PROT_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from TBAT_PROT to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from TBAT_PROT to PRE_CHARGE state, resuming charging after having recovered from a battery temperature error.
bits : 7 - 14 (8 bit)
access : read-only

TBAT_STATUS_UPDATE_IRQ : 0 = No battery temperature status update event has been captured 1 = Battery temperature pack's status has been checked and refreshed by the Charger's Battery temperature monitor FSM. Thus, the new status of the battery temperature should be checked by SW.
bits : 8 - 16 (9 bit)
access : read-only

CV_TO_CC_IRQ : 0 = No transition of the Charger's FSM from CV_CHARGE to CC_CHARGE state has been captured 1 = Charger's FSM has switched from CV_CHARGE to CC_CHARGE state
bits : 9 - 18 (10 bit)
access : read-only

CC_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from CC_CHARGE to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from CC_CHARGE to PRE_CHARGE state
bits : 10 - 20 (11 bit)
access : read-only

CV_TO_PRECHARGE_IRQ : 0 = No transition of the Charger's FSM from CV_CHARGE to PRE_CHARGE state has been captured 1 = Charger's FSM has switched from CV_CHARGE to PRE_CHARGE state
bits : 11 - 22 (12 bit)
access : read-only

PRECHARGE_TIMEOUT_IRQ : 0 = State charge time counter has not yet reached the maximum Pre-charge time (set in CHARGER_PRECHARGE_TIME_REG) 1 = Total charge time counter has reached the maximum Pre-charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured.
bits : 0 - 0 (1 bit)
access : read-only

CC_CHARGE_TIMEOUT_IRQ : 0 = State charge time counter has not yet reached the maximum CC charge time (set in CHARGER_CC_CHARGE_TIME_REG) 1 = Total charge time counter has reached the maximum CC charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured.
bits : 1 - 2 (2 bit)
access : read-only

CV_CHARGE_TIMEOUT_IRQ : 0 = State charge time counter has not yet reached the maximum CV charge time (set in CHARGER_CV_CHARGE_TIME_REG) 1 = Total charge time counter has reached the maximum CV charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured.
bits : 2 - 4 (3 bit)
access : read-only

TOTAL_CHARGE_TIMEOUT_IRQ : 0 = Total charge time counter has not yet reached the maximum charge time (set in CHARGER_TOTAL_CHARGE_TIME_REG) 1 = Total charge time counter has reached the maximum charge time programmed. The Charger's FSM will move to the respective error state (ERROR) and charging will be automatically stopped, as soon as the specific event is captured.
bits : 3 - 6 (4 bit)
access : read-only

VBAT_OVP_ERROR_IRQ : 0 = Vbat has not exceeded the Over-Voltage Protection (OVP) level, so charging may continue 1 = Vbat has exceeded the Over-Voltage level, thus an OVP error event has been captured. The Charger's FSM switches to the respective error state (ERROR) as soon as the OVP event is captured by the digital part of the Charger and charging will be automatically stopped.
bits : 4 - 8 (5 bit)
access : read-only

TDIE_ERROR_IRQ : 0 = No Die temperature error IRQ events have been captured, so charging may continue 1 = A Die temperature error IRQ event is captured, declaring that the Charger's FSM has switched to the respective error state (TDIE_PROT) and charging will be automatically stopped. Note : The status bit is updated automatically when a Die temperature error is detected, thus when the die temperature is found to have exceeded the programmed level, regardless of the stae of the respective IRQ mask bit.
bits : 5 - 10 (6 bit)
access : read-only

TBAT_ERROR_IRQ : 0 = No Battery temperature error IRQ event is captured, so charging may continue 1 = A Battery temperature error IRQ event has been captured, declaring that the Charger's FSM has moved to the respective error state (TBAT_PROT). Note : The status bit is updated automatically when the Battery temperature is detected to be either in the HOT or in the COLD zone, regardless of the state of the respective IRQ mask bit.
bits : 6 - 12 (7 bit)
access : read-only

DISABLED_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 0 - 0 (1 bit)
access : write-only

PRECHARGE_TO_CC_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 1 - 2 (2 bit)
access : write-only

CC_TO_CV_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 2 - 4 (3 bit)
access : write-only

CC_TO_EOC_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 3 - 6 (4 bit)
access : write-only

CV_TO_EOC_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 4 - 8 (5 bit)
access : write-only

EOC_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 5 - 10 (6 bit)
access : write-only

TDIE_PROT_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 6 - 12 (7 bit)
access : write-only

TBAT_PROT_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 7 - 14 (8 bit)
access : write-only

TBAT_STATUS_UPDATE_IRQ_CLR : Writing a 1 will reset the Battery temperature status update IRQ status bit writing a 0 will have no effect
bits : 8 - 16 (9 bit)
access : write-only

CV_TO_CC_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 9 - 18 (10 bit)
access : write-only

CC_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 10 - 20 (11 bit)
access : write-only

CV_TO_PRECHARGE_IRQ_CLR : Writing a 1 will reset the respective Charger's State IRQ status bit writing a 0 will have no effect
bits : 11 - 22 (12 bit)
access : write-only

PRECHARGE_TIMEOUT_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 0 - 0 (1 bit)
access : write-only

CC_CHARGE_TIMEOUT_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 1 - 2 (2 bit)
access : write-only

CV_CHARGE_TIMEOUT_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 2 - 4 (3 bit)
access : write-only

TOTAL_CHARGE_TIMEOUT_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 3 - 6 (4 bit)
access : write-only

VBAT_OVP_ERROR_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 4 - 8 (5 bit)
access : write-only

TDIE_ERROR_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 5 - 10 (6 bit)
access : write-only

TBAT_ERROR_IRQ_CLR : Writing a 1 will reset the respective Charger's Error IRQ status bit writing a 0 will have no effect
bits : 6 - 12 (7 bit)
access : write-only

CHARGER_IS_POWERED_UP : 0 = Charger is either off or it is being powered-on but the analogue ciruitry is not yet settled. The charger's main FSM is either in POWER_UP or INIT states. 1 = Charger is powered-up, so its analogue ciruitry should now be settled. The Charger's FSM has left both power-up states (POWER_UP, INIT), so charging can start.
bits : 0 - 0 (1 bit)
access : read-only

CHARGER_CC_MODE : 0 = Charger's Current loop not in regulation (or Charger is off) 1 = Charger's Constant Current (CC) mode active, current loop in regulation
bits : 1 - 2 (2 bit)
access : read-only

CHARGER_CV_MODE : 0 = Charger's voltage loop not in regulation (or Charger is off) 1 = Charger's Constant Voltage (CV) mode active, voltage loop in regulation
bits : 2 - 4 (3 bit)
access : read-only

END_OF_CHARGE : 0 = Actual charge current is above the current level programmed in I_END_OF_CHARGE field of CHARGER_CURRENT_PARAM_REG (or charger is off) 1 = Actual charge current is below the current level programmed in I_END_OF_CHARGE bit-field of CHARGER_CURRENT_PARAM_REG.
bits : 3 - 6 (4 bit)
access : read-only

MAIN_VBAT_COMP_OUT : This bit-field reflects the status of the main Vbat comparator residing in the analogue circuitry of the Charger. This comparator is used to check Vbat against either the Pre-Charge or the Replenish voltage level, depending on what is driven by the Charger's digital block. Thus, when the FSM is active, the comparator gets as reference the Replenish setting as soon as the FSM has reached the END_OF_CHARGE state. Otherwise,the Pre-Charge voltage setting is driven, including the Bypass mode. According to the above, the encoding is as follows for the case the comparator compares Vbat against the Pre-Charge level: 0 = Vbat has not exceeded the set Pre-Charge voltage level. 1 = Vbat has reached or exceeded the set Pre-Charge voltage level. For the case the comparator compares agains the Replenish level (when the FSM has reached the END_OF_CHARGE state, so when the charging has been completed), the encoding is as follows: 0 = Vbat has dropped below the set Replenish level, so charging will re-start and the FSM will move to the PRE_CHARGE state. 1 = Vbat is still greater or equal to the set Replenish level, thus charging remains in hold and the FSM in END_OF_CHARGE state.
bits : 4 - 8 (5 bit)
access : read-only

VBAT_OVP_COMP_OUT : 0 = Vbat has not exceeded the Over-Voltage Protection (OVP) voltage limit, according to the respective analogue comparator's output. 1 = Vbat is found to have exceeded the OVP voltage setting, thus charging should be disabled. The OVP voltage settings are defined in CHARGER_VOLTAGE_PARAM_REG.V_OVP (for the Normal battery temperature zone), as well as in CHARGER_JEITA_V_OVP_REG (for Cool and Warm temperature zones, to comply with JEITA).
bits : 5 - 10 (6 bit)
access : read-only

TDIE_COMP_OUT : 0 = Die temperature is found to be below the programmed level, set in CHARGER_TEMPSET_PARAM_REG.TDIE_SET level (normal operation) 1 = Die temperature is found to be above the set level. Charging will be disabled if Die temperature protection is enabled and the Die temperature is found to be above the set level four consecutive times (see also TDIE_ERROR_DEBOUNCE_CNT bit-field). In that case, the Charger's FSM will also move the respective error state (TDIE_PROT) and an IRQ may be generated, if the respective mask bit of CHARGER_ERROR_IRQ_MASK_REG is set.
bits : 6 - 12 (7 bit)
access : read-only

TBAT_HOT_COMP_OUT : Returns the status of the battery temperature comparator dedicated to the Hot temperature zone. 0 = Battery temperature pack is found to be below the Hot zone 1 = Battery temperature pack is found to be in the non-allowed Hot temperature zone. Thus, charging will be disabled, provided that battery temperature protection is enabled.
bits : 7 - 14 (8 bit)
access : read-only

MAIN_TBAT_COMP_OUT : Returns the status of the main battery temperature comparator. This comparator by default checks if the battery temperature is in the Cold zone. However, if JEITA support is enabled and battery temperature is found to not be in either the Hot or the Cold zone, the same comparator is used to check for the Warm and Cool zones, as JEITA suggests. The specific bit-field is suggested to be used in bypass mode and when the JEITA support is disabled (so when the battery temperature is checked agains the Hot and the Cold zones). In that case, the comparator checks the battery temperature agains the Cold level and its status can be as follows: 0 = Battery temperature pack is found to be below the Cold level, so in the non-allowed Cold temperature zone. Thus, charging will be disabled, provided that the NTC_LOW_DISABLE bit-field of CHARGER_CTRL_REG is not set. 1 = Battery temperature pack is found to be above the non-allowed Cold temperature zone. Thus, charging will be continued, provided that battery temperature will not be in the Hot zone as well. When the Charger's main FSM is active and JEITA is enabled, the Charger's digital block takes over and controls the respective comparator's output.
bits : 8 - 16 (9 bit)
access : read-only

TBAT_STATUS : Battery pack temperature status, according to the following ( 1-Hot -like) encoding: 00001 : Battery temperature in COLD zone (default) 00010 : Battery temperature in COOL zone 00100 : Battery temperature in NORMAL zone (above COOL and below WARM zones) 01000 : Battery temperature in WARM zone 10000 : Battery temperature in HOT zone It is noted that, according to the JEITA standard (supported if the JEITA_SUPPORT_ENABLED bit-field of CHARGER_CTRL_REG is not set) , if the battery pack temperature is in the HOT zone, charging will always be stopped. The same will happen also for the case of the COLD zone, unless the NTC_LOW_DISABLE bit-field of CHARGER_CTRL_REG is set. In that case, charging will continue. It is finally noted that only the aforementioned values are available for this bit-field, since it is 1-Hot encoding based. Not more than 1 bit can be high at the same time, since this would mean that battery temperature is at two different temperature zones concurrently.
bits : 9 - 22 (14 bit)
access : read-only

CHARGER_STATE : Indicating the state of the Charger's main FSM, based on the following encoding: 0x0 = POWER_UP (Charger's power-up not yet set) 0x1 = INIT (Charger is being power-up, FSM waiting for the analogue to settle) 0x2 = DISABLED (Charger powered-up but charging not yet started) 0x3 = PRE_CHARGE (Pre-Charge state) 0x4 = CC_CHARGE (Constant Current state) 0x5 = CV_CHARGE (Constant Voltage state) 0x6 = END_OF_CHARGE (End-of-Charge state) 0x7 = TDIE_PROT (Die temperature protection state, visited when Die temperature limit is exceeded) 0x8 = TBAT_PROT (Battery temperature protection state, visited when Battery temperature is either COLD or HOT) 0x9 = BYPASSED (Bypassed state, visited only when the FSM is bypassed and SW takes over control) 0xA = ERROR (Error state, visited when a charge time-out occurs or in the case of Vbat exceeding over-voltage level)
bits : 14 - 31 (18 bit)
access : read-only

CHARGER_JEITA_STATE : Returns the state of the Charger's JEITA FSM. This FSM is used to update the state of the battery temperature pack, depending on the value programmed in CHARGER_CTRL_REG.TBAT_MONITOR_MODE bit-field. The encoding of the states is as follows: 0x0 = CHECK_IDLE 0x1 = CHECK_THOT 0x2 = CHECK_TCOLD 0x3 = CHECK_TWARM 0x4 = CHECK_TCOOL 0x5 = CHECK_TNORMAL 0x6 = UPDATE_TBAT The FSM initially is in CHECK_IDLE state and starts checking the battery's temperature by visiting the states that check for the respective temperature area (Hot, Cold, Warm, Cool, Normal), in this order. If the battery temperature is found to be in one of the aforementioned zones, it directly moves to UPDATE_TBAT state, to update the battery temperature's state and notify the main FSM of the Charger about the battery temperature status, before returning to the CHECK_IDLE state. A Charger State IRQ will also be generated upon refreshing the battery temperature status (see also the description of CHARGER_STATE_IRQ_MASK_REG register).
bits : 18 - 38 (21 bit)
access : read-only

TDIE_ERROR_DEBOUNCE_CNT : The specific bit-field returns the consecutive number of times the Die temperature is seen either above (for the case of an error) or below (for the case of recovering from an error) the set Die temperature level.This is performed by a counter, which is increased: - Each time the Die temperature comparator shows that Die temperature exceeds the set level, and while charging is active, provided that Die temperature protection is enabled. If, however, the CHARGER_CTRL_REG.TDIE_PROT_ENABLE bit-field is not set, the counter is reset and stays frozen to zero. - Each time the Die temperature comparator shows that Die temperature is again below the set level, and while the FSM is in the Die temperature protection error state (TDIE_PROT) and the TDIE_ERROR_RESUME bit-field of CHARGER_CTRL_REG is set. If the specific bit-field is not set, the debounce counter is reset to 0 and it is kept frozen until the FSM is again enabled to resume from Die temperature errors. If the Die temperature comparator of the Charger's analogue circuitry shows that temperature has exceeded the programmed level for four consecutive times and charging is active, the Charger's FSM considers this as a Die temperature error and moves to the TDIE_PROT state, resetting the timer at the same time and of course halting charging. To recover from this state and resume charging, the FSM needs to see that Die temperature is below the programmed level for four consecutive times, again, provided that the TDIE_ERROR_RESUME bit-field of CHARGER_CTRL_REG is set. As soon as this happens, the error counter is again reset and the Charger's FSM resumes, by moving to PRE_CHARGE state. Consequently, the counter's value always ranges from 0 to 4. Note: When the Charger's FSM is in BYPASSED state, then this bit-field is reset and kept frozen to zero. Consequently, the number of times Die temperature has exceeded the pre-programmed threshold should be determined by SW.
bits : 21 - 44 (24 bit)
access : read-only

EOC_EVENTS_DEBOUNCE_CNT : The specific bit-field returns the number of times the End-of-Charge signal has been consecutively found to be high. It is used to determine when the Charger's FSM will switch from CV_CHARGE to END_OF_CHARGE state, implementing a debounce mechanism on End-of-Charge signal, coming from the analogue circuitry of the Charger towards the FSM. The specific counter, running with the Charger's 1Mhz clock: - Increases after detecting that the End-of-Charge signal is high when the respective interval for the End-of-Charge check expires. This actually happens after having detected a positive edge on End-of-Charge signal, since only after that is it possible for the interval timer to start ticking. - Resets to zero when End-of-Charge is seen low when the interval timer has expired or when an End-of-Charge negative edge is seen before the timer's expiration, starting-over. - Does not count if End-of-Charge signal is seen high and either the CV_MODE signal (also driven by the analogue circutry) or the End-of-Charge signal of the previous clock cycle is seen low. - Is reset when the Charger's FSM is not in either the CC_CHARGE or the CV_CHARGE state or after having reached 100 (4). This is the threshold after which the End-of-Charge signal is considered stable by the Charger's FSM, to switch to the END_OF_CHARGE state. Thus, in practice, the specific counter (and bit-field) ranges between 0 and 4. Note: See also the EOC_INTERVAL_CHECK_TIMER/THRES bit-fields of CHARGER_CTRL_REG.
bits : 24 - 50 (27 bit)
access : read-only

OVP_EVENTS_DEBOUNCE_CNT : The specific bit-field returns the consecutive number of times Vbat has exceeded the programmed Over-Voltage Protection (OVP) level. It is used to determine when the Charger's FSM will exit any of the charging states (PRE/CC/CV_CHARGE) and will switch to the ERROR state due to an OVP error. This will happen as soon as the respective counter of OVP events reaches or exceeds a fixed number (4), similar to the approach adopted in the End-of-Charge and Die Temperature debouncing mechanisms. The specific counter increases only while the Charger's FSM is in any of the three charging,states, the Vbat OVP interval check timer has reached the threshold set and when Vbat OVP comparator's output is asserted. Note 1 : By default, as soon as the counter reaches 4, the FSM will switch to the ERROR state and the counter will reset again. Thus, in that case the specific counter ranges from 0 to 4 and vice-versa. However, if the monitoring of Vbat OVP comparator's state is less frequent than 5 (4+1) times the CHARGER_OVP_COMP_TIMER_REG[OVP_INTERVAL_CHECK_THRES] and Vbat has exceeded the OVP voltage level based on the comparator's output signal, then this counter will exceed 4 and may overflow. This will not harm, however, the detection of the OVP event, as it only increases the number of OVP event occurrences by the debounce timer, until the OVP comparator timer's settling time has expired. Thus, the Charger FSM will again switch to ERROR when the counter has reached or exceeded 4 (bit [2] of OVP_EVENTS_DEBOUNCE_CNT is set) and the OVP comparator's timer has expired. Note 2: See also the OVP_INTERVAL_CHECK_TIMER, OVP_INTERVAL_CHECK_THRES of CHARGER_OVP_COMP_TIMER_REG, for the debouncing mechanism of the Vbat OVP comparator's output.
bits : 27 - 56 (30 bit)
access : read-only

V_CHARGE : This bit-field determines the charge voltage levels supported. The supported levels are determined according to the following encoding: 0 : 2.80V 1 : 2.85V 2 : 2.90V 3 : 2.95V 4 : 3.00V 5 : 3.05V 6 : 3.10V 7 : 3.15V 8 : 3.20V 9 : 3.25V 10 : 3.30V 11 : 3.35V 12 : 3.40V 13 : 3.45V 14 : 3.50V 15 : 3.55V 16 : 3.60V 17 : 3.65V 18 : 3.70V 19 : 3.75V 20 : 3.80V 21 : 3.82V 22 : 3.84V 23 : 3.86V 24 : 3.88V 25 : 3.90V 26 : 3.92V 27 : 3.94V 28 : 3.96V 29 : 3.98V 30 : 4.00V 31 : 4.02V 32 : 4.04V 33 : 4.06V 34 : 4.08V 35 : 4.10V 36 : 4.12V 37 : 4.14V 38 : 4.16V 39 : 4.18V 40 : 4.20V 41 : 4.22V 42 : 4.24V 43 : 4.26V 44 : 4.28V 45 : 4.30V 46 : 4.32V 47 : 4.34V 48 : 4.36V 49 : 4.38V 50 : 4.40V 51 : 4.42V 52 : 4.44V 53 : 4.46V 54 : 4.48V 55 : 4.50V 56 : 4.52V 57 : 4.54V 58 : 4.56V 59 : 4.58V 60 : 4.60V 61 : 4.70V 62 : 4.80V 63 : 4.90V* It has to be noted that the specific values correspond to the normal battery temperature zone. However, the specific register field may be updated by the JEITA FSM (which checks the battery temperature either once or periodically), in order to adapt the charge voltage to the battery temperature zone (see also CHARGER_CTRL_REG.TBAT_MONITOR_MODE field as well). This is valid also for the other three fields of the current register. Consequently, in that case the register returns the Charge voltage settings that abide to the JEITA requirements for the battery (either COOL, WARM or NORMAL). Note: Option 63 (4.90V) is not supported for V_CHARGE, V_PRECHARGE and V_REPLENISH bit-fields (and respective levels). It should be used only in the V_OVP bit-field, as the (maximum) Over-voltage protection level.
bits : 0 - 5 (6 bit)
access : read-write

V_PRECHARGE : This bit-field determines the voltage level at which the battery is considered as Pre-charged and therefore the Charger's FSM should move to the CC_CHARGE state, entering the Constant Current charging phase. Regarding the supported Pre-Charge voltage levels, see also the description of V_CHARGE bit-field of this register.
bits : 6 - 17 (12 bit)
access : read-write

V_REPLENISH : This bit-field determines the absolute value (in V) of the Replenish voltage threshold. As soon as charging has been completed and the Charger's FSM has reached the END_OF_CHARGE state, the respective analogue comparator of the Charger compares VBAT with the Replenish level. If VBAT is found to have dropped below this level, charging should start-over again and in that case, the FSM moves again to the PRE_CHARGE state. Regarding the supported Replenish voltage levels, see the description of V_CHARGE bit-field.
bits : 12 - 29 (18 bit)
access : read-write

V_OVP : This bit-field determines the VBAT Over-voltage protection limit. This Over-voltage protection level is used by the Charger's analogue circuitry and specifically by a dedicated comparator, the output of which is sampled by the digital block of the Charger. As soon as VBAT is detected to have reached or exceeded this level, the Charger's FSM moves to ERROR state, interrupting charging. If the respective Error IRQ mask bit is set, an Error IRQ pulse will be also generated. Regarding the actual range of supported values for this bit-field, see the the description of V_CHARGE bit-field of this register.
bits : 18 - 41 (24 bit)
access : read-write