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address_offset : 0x0 Bytes (0x0)
size : 0x2110 byte (0x0)
mem_usage : registers
protection :
CMAC and System Control Register
address_offset : 0x2000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMAC2SYS_IRQ_STATE : The current state of the CMAC2SYS_IRQ signal.
bits : 0 - 0 (1 bit)
access : read-only
CMAC2SYS_IRQ_CLR : Writing 0 will have no effect. Writing 1 will clear the CMAC2SYS_IRQ, a process that depends on the state of CMAC and the relationship of the PCLK and CMAC clocks. Reading will return 1 as long as the clearing process is pending, otherwise it will return 0 .
bits : 1 - 2 (2 bit)
access : read-write
CMAC_RST_BS_STATE :
bits : 7 - 14 (8 bit)
access : read-only
CMAC_RST_MCPU_STATE : The state of the CMAC M0+ reset signal. Note that this reset is driven also by CLK_RADIO_REG->CMAC_SYNCH_RESET.
bits : 8 - 16 (9 bit)
access : read-only
MCPU_SLEEPING_STATE :
bits : 9 - 18 (10 bit)
access : read-only
CMAC_FW_ERROR_STATE :
bits : 10 - 20 (11 bit)
access : read-only
CMAC_BS_ERROR_STATE :
bits : 11 - 22 (12 bit)
access : read-only
CMAC_CPU_ERROR_STATE :
bits : 12 - 24 (13 bit)
access : read-only
CMAC_SYSMEMCTRL_ERROR_STATE :
bits : 13 - 26 (14 bit)
access : read-only
CMAC_WDOG_EXPIRE_STATE :
bits : 14 - 28 (15 bit)
access : read-only
CMAC_LOCKUP_STATE :
bits : 15 - 30 (16 bit)
access : read-only
CMAC_CONST_1 : Always read as 1 . Note: Creating an always non-zero register value, making easier a visual check of register when power domain is off.
bits : 31 - 62 (32 bit)
access : read-only
CMAC Watch Dog Control Register
address_offset : 0x2004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CM_WDOG_CNT : Provides access to the counter, which counts down every 10.24 msec. FW should reload the WDOG counter by writing to CM_WDOG_REG the value (CM_WDOG_CNT | CM_WDOG_WRITE_VALID), i.e. write can be done only by writing at the same time CM_WDOG_WRITE_VALID with ones. The counter will start counting immediately after the power up of the Power Domain.
bits : 0 - 12 (13 bit)
access : read-write
CM_WDOG_WRITE_VALID : In order to allow a write of any of the remaining fields, this value must be also written simultaneously with the value 3 . Reading this field will return always '0'.
bits : 17 - 35 (19 bit)
access : write-only
CM_WDOG_SYS_RST_REQ : Refer to CM_WDOG_EXPIRE.
bits : 28 - 56 (29 bit)
access : read-only
CM_WDOG_EXPIRE : This bit automatically is set to 1 as soon as CM_WDOG_CNT=0, causing CM_WDOG_CNT to start counting again from the value of 16 and also asserting CM_ERROR_REG->CM_WDOG_EXPIRE_ERR. If the SW will write CM_WDOG_EXPIRE = 0 and CM_WDOG_CNT=0, then at the next WDOG clock cycle the CM_WDOG_EXPIRE will automatically be set to to 1 . If the SW will write CM_WDOG_EXPIRE = 1 and CM_WDOG_CNT=0, then at the next WDOG clock cycle the CM_WDOG_SYS_RST_REQ will automatically be set to 1 . The CM_WDOG_SYS_RST_REQ will reset the system and will update the RESET_STAT_REG->CMAC_WDOGRESET_STAT. Refer also to CM_EXC_STAT_REG->EXC_WDOG_EARLY.
bits : 29 - 58 (30 bit)
access : read-write
SYS2CMAC_WDOG_FREEZE_DIS : Setting to '1' will mask the SYS2CMAC_WDOG_FREEZE, which is provided by SET_FREEZE_REG->FRZ_CMAC_WDOG. Setting to 1 can be done only by writing at the same time CM_WDOG_WRITE_VALID with ones. The field can be only set to '1', so it can be set during the initilization and it will not change during the reloadings. It can be reseted either via power cycling the Power Domain or via the CLK_RADIO_REG->CMAC_SYNCH_RESET.
bits : 30 - 60 (31 bit)
access : read-write
SYS2CMAC_WDOG_FREEZE : A read-only copy of SET_FREEZE_REG->FRZ_CMAC_WDOG value.
bits : 31 - 62 (32 bit)
access : read-only
Diagnostic IRQ on Word1 - Word1 Register
address_offset : 0x2100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAG1_DCF_21 : Same signal as the one in CM_DIAG_WORD1_REG. Refer to CM_DIAG_WORD1_REG for signal description.
bits : 0 - 0 (1 bit)
access : read-only
DIAG1_DCF_22 : Refer to bit 0.
bits : 1 - 2 (2 bit)
access : read-only
DIAG1_DCF_23 : Refer to bit 0.
bits : 2 - 4 (3 bit)
access : read-only
DIAG1_DCF_24 : Refer to bit 0.
bits : 3 - 6 (4 bit)
access : read-only
DIAG1_DCF_25 : Refer to bit 0.
bits : 4 - 8 (5 bit)
access : read-only
DIAG1_DCF_26 : Refer to bit 0.
bits : 5 - 10 (6 bit)
access : read-only
DIAG1_PHY_RX_EN_RFCU : Refer to bit 0.
bits : 6 - 12 (7 bit)
access : read-only
DIAG1_PHY_TX_EN_RFCU : Refer to bit 0.
bits : 7 - 14 (8 bit)
access : read-only
DIAG1_SYNC_FOUND : Refer to bit 0.
bits : 8 - 16 (9 bit)
access : read-only
DIAG1_MATCH0101 : Refer to bit 0.
bits : 9 - 18 (10 bit)
access : read-only
DIAG1_SIGNAL_DETECTED : Refer to bit 0.
bits : 10 - 20 (11 bit)
access : read-only
Diagnostic IRQ on Word1 - Edge Register
address_offset : 0x2104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAG1_DCF_21 : 0: The positive edge is selected to set the corresponding bit of CM_DIAG_IRQ1_STAT_REG. 1: The negative edge is selected.
bits : 0 - 0 (1 bit)
access : read-write
DIAG1_DCF_22 : Refer to bit 0.
bits : 1 - 2 (2 bit)
access : read-write
DIAG1_DCF_23 : Refer to bit 0.
bits : 2 - 4 (3 bit)
access : read-write
DIAG1_DCF_24 : Refer to bit 0.
bits : 3 - 6 (4 bit)
access : read-write
DIAG1_DCF_25 : Refer to bit 0.
bits : 4 - 8 (5 bit)
access : read-write
DIAG1_DCF_26 : Refer to bit 0.
bits : 5 - 10 (6 bit)
access : read-write
DIAG1_PHY_RX_EN_RFCU : Refer to bit 0.
bits : 6 - 12 (7 bit)
access : read-write
DIAG1_PHY_TX_EN_RFCU : Refer to bit 0.
bits : 7 - 14 (8 bit)
access : read-write
Diagnostic IRQ on Word1 - Status Register
address_offset : 0x2108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAG1_DCF_21 : 1: the corresponding event is pending. 0: the corresponding event is not pending. Writing a '1' will clear the corresponding bit. Writing a '0' into a bit will have no effect. Use this register to detect and acknowledge the source that triggers the DIAG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write
DIAG1_DCF_22 : Refer to bit 0.
bits : 1 - 2 (2 bit)
access : read-write
DIAG1_DCF_23 : Refer to bit 0.
bits : 2 - 4 (3 bit)
access : read-write
DIAG1_DCF_24 : Refer to bit 0.
bits : 3 - 6 (4 bit)
access : read-write
DIAG1_DCF_25 : Refer to bit 0.
bits : 4 - 8 (5 bit)
access : read-write
DIAG1_DCF_26 : Refer to bit 0.
bits : 5 - 10 (6 bit)
access : read-write
DIAG1_PHY_RX_EN_RFCU : Refer to bit 0.
bits : 6 - 12 (7 bit)
access : read-write
DIAG1_PHY_TX_EN_RFCU : Refer to bit 0.
bits : 7 - 14 (8 bit)
access : read-write
DIAG1_SYNC_FOUND : Refer to bit 0.
bits : 8 - 16 (9 bit)
access : read-write
DIAG1_MATCH0101 : Refer to bit 0.
bits : 9 - 18 (10 bit)
access : read-write
DIAG1_SIGNAL_DETECTED : Refer to bit 0.
bits : 10 - 20 (11 bit)
access : read-write
Diagnostic IRQ on Word1 - Mask Register
address_offset : 0x210C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIAG1_DCF_21 : 1: Raise an DIAG_IRQ when the corresponding bit of CM_DIAG_IRQ1_STAT_REG is also 1 . 0: Mask the state of the corresponding bit of CM_DIAG_IRQ1_STAT_REG in order to not trigger DIAG_IRQ.
bits : 0 - 0 (1 bit)
access : read-write
DIAG1_DCF_22 : Refer to bit 0.
bits : 1 - 2 (2 bit)
access : read-write
DIAG1_DCF_23 : Refer to bit 0.
bits : 2 - 4 (3 bit)
access : read-write
DIAG1_DCF_24 : Refer to bit 0.
bits : 3 - 6 (4 bit)
access : read-write
DIAG1_DCF_25 : Refer to bit 0.
bits : 4 - 8 (5 bit)
access : read-write
DIAG1_DCF_26 : Refer to bit 0.
bits : 5 - 10 (6 bit)
access : read-write
DIAG1_PHY_RX_EN_RFCU : Refer to bit 0.
bits : 6 - 12 (7 bit)
access : read-write
DIAG1_PHY_TX_EN_RFCU : Refer to bit 0.
bits : 7 - 14 (8 bit)
access : read-write
DIAG1_SYNC_FOUND : Refer to bit 0.
bits : 8 - 16 (9 bit)
access : read-write
DIAG1_MATCH0101 : Refer to bit 0.
bits : 9 - 18 (10 bit)
access : read-write
DIAG1_SIGNAL_DETECTED : Refer to bit 0.
bits : 10 - 20 (11 bit)
access : read-write
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