CM_SLP_CTRL_REG

CM_SLP_CTRL2_REG

CM_SLP_TIMER_REG

SLP_TIMER_SW : Timer SW
bits : 0 - 0 (1 bit)
access : read-write

SLP_TIMER_CNT_SIGN : Refer to CM_SLP_CTRL2_REG->SLP_TIMER_CNT_SIGN.
bits : 5 - 10 (6 bit)
access : read-only

LP_CLK_STATE : LP_CLK state
bits : 6 - 12 (7 bit)
access : read-only

SLP_TIMER_ACTIVE : Refer to SLP_TIMER_SW
bits : 7 - 14 (8 bit)
access : read-only

TCLK_FROM_PCLK : T Clock
bits : 8 - 16 (9 bit)
access : read-write

TCLK_FROM_LPCLK : T Clock
bits : 9 - 18 (10 bit)
access : read-write

CMAC_WAKEUP_ON_SWD_EN : If '1' then enable the generation of CMAC_WAKEUP_ON_SWD.
bits : 24 - 48 (25 bit)
access : read-write

SLP_TIMER_IRQ_STATE : Provides the current state of the CMAC Sleep Timer IRQ.
bits : 0 - 0 (1 bit)
access : read-only

SLP_TIMER_IRQ_CLR : Writing '1' will cause the IRQ to be cleared. This field remains to '1' until the IRQ is cleared. Writing '0' has no effect. Note that clearing the IRQ is not possible as long as the Timer is 1 , since the Expire event has higher priority.
bits : 1 - 2 (2 bit)
access : read-write

SLP_TIMER_IRQ_SET : Writing '1' will cause the IRQ to be set. This field remains to '1' until the IRQ is set. Writing '0' has no effect. System CPU SW may use this field to force CMAC to wakeup through SLP_TIMER. Note that typically SW wakes up CMAC through the SYS2CMAC_IRQ (via PDC).
bits : 2 - 4 (3 bit)
access : read-write

SLP_TIMER_CNT_SIGN : Timer sign
bits : 5 - 10 (6 bit)
access : read-only

LP_CLK_STATE : Refer to CM_SLP_CTRL_REG->LP_CLK_STATE.
bits : 6 - 12 (7 bit)
access : read-only

SLP_TIMER_ACTIVE : Refer to CM_SLP_CTRL_REG->SLP_TIMER_ACTIVE
bits : 7 - 14 (8 bit)
access : read-only

CMAC_WAKEUP_ON_SWD_STATE : Provides the current state of CMAC_WAKEUP_ON_SWD. Writing '1' will clear this bit. Writing '0' has no effect. When CM_SLP_CTRL_REG->CMAC_WAKEUP_ON_SWD_EN=1 and the Radio Power Domain is down and SYS_CTRL_REG->CMAC_DEBUGGER_ENABLE=1 then any negative edge on SWDCLK pin will set the CMAC_WAKEUP_ON_SWD. The CMAC_WAKEUP_ON_SWD logically OR-ed with SLP_TIMER_IRQ is connected to PDC and thus it is able to wake up the CMAC, allowing the connection of CMAC Cortex with the debugger. Note: If the pins are not used as CMAC SWD, then keep SYS_CTRL_REG->CMAC_DEBUGGER_ENABLE=0 to avoid false wakeup triggers.
bits : 8 - 16 (9 bit)
access : read-write

CM_SLP_TIMER_VALUE : Timer value
bits : 0 - 31 (32 bit)
access : read-write