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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_COM_REG

SET_CLK_COM_REG

RESET_CLK_COM_REG


CLK_COM_REG

Peripheral divider register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_COM_REG CLK_COM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ENABLE UART2_ENABLE UART2_CLK_SEL UART3_ENABLE UART3_CLK_SEL SPI_ENABLE SPI_CLK_SEL SPI2_ENABLE SPI2_CLK_SEL I2C_ENABLE I2C_CLK_SEL I2C2_ENABLE I2C2_CLK_SEL SNC_DIV LCD_EXT_CLK_SEL

UART_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-write

UART2_ENABLE : Enables the clock
bits : 1 - 2 (2 bit)
access : read-write

UART2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 2 - 4 (3 bit)
access : read-write

UART3_ENABLE : Enables the clock
bits : 3 - 6 (4 bit)
access : read-write

UART3_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 4 - 8 (5 bit)
access : read-write

SPI_ENABLE : Enables the clock
bits : 5 - 10 (6 bit)
access : read-write

SPI_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 6 - 12 (7 bit)
access : read-write

SPI2_ENABLE : Enables the clock
bits : 7 - 14 (8 bit)
access : read-write

SPI2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 8 - 16 (9 bit)
access : read-write

I2C_ENABLE : Enables the clock
bits : 9 - 18 (10 bit)
access : read-write

I2C_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 10 - 20 (11 bit)
access : read-write

I2C2_ENABLE : Enables the clock
bits : 11 - 22 (12 bit)
access : read-write

I2C2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 12 - 24 (13 bit)
access : read-write

SNC_DIV : Division factor for SNC, w.r.t. pclk setting 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 14 - 29 (16 bit)
access : read-write

LCD_EXT_CLK_SEL : Select LCD external clock speed. 0x0: 1 Hz 0x1: 62.5 Hz 0x2: 125 Hz 0x3: off
bits : 16 - 33 (18 bit)
access : read-write


SET_CLK_COM_REG

Peripheral divider register SET register. Reads back 0x0000
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_CLK_COM_REG SET_CLK_COM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ENABLE UART2_ENABLE UART2_CLK_SEL UART3_ENABLE UART3_CLK_SEL SPI_ENABLE SPI_CLK_SEL SPI2_ENABLE SPI2_CLK_SEL I2C_ENABLE I2C_CLK_SEL I2C2_ENABLE I2C2_CLK_SEL SDADC_CLK_SEL SNC_DIV LCD_EXT_CLK_SEL

UART_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-writeonce

UART2_ENABLE : Enables the clock
bits : 1 - 2 (2 bit)
access : read-writeonce

UART2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 2 - 4 (3 bit)
access : read-writeonce

UART3_ENABLE : Enables the clock
bits : 3 - 6 (4 bit)
access : read-writeonce

UART3_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 4 - 8 (5 bit)
access : read-writeonce

SPI_ENABLE : Enables the clock
bits : 5 - 10 (6 bit)
access : read-writeonce

SPI_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 6 - 12 (7 bit)
access : read-writeonce

SPI2_ENABLE : Enables the clock
bits : 7 - 14 (8 bit)
access : read-writeonce

SPI2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 8 - 16 (9 bit)
access : read-writeonce

I2C_ENABLE : Enables the clock
bits : 9 - 18 (10 bit)
access : read-writeonce

I2C_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 10 - 20 (11 bit)
access : read-writeonce

I2C2_ENABLE : Enables the clock
bits : 11 - 22 (12 bit)
access : read-writeonce

I2C2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 12 - 24 (13 bit)
access : read-writeonce

SDADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 13 - 26 (14 bit)
access : read-writeonce

SNC_DIV : Division factor for SNC, w.r.t. pclk setting 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 14 - 29 (16 bit)
access : read-writeonce

LCD_EXT_CLK_SEL : Select LCD external clock speed. 0x0: 1 Hz 0x1: 62.5 Hz 0x2: 125 Hz 0x3: off
bits : 16 - 33 (18 bit)
access : read-writeonce


RESET_CLK_COM_REG

Peripheral divider register RESET register. Reads back 0x0000
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_CLK_COM_REG RESET_CLK_COM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UART_ENABLE UART2_ENABLE UART2_CLK_SEL UART3_ENABLE UART3_CLK_SEL SPI_ENABLE SPI_CLK_SEL SPI2_ENABLE SPI2_CLK_SEL I2C_ENABLE I2C_CLK_SEL I2C2_ENABLE I2C2_CLK_SEL SDADC_CLK_SEL SNC_DIV LCD_EXT_CLK_SEL

UART_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-write

UART2_ENABLE : Enables the clock
bits : 1 - 2 (2 bit)
access : read-write

UART2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 2 - 4 (3 bit)
access : read-write

UART3_ENABLE : Enables the clock
bits : 3 - 6 (4 bit)
access : read-write

UART3_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 4 - 8 (5 bit)
access : read-write

SPI_ENABLE : Enables the clock
bits : 5 - 10 (6 bit)
access : read-write

SPI_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 6 - 12 (7 bit)
access : read-write

SPI2_ENABLE : Enables the clock
bits : 7 - 14 (8 bit)
access : read-write

SPI2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 8 - 16 (9 bit)
access : read-write

I2C_ENABLE : Enables the clock
bits : 9 - 18 (10 bit)
access : read-write

I2C_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 10 - 20 (11 bit)
access : read-write

I2C2_ENABLE : Enables the clock
bits : 11 - 22 (12 bit)
access : read-write

I2C2_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 12 - 24 (13 bit)
access : read-write

SDADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 13 - 26 (14 bit)
access : read-write

SNC_DIV : Division factor for SNC, w.r.t. pclk setting 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 14 - 29 (16 bit)
access : read-write

LCD_EXT_CLK_SEL : Select LCD external clock speed. 0x0: 1 Hz 0x1: 62.5 Hz 0x2: 125 Hz 0x3: off
bits : 16 - 33 (18 bit)
access : read-write



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