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address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection :
Peripheral divider register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock/ 2
bits : 0 - 0 (1 bit)
access : read-write
LRA_CLK_EN : Enables the clock
bits : 1 - 2 (2 bit)
access : read-write
MC_CLK_EN : Enables the clock
bits : 2 - 4 (3 bit)
access : read-write
MC_CLK_DIV : Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider: 0x0: divide LP clock by 1 0x1: divide LP clock by 2 ... 0x1F: divide LP clock by 32
bits : 3 - 10 (8 bit)
access : read-write
MC_TRIG_DIV : Trigger divider for the motor controller 0x0: divide LP_CLK by 1 0x1: divide LP_CLK by 2 ... 0x1F: divide LP_CLK by 32
bits : 8 - 20 (13 bit)
access : read-write
PCM divider and enables
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCM_DIV : PCM clock divider. Minimum value is 0x2.
bits : 0 - 11 (12 bit)
access : read-write
CLK_PCM_EN : Enable for the internally generated PCM clock The PCM_DIV must be set before or together with CLK_PCM_EN.
bits : 12 - 24 (13 bit)
access : read-write
PCM_SRC_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 13 - 26 (14 bit)
access : read-write
PCM fractional division register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PCM_FDIV : These bits define the fractional division part of the PCM clock. The left most '1' defines the denominator, the number of '1' bits define the numerator. E.g. 0x0110 means 2/9, with a distribution of 1.0001.0000 0xfeee means 13/16, with a distribution of 1111.1110.1110.1110
bits : 0 - 15 (16 bit)
access : read-write
PDM divider and enables
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM_DIV : PDM clock divider
bits : 0 - 7 (8 bit)
access : read-write
CLK_PDM_EN : Enable for the internally generated PDM clock The PDM_DIV must be set before or together with CLK_PDM_EN.
bits : 8 - 16 (9 bit)
access : read-write
PDM_MASTER_MODE : Master mode selection 0: slave mode 1: master mode
bits : 9 - 18 (10 bit)
access : read-write
SRC divider and enables
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRC_DIV : SRC clock divider
bits : 0 - 7 (8 bit)
access : read-write
CLK_SRC_EN : Enable for the internally generated SRC clock The SRC_DIV must be set before or together with CLK_SRC_EN.
bits : 8 - 16 (9 bit)
access : read-write
Peripheral divider register SET register, reads 0x0000
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock/ 2
bits : 0 - 0 (1 bit)
access : read-writeonce
LRA_CLK_EN : Enables the clock
bits : 1 - 2 (2 bit)
access : read-writeonce
MC_CLK_EN : Enables the clock
bits : 2 - 4 (3 bit)
access : read-writeonce
MC_CLK_DIV : Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider: 0x0: divide LP clock by 1 0x1: divide LP clock by 2 ... 0x1F: divide LP clock by 32
bits : 3 - 10 (8 bit)
access : read-writeonce
MC_TRIG_DIV : Trigger divider for the motor controller 0x0: divide LP_CLK by 1 0x1: divide LP_CLK by 2 ... 0x1F: divide LP_CLK by 32
bits : 8 - 20 (13 bit)
access : read-writeonce
Peripheral divider register RESET register, reads 0x0000
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPADC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock/ 2
bits : 0 - 0 (1 bit)
access : read-write
LRA_CLK_EN : Enables the clock
bits : 1 - 2 (2 bit)
access : read-write
MC_CLK_EN : Enables the clock
bits : 2 - 4 (3 bit)
access : read-write
MC_CLK_DIV : Clock divider for the motor controller slot. The slots are clocked on (a PCLK synchronized version of) the LP clock, and can be further divided by this divider: 0x0: divide LP clock by 1 0x1: divide LP clock by 2 ... 0x1F: divide LP clock by 32
bits : 3 - 10 (8 bit)
access : read-write
MC_TRIG_DIV : Trigger divider for the motor controller 0x0: divide LP_CLK by 1 0x1: divide LP_CLK by 2 ... 0x1F: divide LP_CLK by 32
bits : 8 - 20 (13 bit)
access : read-write
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