\n
address_offset : 0x0 Bytes (0x0)
size : 0x8 byte (0x0)
mem_usage : registers
protection :
Peripheral divider register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LCD_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-write
LCD_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 1 - 2 (2 bit)
access : read-write
LCD_RESET_REQ : Generates a SW reset towards the LCD controller.
bits : 4 - 8 (5 bit)
access : read-write
CLK_CHG_EN : Enables the clocks for the charger FSM block
bits : 5 - 10 (6 bit)
access : read-write
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BATCHECK_TRIM : Trim the current load with steps of 2.7 percent from -19.1 percent to +19.1 percent. 0: +0.0 percent , 8: -0 percent 1: +2.7 percent , 9: -2.7 percent 2: +5.5 percent , 10: -5.5 percent 3: +8.2 percent , 11: -8.2 percent 4: +10.9 percent , 12: -10.9 percent 5: +13.6 percent , 13: -13.6 percent 6: +16.4 percent , 14: -16.4 percent 7: +19.1 percent , 15: -19.1 percent
bits : 0 - 3 (4 bit)
access : read-write
BATCHECK_ILOAD : Set the current load to (ILOAD+1) mA.
bits : 4 - 10 (7 bit)
access : read-write
BATCHECK_LOAD_ENABLE : Enable a current load on the battery.
bits : 7 - 14 (8 bit)
access : read-write
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