CLK_AMBA_REG

CLK_RADIO_REG

CLK_CTRL_REG

CLK_TMR_REG

CLK_SWITCH2XTAL_REG

PMU_CTRL_REG

SYS_STAT_REG

CLK_RC32K_REG

CLK_RCX_REG

BANDGAP_REG

VBUS_IRQ_CLEAR_REG

BOD_LVL_CTRL0_REG

BOD_LVL_CTRL1_REG

BOD_LVL_CTRL2_REG

P0_PAD_LATCH_REG

P0_SET_PAD_LATCH_REG

P0_RESET_PAD_LATCH_REG

P1_PAD_LATCH_REG

P1_SET_PAD_LATCH_REG

P1_RESET_PAD_LATCH_REG

BOD_STATUS_REG

POR_VBAT_CTRL_REG

POR_PIN_REG

POR_TIMER_REG

LDO_VDDD_HIGH_CTRL_REG

RESET_STAT_REG

RAM_PWR_CTRL_REG

SECURE_BOOT_REG

DISCHARGE_RAIL_REG

ANA_STATUS_REG

PMU_SLEEP_REG

PMU_TRIM_REG

HCLK_DIV : AHB interface and microprocessor clock. Source clock divided by: 000 = divide hclk by 1 001 = divide hclk by 2 010 = divide hclk by 4 011 = divide hclk by 8 1xx = divide hclk by 16
bits : 0 - 2 (3 bit)
access : read-write

PCLK_DIV : APB interface clock, Cascaded with HCLK: 00 = divide hclk by 1 01 = divide hclk by 2 10 = divide hclk by 4 11 = divide hclk by 8
bits : 4 - 9 (6 bit)
access : read-write

AES_CLK_ENABLE : Clock enable for AES crypto block
bits : 6 - 12 (7 bit)
access : read-write

TRNG_CLK_ENABLE : Clock enable for TRNG block
bits : 8 - 16 (9 bit)
access : read-write

OTP_ENABLE : Clock enable for OTP controller
bits : 9 - 18 (10 bit)
access : read-write

QSPI_DIV : QSPI divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8
bits : 10 - 21 (12 bit)
access : read-write

QSPI_ENABLE : Clock enable for QSPI controller
bits : 12 - 24 (13 bit)
access : read-write

QSPI2_DIV : QSPI divider 00 = divide by 1 01 = divide by 2 10 = divide by 4 11 = divide by 8
bits : 13 - 27 (15 bit)
access : read-write

QSPI2_ENABLE : Clock enable for QSPI RAM controller
bits : 15 - 30 (16 bit)
access : read-write

CMAC_DIV : Division factor for CMAC 0x0 = divide by 1 0x1 = divide by 2 0x2 = divide by 4 0x3 = divide by 8
bits : 0 - 1 (2 bit)
access : read-write

CMAC_CLK_ENABLE : Enables the clock
bits : 2 - 4 (3 bit)
access : read-write

CMAC_CLK_SEL : Selects the clock source 1 = DIV1 clock 0 = DIVN clock
bits : 3 - 6 (4 bit)
access : read-write

CMAC_SYNCH_RESET : Force synchronous reset to CMAC core and Sleep Timer. Its effective only when both Radio and Timer Power Domains are powered and the clocks are enabled. CMAC CPU and CMAC registers, including the retained ones, will be reset. It should be kept in reset for enough time to make sure that it will be captured by CMAC, Low Power and APB clocks.
bits : 4 - 8 (5 bit)
access : read-write

RFCU_ENABLE : Enable the RF control Unit clock
bits : 5 - 10 (6 bit)
access : read-write

SYS_CLK_SEL : Selects the clock source. 0x0 : XTAL32M 0x1 : RC32M 0x2 : The Low Power clock is used 0x3 : The PLL96Mhz is used
bits : 0 - 1 (2 bit)
access : read-write

LP_CLK_SEL : Sets the clock source of the LowerPower clock 0x0: RC32K 0x1: RCX 0x2: XTAL32K through the oscillator with an external Crystal. 0x3: XTAL32K through an external square wave generator (set PID of GPIO to FUNC_GPIO)
bits : 2 - 5 (4 bit)
access : read-write

USB_CLK_SRC : Selects the USB source clock 0 : PLL clock, divided by 2 1 : HCLK
bits : 4 - 8 (5 bit)
access : read-write

RUNNING_AT_LP_CLK : Indicates that either the LP_CLK is being used as clock
bits : 12 - 24 (13 bit)
access : read-only

RUNNING_AT_RC32M : Indicates that the RC32M clock is used as clock
bits : 13 - 26 (14 bit)
access : read-only

RUNNING_AT_XTAL32M : Indicates that the XTAL32M clock is used as clock, and may not be switched off
bits : 14 - 28 (15 bit)
access : read-only

RUNNING_AT_PLL96M : Indicates that the PLL96MHz clock is used as clock, and may not be switched off
bits : 15 - 30 (16 bit)
access : read-only

WAKEUPCT_ENABLE : Enables the clock
bits : 0 - 0 (1 bit)
access : read-write

TMR_PWM_AON_MODE : Maps Timer1_pwm onto P1_01 This state is preserved during deep sleep, to allow PWM output on the pad during deep sleep.
bits : 1 - 2 (2 bit)
access : read-write

TMR2_PWM_AON_MODE : Maps Timer2_pwm onto P1_06. This state is preserved during deep sleep, to allow PWM output on the pad during deep sleep.
bits : 2 - 4 (3 bit)
access : read-write

SWITCH2XTAL : When writing to this register, the clock switch will happen from RC32M to XTAL32M. If any other clock is selected than RC32M, the selection is discarded.
bits : 0 - 0 (1 bit)
access : write-only

PERIPH_SLEEP : Put the peripherals power domain (PD_PER) in powerdown
bits : 0 - 0 (1 bit)
access : read-write

RADIO_SLEEP : Put the digital part of the radio, including CMAC (PD_RAD) in powerdown
bits : 1 - 2 (2 bit)
access : read-write

TIM_SLEEP : Put the Timers Powerdomain (PD_TIM) in powerdown.
bits : 2 - 4 (3 bit)
access : read-write

COM_SLEEP : Put the Communications powerdomain (PD_COM) in powerdown
bits : 3 - 6 (4 bit)
access : read-write

MAP_BANDGAP_EN : Setting this bit will: -map bandgap_enable to P0_25 -map (wokenup OR cmac_slp_timer_expire) to P0_16
bits : 4 - 8 (5 bit)
access : read-write

RESET_ON_WAKEUP : Perform a Hardware Reset after waking up. Booter will be started.
bits : 5 - 10 (6 bit)
access : read-write

SYS_SLEEP : Put the System powerdomain (PD_SYS) in powerdown. If this bit is '1', and there is no pending IRQ in the PDC for the M33, the PD_SYS will be switched off. Wakeup should be handled by the PDC.
bits : 6 - 12 (7 bit)
access : read-write

RETAIN_CACHE : Selects the retainability of the cache block during deep sleep. '1' is retainable, '0' is power gated
bits : 7 - 14 (8 bit)
access : read-write

ENABLE_CLKLESS : Selects the clockless sleep mode. Wakeup is done asynchronously. When set to '1', the lp_clk is stopped during deep sleep, until a wakeup event (not debounced) is detected by the WAKUPCT block. When set to '0', the lp_clk continues running, so the MAC counters keep on running. This mode cannot be combined with regulated sleep, so keep SLEEP_TIMER=0 when using ENABLE_CLKLESS.
bits : 8 - 16 (9 bit)
access : read-write

RAD_IS_DOWN : Indicates that PD_RAD is in power down
bits : 0 - 0 (1 bit)
access : read-only

RAD_IS_UP : Indicates that PD_RAD is functional
bits : 1 - 2 (2 bit)
access : read-only

PER_IS_DOWN : Indicates that PD_PER is in power down
bits : 2 - 4 (3 bit)
access : read-only

PER_IS_UP : Indicates that PD_PER is functional
bits : 3 - 6 (4 bit)
access : read-only

SYS_IS_DOWN : Indicates that PD_SYS is in power down
bits : 4 - 8 (5 bit)
access : read-only

SYS_IS_UP : Indicates that PD_SYS is functional
bits : 5 - 10 (6 bit)
access : read-only

MEM_IS_DOWN : Indicates that PD_MEM is in power down
bits : 6 - 12 (7 bit)
access : read-only

MEM_IS_UP : Indicates that PD_MEM is functional
bits : 7 - 14 (8 bit)
access : read-only

TIM_IS_DOWN : Indicates that PD_TIM is in power down
bits : 8 - 16 (9 bit)
access : read-only

TIM_IS_UP : Indicates that PD_TIM is functional
bits : 9 - 18 (10 bit)
access : read-only

COM_IS_DOWN : Indicates that PD_COM is in power down
bits : 10 - 20 (11 bit)
access : read-only

COM_IS_UP : Indicates that PD_COM is functional
bits : 11 - 22 (12 bit)
access : read-only

DBG_IS_ACTIVE : Indicates that a debugger is attached.
bits : 12 - 24 (13 bit)
access : read-only

POWER_IS_UP : Indicates that the Startup statemachine is finished, and all power regulation is in order. In UltraFastWakeup mode, the SW needs to wait for this signal before starting any heavy traffic.
bits : 13 - 26 (14 bit)
access : read-only

RC32K_ENABLE : Enables the 32kHz RC oscillator
bits : 0 - 0 (1 bit)
access : read-write

RC32K_TRIM : 0000 = lowest frequency 0111 = default 1111 = highest frequency
bits : 1 - 5 (5 bit)
access : read-write

RCX_ENABLE : Enable the RCX oscillator
bits : 0 - 0 (1 bit)
access : read-write

RCX_RADJUST : Adjust resistance part of RC-time delay. Lower resistance increases power consumption. 0x0: maximum resistance 0x1: minimum resistance
bits : 1 - 2 (2 bit)
access : read-write

RCX_CADJUST : Adjust capacitance part of RC-time delay. 0x00: minimum capacitance 0x1F: maximum capacitance
bits : 2 - 8 (7 bit)
access : read-write

RCX_C0 : Add unit capacitance to RC-time delay.
bits : 7 - 14 (8 bit)
access : read-write

RCX_BIAS : LDO bias current. 0x0: minimum 0xF: maximum
bits : 8 - 19 (12 bit)
access : read-write

BGR_TRIM : Trim register for bandgap
bits : 0 - 4 (5 bit)
access : read-write

SYSRAM_LPMX : RAM Transparent Light Sleep (TLS) Core Enable for System RAMs. Assert low to enable the TLS core feature, which will result in lower leakage current. In case VDD is below 0.81V, it is necessary to hold this pin high to maintain data retention.
bits : 5 - 10 (6 bit)
access : read-write

BGR_ITRIM : Current trimming for bias
bits : 6 - 17 (12 bit)
access : read-write

BANDGAP_ENABLE_CLAMP : Enables a supply clamp inside the bandgap that improves PSRR. Should be enabled by software after cold boot.
bits : 12 - 24 (13 bit)
access : read-write

VBUS_IRQ_CLEAR : Writing any value to this register will reset the VBUS_IRQ line
bits : 0 - 15 (16 bit)
access : write-only

BOD_LVL_VBAT : Brown-out detection level for VBAT disable the bod channel before adjusting the level setting. VTH_BOD = 1.5*(1.2 * (BOD_LVL+1)/192)
bits : 0 - 8 (9 bit)
access : read-write

BOD_LVL_V30 : Brown-out detection level for V30 disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 9 - 26 (18 bit)
access : read-write

BOD_LVL_V18 : Brown-out detection level for V18 disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 18 - 44 (27 bit)
access : read-write

BOD_LVL_V18P : Brown-out detection level for V18P disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 0 - 8 (9 bit)
access : read-write

BOD_LVL_VDD_ON : Brown-out detection level for VDD in active disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 9 - 25 (17 bit)
access : read-write

BOD_LVL_VDD_RET : Brown-out detection level for VDD in sleep disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 17 - 41 (25 bit)
access : read-write

BOD_LVL_V18F : Brown-out detection level for V18F disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 0 - 8 (9 bit)
access : read-write

BOD_LVL_V14 : Brown-out detection level for V14 disable the bod channel before adjusting the level setting. VTH_BOD = 1.2 * (BOD_LVL+1)/192
bits : 9 - 26 (18 bit)
access : read-write

P0_LATCH_EN : Direct write to the specific pad_latch_enable signal
bits : 0 - 31 (32 bit)
access : read-write

P0_SET_LATCH_EN : Direct Set of the marked bits. Reading returns 0x0.
bits : 0 - 31 (32 bit)
access : read-writeonce

P0_RESET_LATCH_EN : Direct Reset of the marked bits. Reading returns 0x0.
bits : 0 - 31 (32 bit)
access : read-write

P1_LATCH_EN : Direct write to the specific pad_latch_enable signal
bits : 0 - 22 (23 bit)
access : read-write

P1_SET_LATCH_EN : Direct Set of the marked bits. Reading returns 0x0.
bits : 0 - 22 (23 bit)
access : read-writeonce

P1_RESET_LATCH_EN : Direct Reset of the marked bits. Reading returns 0x0.
bits : 0 - 22 (23 bit)
access : read-write

BOD_VBAT : 1: below trigger level (BOD event) 0: above trigger level
bits : 0 - 0 (1 bit)
access : read-only

BOD_V30 : 1: below trigger level (BOD event) 0: above trigger level
bits : 1 - 2 (2 bit)
access : read-only

BOD_V18 : 1: below trigger level (BOD event) 0: above trigger level
bits : 2 - 4 (3 bit)
access : read-only

BOD_V18P : 1: below trigger level (BOD event) 0: above trigger level
bits : 3 - 6 (4 bit)
access : read-only

BOD_VDD : 1: below trigger level (BOD event) 0: above trigger level
bits : 4 - 8 (5 bit)
access : read-only

BOD_V18F : 1: below trigger level (BOD event) 0: above trigger level
bits : 5 - 10 (6 bit)
access : read-only

BOD_V14 : 1: below trigger level (BOD event) 0: above trigger level
bits : 6 - 12 (7 bit)
access : read-only

POR_VBAT_THRES_LOW : Low-side (CTAT) threshold contribution Level --> Threshold 0xC --> 1.25V 0xC --> 1.27V 0xC --> 1.29V 0xC --> 1.31V 0x0 --> 1.44V 0x1 --> 1.49V 0x2 --> 1.53V 0x3 --> 1.58V 0x4 --> 1.63V 0x5 --> 1.68V 0x6 --> 1.73V 0x7 --> 1.78V 0x8 --> 1.83V 0x9 --> 1.87V 0xA --> 1.92V 0xB --> 1.97V 0xF --> 1.63V use only with POR_VBAT_THRES_LOW=0x6 and POR_VBAT_THRES_HYST=0x2
bits : 0 - 3 (4 bit)
access : read-write

POR_VBAT_THRES_HIGH : High-side (PTAT) threshold contribution: Level --> Threshold 0x0 --> 1.25V 0x1 --> 1.27V 0x2 --> 1.29V 0x3 --> 1.31V 0x4 --> 1.44V 0x5 --> 1.49V 0x6 --> 1.53V 0x7 --> 1.58V 0x8 --> 1.63V 0x9 --> 1.68V 0xA --> 1.73V 0xB --> 1.78V0xC --> 1.83V0xD --> 1.87V0xE --> 1.92V 0xF --> 1.97V
bits : 4 - 11 (8 bit)
access : read-write

POR_VBAT_HYST_LOW : Controls hysteresis of POR. 20mV per step. Must be set to 0x2 when thres_ctrl_low is set to 0xf.
bits : 8 - 19 (12 bit)
access : read-write

POR_VBAT_ENABLE : Enables generation of the POR
bits : 12 - 24 (13 bit)
access : read-write

POR_VBAT_MASK_N : Enables propagation of the generated POR
bits : 13 - 26 (14 bit)
access : read-write

POR_PIN_SELECT : 0x00: P0_00 ... 0x1f: P0_31 0x20: P1_00 ... 0x36: P1_22 0x37 to 0x3E: reserved 0x3F: POR generation disabled
bits : 0 - 5 (6 bit)
access : read-write

POR_PIN_POLARITY : 0: Active Low 1: Active High Note: This applies only for the GPIO pin. Reset pad is always active High
bits : 7 - 14 (8 bit)
access : read-write

POR_TIME : Time for the POReset to happen. Formula: Time = POR_TIME x 4096 x RC32 clock period Default value: ~3 seconds
bits : 0 - 6 (7 bit)
access : read-write

LDO_VDDD_HIGH_VREF_HOLD : 0: Indicates that the reference input is tracked, 1: Indicates that the reference input is sampled.
bits : 0 - 0 (1 bit)
access : read-write

LDO_VDDD_HIGH_ENABLE : 0: LDO VDDD_HIGH off, 1: LDO VDDD_HIGH on.
bits : 1 - 2 (2 bit)
access : read-write

LDO_VDDD_HIGH_STATIC_LOAD_ENABLE : Enables a static load of approx. 10 uA at the output of the LDO VDDD_HIGH.
bits : 2 - 4 (3 bit)
access : read-write

LDO_VDDD_HIGH_LOW_ZOUT_DISABLE : Disables the low Zout switch. The low Zout switch pulls the output of the LDO to ground. When 0, the output of the LDO is pulled to ground when the LDO is disabled. When 1, the output of the LDO remains floating when the LDO is disabled.
bits : 3 - 6 (4 bit)
access : read-write

PORESET_STAT : Indicates that a PowerOn Reset has happened. All bitfields of RESET_STAT_REG should be read (in order to check the source of reset) and then cleared to '0', allowing thus the HW to automatically set to '1' the proper bitfields during the next reset event.
bits : 0 - 0 (1 bit)
access : read-write

HWRESET_STAT : Indicates that a HW Reset has happened
bits : 1 - 2 (2 bit)
access : read-write

SWRESET_STAT : Indicates that a SW Reset has happened
bits : 2 - 4 (3 bit)
access : read-write

WDOGRESET_STAT : Indicates that a Watchdog timeout has happened. Note that it is also set when a POReset has happened.
bits : 3 - 6 (4 bit)
access : read-write

SWD_HWRESET_STAT : Indicates that a write to SWD_RESET_REG has happened. Note that it is also set when a POReset has happened.
bits : 4 - 8 (5 bit)
access : read-write

CMAC_WDOGRESET_STAT : Indicates that a CMAC-Watchdog timeout has happened. Note that it is also set when a POReset has happened.
bits : 5 - 10 (6 bit)
access : read-write

RAM1_PWR_CTRL : Power state control of the individual RAMs. May only change when the memory isn't accessed. When PD_MEM_IS_UP: 0x0: Normal operation 0x1: Normal operation 0x2: Retained (no access possible) 0x3: Off (memory content corrupted) When PD_MEM_IS_DOWN: 0x0: Retained 0x1: Off (memory content corrupted) 0x2: Retained 0x3: Off (memory content corrupted)
bits : 0 - 1 (2 bit)
access : read-write

RAM2_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 2 - 5 (4 bit)
access : read-write

RAM3_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 4 - 9 (6 bit)
access : read-write

RAM4_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 6 - 13 (8 bit)
access : read-write

RAM5_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 8 - 17 (10 bit)
access : read-write

RAM6_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 10 - 21 (12 bit)
access : read-write

RAM7_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 12 - 25 (14 bit)
access : read-write

RAM8_PWR_CTRL : See description of RAM1_PWR_CTRL.
bits : 14 - 29 (16 bit)
access : read-write

SECURE_BOOT : Follows the respective OTP flag value. Its value is updated by the BootROM code. 1: system is a secure system supporting secure boot 0: system is not supporting secure boot
bits : 0 - 0 (1 bit)
access : read-write

FORCE_DEBUGGER_OFF : Follows the respective OTP flag value. Its value is updated by the BootROM code. 1: The system debugger SWD is totally disabled. 0: The system debugger is enabled with DEBUGGER_ENABLE
bits : 1 - 2 (2 bit)
access : read-write

FORCE_CMAC_DEBUGGER_OFF : This bit will permanently disable the CMAC debugger
bits : 2 - 4 (3 bit)
access : read-write

PROT_SIG_KEY_WRITE : This bit will permanently disable ANY write capability at OTP offset 0x000008C0 and for the complete segment
bits : 3 - 6 (4 bit)
access : read-write

PROT_AES_KEY_WRITE : This bit will permanently disable ANY write capability at OTP offset 0x00000A00 and for the complete segment
bits : 4 - 8 (5 bit)
access : read-write

PROT_AES_KEY_READ : This bit will permanently disable CPU read capability at OTP offset 0x00000A00 and for the complete segment
bits : 5 - 10 (6 bit)
access : read-write

PROT_QSPI_KEY_WRITE : This bit will permanently disable ANY write capability at OTP offset 0x00000B00 and for the complete segment
bits : 6 - 12 (7 bit)
access : read-write

PROT_QSPI_KEY_READ : This bit will permanently disable CPU read capability at OTP offset 0x00000B00 and for the complete segment
bits : 7 - 14 (8 bit)
access : read-write

RESET_V14 : 1: Enables immediate discharging of the V14 rail. Note that the source is not disabled. 0: disable immediate discharging of the V14 rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V14
bits : 0 - 0 (1 bit)
access : read-write

RESET_V18 : 1: Enables immediate discharging of the V18 rail. Note that the source is not disabled. 0: disable immediate discharging of the V18 rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18
bits : 1 - 2 (2 bit)
access : read-write

RESET_V18P : 1: Enables immediate discharging of the V18P rail. Note that the source is not disabled. 0: disable immediate discharging of the V18P rail. This bit is ORed with the automatic function controlled by PMU_RESET_RAIL_REG.RESET_V18P
bits : 2 - 4 (3 bit)
access : read-write

BOD_VIN_NOK : General output of the BOD to indicate that one of the monitored inputs is below the trigger-level.
bits : 0 - 0 (1 bit)
access : read-only

LDO_VDD_HIGH_OK : When high the ADC LDO is active. This LDO also supplies part of the LRA
bits : 1 - 2 (2 bit)
access : read-only

LDO_CORE_OK : When high LDO_CORE(LDO1V2) is active
bits : 2 - 4 (3 bit)
access : read-only

LDO_RADIO_OK : When high LDO_RADIO is active
bits : 3 - 6 (4 bit)
access : read-only

LDO_1V8_OK : When high LDO_IO is active
bits : 4 - 8 (5 bit)
access : read-only

LDO_1V8P_OK : When high LDO_IO2 is active
bits : 5 - 10 (6 bit)
access : read-only

LDO_3V0_VBUS_OK : When high LDO_VBUS is active
bits : 6 - 12 (7 bit)
access : read-only

LDO_3V0_VBAT_OK : When high LDO_VBAT is active
bits : 7 - 14 (8 bit)
access : read-only

BANDGAP_OK : When high bandgap is active
bits : 8 - 16 (9 bit)
access : read-only

VBUS_AVAILABLE : High when VBUS > ( VBAT + 150 mV). Hysteresis is approx. 40 mV
bits : 9 - 18 (10 bit)
access : read-only

COMP_VDD_OK : COMP_VDD_OK = 1 -> VDD > 1.125V
bits : 10 - 20 (11 bit)
access : read-only

COMP_VBAT_LOW : COMP_VBAT_LOW = 1 -> VBAT > 1.667V
bits : 11 - 22 (12 bit)
access : read-only

COMP_VBAT_HIGH : COMP_VBAT_HIGH =1 -> VBAT > 2.5V
bits : 12 - 24 (13 bit)
access : read-only

COMP_VBUS_LOW : COMP_VBUS_LOW = 1 -> VBUS > 3.4V
bits : 13 - 26 (14 bit)
access : read-only

COMP_VBUS_HIGH : COMP_VBUS_HIGH = 1 -> VBUS > 4V
bits : 14 - 28 (15 bit)
access : read-only

BG_REFRESH_INTERVAL : This is a value defining the interval every which the Bandgap will be activated for refresh. The value represents ticks of lp_clk/64 e.g. 30,5 us * 64 = 1,9 ms.
bits : 0 - 11 (12 bit)
access : read-write

BOD_SLEEP_INTERVAL : This is a value defining the interval every which Brown Out Detection is activated to check on the power rails voltage. The value represents BG_REFRESH_INTERVALs
bits : 12 - 27 (16 bit)
access : read-write

FAST_WAKEUP : Speeds up the wakeup process by enabling all LDOs simultaneously instead of in staggered order. Only use if all voltages have been retained during sleep.
bits : 16 - 32 (17 bit)
access : read-write

ULTRA_FAST_WAKEUP : Allows the core to start running on the RC32M while the PMU is still waiting for supplies to settle to the final value. Only use in combination with FAST_WAKEUP and 0.9 V on VDD during sleep.
bits : 17 - 34 (18 bit)
access : read-write

CLAMP_VDD_WKUP_MAX : Forces the VDD clamp voltage to its maximum value when waking up from sleep.
bits : 18 - 36 (19 bit)
access : read-write

LDO_SUPPLY_VBUS_TRIM : Trim setting for LDO_SUPPLY_VBUS Sign-magnitude notation, trim range ±10 percent
bits : 0 - 3 (4 bit)
access : read-write

LDO_SUPPLY_VBAT_TRIM : Trim setting for LDO_SUPPLY_VBAT Sign-magnitude notation, trim range ±10 percent
bits : 4 - 11 (8 bit)
access : read-write

LDO_1V8P_TRIM : Trim setting for LDO_1V8P Unsigned binary notation, trim range ±10 percent
bits : 8 - 19 (12 bit)
access : read-write

LDO_1V8_TRIM : Trim setting for LDO_1V8 Unsigned binary notation, trim range ±10 percent
bits : 12 - 27 (16 bit)
access : read-write