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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x74 byte (0x0)
mem_usage : registers
protection :

Registers

CLK_FREQ_TRIM_REG

TRIM_CTRL_REG

XTALRDY_CTRL_REG

PLL_SYS_STATUS_REG


CLK_FREQ_TRIM_REG

Xtal frequency trimming register.
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLK_FREQ_TRIM_REG CLK_FREQ_TRIM_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL32M_TRIM XTAL32M_RAMP XTAL32M_START

XTAL32M_TRIM : Xtal frequency trimming register. 0x2BF = lowest frequency (high load capacitance) 0x000 = highest frequency (low load capacitance) Cload = 5.0p + 6.09p * XTAL32M_TRIM/0x2BF- this includes the PCB parasitic capacitances of the reference desing
bits : 0 - 9 (10 bit)
access : read-write

XTAL32M_RAMP : Xtal frequency trimming register - RAMP phase of startup. 0x2BF = lowest frequency (high load capacitance) 0x000 = highest frequency (low load capacitance) Cload = 5.0p + 6.09p * XTAL32M_TRIM/0x2BF- this includes the PCB parasitic capacitances of the reference desing
bits : 10 - 29 (20 bit)
access : read-write

XTAL32M_START : Xtal frequency trimming register - START phase of startup 0x2BF = lowest frequency (high load capacitance) 0x000 = highest frequency (low load capacitance) Cload = 5.0p + 6.09p * XTAL32M_TRIM/0x2BF- this includes the PCB parasitic capacitances of the reference desing
bits : 20 - 49 (30 bit)
access : read-write


TRIM_CTRL_REG

Control trimming of the XTAL32M
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM_CTRL_REG TRIM_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTAL_COUNT_N XTAL_TRIM_SELECT XTAL_SETTLE_N

XTAL_COUNT_N : Defines the number of XTAL cycles to be counted, before the xtal trimming is applied, in steps of 32. 0x01: 32 0x02: 64 0x3f:2016
bits : 0 - 5 (6 bit)
access : read-write

XTAL_TRIM_SELECT : Select which source controls the XTAL trimming 0b00: xtal counter. Starts CLK_FREQ_TRIM_REG[XTAL32M_START] after COUNT_N * 32 xtal pulses trim is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b01: xtal OK filter. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START], when xtal is ramping is changed to CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b10: statically forced off. Only uses CLK_FREQ_TRIM_REG[XTAL32M_TRIM]. 0b11: xtal OK filter, 2 stage. Starts with CLK_FREQ_TRIM_REG[XTAL32M_START] switches to CLK_FREQ_TRIM_REG[XTAL32M_RAMP] after timeout (sw1='1', XTAL32M_CTRL0_REG[XTAL32M_SW_DELAY]), and switches to CLK_FREQ_TRIM_REG[XTAL32M_TRIM] when sw2='1'.
bits : 6 - 13 (8 bit)
access : read-write

XTAL_SETTLE_N : Designates that the XTAL can be safely used as the CPU clock. When XTAL_CLK_CNT reases this value, the signal XTAL_SETTLE_READY will be set
bits : 8 - 21 (14 bit)
access : read-write


XTALRDY_CTRL_REG

Control register for XTALRDY IRQ
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

XTALRDY_CTRL_REG XTALRDY_CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTALRDY_CNT XTALRDY_CLK_SEL

XTALRDY_CNT : Number of 32kHz or 256kHz cycles between the crystal is enabled, and the XTALRDY_IRQ is fired. Frequency set by XTALRDY_CLK_SEL. 0x00: no interrupt
bits : 0 - 7 (8 bit)
access : read-write

XTALRDY_CLK_SEL : XTALRDY IRQ timer clock selection: 0: 32KHz 1: 256kHz
bits : 8 - 16 (9 bit)
access : read-write


PLL_SYS_STATUS_REG

System PLL status register.
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PLL_SYS_STATUS_REG PLL_SYS_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PLL_LOCK_FINE PLL_BEST_MIN_CUR PLL_CALIBRATION_END LDO_PLL_OK

PLL_LOCK_FINE : 1: PLL locked
bits : 0 - 0 (1 bit)
access : read-only

PLL_BEST_MIN_CUR : Calibrated VCO current.
bits : 5 - 15 (11 bit)
access : read-only

PLL_CALIBRATION_END : Indicates that calibration has finished.
bits : 11 - 22 (12 bit)
access : read-only

LDO_PLL_OK : 1: Indicates that LDO PLL is in regulation.
bits : 15 - 30 (16 bit)
access : read-only



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