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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3C byte (0x0)
mem_usage : registers
protection :

Registers

VDD_REG

V18_REG

V18P_REG

TEST_REG

STATUS1_REG

STATUS2_REG

STATUS3_REG

STATUS4_REG

IRQ_STATUS_REG

IRQ_CLEAR_REG

IRQ_MASK_REG

CTRL1_REG

CTRL2_REG

V14_REG


VDD_REG

DCDC VDD Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDD_REG VDD_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_VDD_ENABLE_LV DCDC_VDD_ENABLE_HV DCDC_VDD_IDLE_MIN DCDC_VDD_IDLE_HYST DCDC_VDD_CUR_LIM_MIN DCDC_VDD_CUR_LIM_MAX_LV DCDC_VDD_CUR_LIM_MAX_HV DCDC_VDD_TRIM DCDC_VDD_FAST_RAMPING

DCDC_VDD_ENABLE_LV : Output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 0 - 0 (1 bit)
access : read-write

DCDC_VDD_ENABLE_HV : Output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 1 - 2 (2 bit)
access : read-write

DCDC_VDD_IDLE_MIN : Minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 2 - 8 (7 bit)
access : read-write

DCDC_VDD_IDLE_HYST : Idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 7 - 18 (12 bit)
access : read-write

DCDC_VDD_CUR_LIM_MIN : Minimum current limit I = 30 mA * (1 + N)
bits : 12 - 28 (17 bit)
access : read-write

DCDC_VDD_CUR_LIM_MAX_LV : Maximum current limit (low battery voltage mode) I = 30 mA * (1 + N)
bits : 17 - 38 (22 bit)
access : read-write

DCDC_VDD_CUR_LIM_MAX_HV : Maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 22 - 48 (27 bit)
access : read-write

DCDC_VDD_TRIM : Output voltage trim Steps of 25 mV
bits : 27 - 56 (30 bit)
access : read-write

DCDC_VDD_FAST_RAMPING : Fast current ramping (improves response time at the cost of more ripple)
bits : 31 - 62 (32 bit)
access : read-write


V18_REG

DCDC V18 Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18_REG V18_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18_ENABLE_LV DCDC_V18_ENABLE_HV DCDC_V18_IDLE_MIN DCDC_V18_IDLE_HYST DCDC_V18_CUR_LIM_MIN DCDC_V18_CUR_LIM_MAX_LV DCDC_V18_CUR_LIM_MAX_HV DCDC_V18_TRIM DCDC_V18_FAST_RAMPING

DCDC_V18_ENABLE_LV : Output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 0 - 0 (1 bit)
access : read-write

DCDC_V18_ENABLE_HV : Output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 1 - 2 (2 bit)
access : read-write

DCDC_V18_IDLE_MIN : Minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 2 - 8 (7 bit)
access : read-write

DCDC_V18_IDLE_HYST : Idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 7 - 18 (12 bit)
access : read-write

DCDC_V18_CUR_LIM_MIN : Minimum current limit I = 30 mA * (1 + N)
bits : 12 - 28 (17 bit)
access : read-write

DCDC_V18_CUR_LIM_MAX_LV : Maximum current limit (low battery voltage mode) I = 30 mA * (1 + N)
bits : 17 - 38 (22 bit)
access : read-write

DCDC_V18_CUR_LIM_MAX_HV : Maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 22 - 48 (27 bit)
access : read-write

DCDC_V18_TRIM : Output voltage trim Steps of 25 mV
bits : 27 - 57 (31 bit)
access : read-write

DCDC_V18_FAST_RAMPING : Fast current ramping (improves response time at the cost of more ripple)
bits : 31 - 62 (32 bit)
access : read-write


V18P_REG

DCDC V18P Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V18P_REG V18P_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V18P_ENABLE_LV DCDC_V18P_ENABLE_HV DCDC_V18P_IDLE_MIN DCDC_V18P_IDLE_HYST DCDC_V18P_CUR_LIM_MIN DCDC_V18P_CUR_LIM_MAX_LV DCDC_V18P_CUR_LIM_MAX_HV DCDC_V18P_TRIM DCDC_V18P_FAST_RAMPING

DCDC_V18P_ENABLE_LV : Output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 0 - 0 (1 bit)
access : read-write

DCDC_V18P_ENABLE_HV : Output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 1 - 2 (2 bit)
access : read-write

DCDC_V18P_IDLE_MIN : Minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 2 - 8 (7 bit)
access : read-write

DCDC_V18P_IDLE_HYST : Idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 7 - 18 (12 bit)
access : read-write

DCDC_V18P_CUR_LIM_MIN : Minimum current limit I = 30 mA * (1 + N)
bits : 12 - 28 (17 bit)
access : read-write

DCDC_V18P_CUR_LIM_MAX_LV : Maximum current limit (low battery voltage mode) I = 30 mA * (1 + N)
bits : 17 - 38 (22 bit)
access : read-write

DCDC_V18P_CUR_LIM_MAX_HV : Maximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 22 - 48 (27 bit)
access : read-write

DCDC_V18P_TRIM : Output voltage trim Steps of 25 mV
bits : 27 - 57 (31 bit)
access : read-write

DCDC_V18P_FAST_RAMPING : Fast current ramping (improves response time at the cost of more ripple)
bits : 31 - 62 (32 bit)
access : read-write


TEST_REG

DCDC Test Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TEST_REG TEST_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_FORCE_P_SW DCDC_FORCE_N_SW DCDC_FORCE_FW_SW DCDC_FORCE_V14_SW DCDC_FORCE_V18_SW DCDC_FORCE_VDD_SW DCDC_FORCE_V18P_SW DCDC_FORCE_IDLE DCDC_ANA_TEST DCDC_OUTPUT_MON DCDC_FORCE_COMP_CLK DCDC_FORCE_CUR_LIM DCDC_FORCE_COMP_CLK_VAL DCDC_FORCE_CUR_LIM_VAL DCDC_TEST_OUT

DCDC_FORCE_P_SW : Force P switch on
bits : 0 - 0 (1 bit)
access : read-write

DCDC_FORCE_N_SW : Force N switch on
bits : 1 - 2 (2 bit)
access : read-write

DCDC_FORCE_FW_SW : Force FW switch on
bits : 2 - 4 (3 bit)
access : read-write

DCDC_FORCE_V14_SW : Force V14 switch on
bits : 3 - 6 (4 bit)
access : read-write

DCDC_FORCE_V18_SW : Force V18 switch on
bits : 4 - 8 (5 bit)
access : read-write

DCDC_FORCE_VDD_SW : Force VDD switch on
bits : 5 - 10 (6 bit)
access : read-write

DCDC_FORCE_V18P_SW : Force V18P switch on
bits : 6 - 12 (7 bit)
access : read-write

DCDC_FORCE_IDLE : Force idle mode
bits : 7 - 14 (8 bit)
access : read-write

DCDC_ANA_TEST : Analog test bus 000 = None 001 = High side ground 010 = Low side supply 011 = Bootstrap voltage 100 = 1.0 V buffer output 101 = None 110 = None 111 = None
bits : 8 - 18 (11 bit)
access : read-write

DCDC_OUTPUT_MON : Output monitor switch (connect to ADC) 000 = None 001 = VDD 010 = V18 011 = V14 100 = V18P 101 = V18F 110 = None 111 = None
bits : 11 - 24 (14 bit)
access : read-write

DCDC_FORCE_COMP_CLK : Disables automatic comparator clock, clock lines values based on FORCE_COMP_CLK_VAL
bits : 14 - 28 (15 bit)
access : read-write

DCDC_FORCE_CUR_LIM : Force output current setting
bits : 15 - 30 (16 bit)
access : read-write

DCDC_FORCE_COMP_CLK_VAL : Sets clock lines for the output comparators
bits : 16 - 35 (20 bit)
access : read-write

DCDC_FORCE_CUR_LIM_VAL : Current limit setting when forced
bits : 20 - 44 (25 bit)
access : read-write

DCDC_TEST_OUT : Selects which register appears on the test mode pins 0 = None 1 = DCDC_STATUS_1 High Bits 2 = DCDC_STATUS_1 Low Bits 3 = DCDC_STATUS_2 High Bits 4 = DCDC_STATUS_2 Low Bits 5 = DCDC_STATUS_3 High Bits 6 = DCDC_STATUS_3 Low Bits 7 = DCDC_STATUS_4 Low Bits 8-F = Reserved
bits : 25 - 53 (29 bit)
access : read-write


STATUS1_REG

DCDC First Status Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS1_REG STATUS1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_STARTUP_COMPLETE DCDC_P_SW_STATE DCDC_N_SW_STATE DCDC_V14_SW_STATE DCDC_V18_SW_STATE DCDC_VDD_SW_STATE DCDC_V18P_SW_STATE DCDC_LV_MODE DCDC_N_COMP DCDC_P_COMP DCDC_N_COMP_N DCDC_N_COMP_P DCDC_V14_COMP_NOK DCDC_V18_COMP_NOK DCDC_VDD_COMP_NOK DCDC_V18P_COMP_NOK DCDC_V14_COMP_OK DCDC_V18_COMP_OK DCDC_VDD_COMP_OK DCDC_V18P_COMP_OK DCDC_V14_AVAILABLE DCDC_V18_AVAILABLE DCDC_VDD_AVAILABLE DCDC_V18P_AVAILABLE

DCDC_STARTUP_COMPLETE : Indicates if the converter is enabled and the startup counter has expired (internal biasing settled)
bits : 0 - 0 (1 bit)
access : read-only

DCDC_P_SW_STATE : DCDC state machine PSW output
bits : 1 - 2 (2 bit)
access : read-only

DCDC_N_SW_STATE : DCDC state machine NSW output
bits : 2 - 4 (3 bit)
access : read-only

DCDC_V14_SW_STATE : DCDC state machine V14 output
bits : 3 - 6 (4 bit)
access : read-only

DCDC_V18_SW_STATE : DCDC state machine V18 output
bits : 4 - 8 (5 bit)
access : read-only

DCDC_VDD_SW_STATE : DCDC state machine VDD output
bits : 5 - 10 (6 bit)
access : read-only

DCDC_V18P_SW_STATE : DCDC state machine V18P output
bits : 6 - 12 (7 bit)
access : read-only

DCDC_LV_MODE : Indicates if the converter is in low battery voltage mode
bits : 7 - 14 (8 bit)
access : read-only

DCDC_N_COMP : DCDC N side continuous time comparator output
bits : 8 - 16 (9 bit)
access : read-only

DCDC_P_COMP : DCDC P side continuous time comparator output
bits : 9 - 18 (10 bit)
access : read-only

DCDC_N_COMP_N : DCDC N side dynamic comparator N output
bits : 10 - 20 (11 bit)
access : read-only

DCDC_N_COMP_P : DCDC N side dynamic comparator P output
bits : 11 - 22 (12 bit)
access : read-only

DCDC_V14_COMP_NOK : NOK output of V14 comparator
bits : 16 - 32 (17 bit)
access : read-only

DCDC_V18_COMP_NOK : NOK output of V18 comparator
bits : 17 - 34 (18 bit)
access : read-only

DCDC_VDD_COMP_NOK : NOK output of VDD comparator
bits : 18 - 36 (19 bit)
access : read-only

DCDC_V18P_COMP_NOK : NOK output of V18P comparator
bits : 19 - 38 (20 bit)
access : read-only

DCDC_V14_COMP_OK : OK output of V14 comparator
bits : 20 - 40 (21 bit)
access : read-only

DCDC_V18_COMP_OK : OK output of V18 comparator
bits : 21 - 42 (22 bit)
access : read-only

DCDC_VDD_COMP_OK : OK output of VDD comparator
bits : 22 - 44 (23 bit)
access : read-only

DCDC_V18P_COMP_OK : OK output of V18P comparator
bits : 23 - 46 (24 bit)
access : read-only

DCDC_V14_AVAILABLE : Indicates whether V14 is available Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured.
bits : 24 - 48 (25 bit)
access : read-only

DCDC_V18_AVAILABLE : Indicates whether V18 is available Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured.
bits : 25 - 50 (26 bit)
access : read-only

DCDC_VDD_AVAILABLE : Indicates whether VDD is available Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured.
bits : 26 - 52 (27 bit)
access : read-only

DCDC_V18P_AVAILABLE : Indicates whether V18P is available Requires that converter is enabled, output is enabled and V_OK has occured. Reset when too many V_NOK events have occured.
bits : 27 - 54 (28 bit)
access : read-only


STATUS2_REG

DCDC Second Status Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS2_REG STATUS2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_CUR_LIM DCDC_VDD_CUR_LIM DCDC_V18_CUR_LIM DCDC_V18P_CUR_LIM

DCDC_V14_CUR_LIM : Actual V14 current limit
bits : 0 - 4 (5 bit)
access : read-only

DCDC_VDD_CUR_LIM : Actual VDD current limit
bits : 5 - 14 (10 bit)
access : read-only

DCDC_V18_CUR_LIM : Actual V18 current limit
bits : 16 - 36 (21 bit)
access : read-only

DCDC_V18P_CUR_LIM : Actual V18P current limit
bits : 21 - 46 (26 bit)
access : read-only


STATUS3_REG

DCDC Third Status Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS3_REG STATUS3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_N_COMP_TRIM DCDC_VDD_N_COMP_TRIM DCDC_V18_N_COMP_TRIM DCDC_V18P_N_COMP_TRIM

DCDC_V14_N_COMP_TRIM : Actual V14 N side comparator trim value
bits : 0 - 5 (6 bit)
access : read-only

DCDC_VDD_N_COMP_TRIM : Actual VDD N side comparator trim value
bits : 6 - 17 (12 bit)
access : read-only

DCDC_V18_N_COMP_TRIM : Actual V18 N side comparator trim value
bits : 16 - 37 (22 bit)
access : read-only

DCDC_V18P_N_COMP_TRIM : Actual V18P N side comparator trim value
bits : 22 - 49 (28 bit)
access : read-only


STATUS4_REG

DCDC Fourth Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUS4_REG STATUS4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_CHARGE_REG_0 DCDC_CHARGE_REG_1 DCDC_CHARGE_REG_2 DCDC_CHARGE_REG_3

DCDC_CHARGE_REG_0 : Charge register position 0
bits : 0 - 2 (3 bit)
access : read-only

DCDC_CHARGE_REG_1 : Charge register position 1
bits : 3 - 8 (6 bit)
access : read-only

DCDC_CHARGE_REG_2 : Charge register position 2
bits : 6 - 14 (9 bit)
access : read-only

DCDC_CHARGE_REG_3 : Charge register position 3
bits : 9 - 20 (12 bit)
access : read-only


IRQ_STATUS_REG

DCDC Interrupt Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_STATUS_REG IRQ_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_STATUS DCDC_V18_TIMEOUT_IRQ_STATUS DCDC_VDD_TIMEOUT_IRQ_STATUS DCDC_V18P_TIMEOUT_IRQ_STATUS DCDC_LOW_VBAT_IRQ_STATUS

DCDC_V14_TIMEOUT_IRQ_STATUS : Timeout occured on V14 output
bits : 0 - 0 (1 bit)
access : read-only

DCDC_V18_TIMEOUT_IRQ_STATUS : Timeout occured on V18 output
bits : 1 - 2 (2 bit)
access : read-only

DCDC_VDD_TIMEOUT_IRQ_STATUS : Timeout occured on VDD output
bits : 2 - 4 (3 bit)
access : read-only

DCDC_V18P_TIMEOUT_IRQ_STATUS : Timeout occured on V18P output
bits : 3 - 6 (4 bit)
access : read-only

DCDC_LOW_VBAT_IRQ_STATUS : Low VBAT detector triggered (battery voltage below 2.5 V)
bits : 4 - 8 (5 bit)
access : read-only


IRQ_CLEAR_REG

DCDC Interrupt Clear Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_CLEAR_REG IRQ_CLEAR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_CLEAR DCDC_V18_TIMEOUT_IRQ_CLEAR DCDC_VDD_TIMEOUT_IRQ_CLEAR DCDC_V18P_TIMEOUT_IRQ_CLEAR DCDC_LOW_VBAT_IRQ_CLEAR

DCDC_V14_TIMEOUT_IRQ_CLEAR : Clear V14 timeout interrupt
bits : 0 - 0 (1 bit)
access : write-only

DCDC_V18_TIMEOUT_IRQ_CLEAR : Clear V18 timeout interrupt
bits : 1 - 2 (2 bit)
access : write-only

DCDC_VDD_TIMEOUT_IRQ_CLEAR : Clear VDD timeout interrupt
bits : 2 - 4 (3 bit)
access : write-only

DCDC_V18P_TIMEOUT_IRQ_CLEAR : Clear V18P timeout interrupt
bits : 3 - 6 (4 bit)
access : write-only

DCDC_LOW_VBAT_IRQ_CLEAR : Clear low VBAT interrupt
bits : 4 - 8 (5 bit)
access : write-only


IRQ_MASK_REG

DCDC Interrupt Mask Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQ_MASK_REG IRQ_MASK_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_TIMEOUT_IRQ_MASK DCDC_V18_TIMEOUT_IRQ_MASK DCDC_VDD_TIMEOUT_IRQ_MASK DCDC_V18P_TIMEOUT_IRQ_MASK DCDC_LOW_VBAT_IRQ_MASK

DCDC_V14_TIMEOUT_IRQ_MASK : Mask V14 timeout interrupt
bits : 0 - 0 (1 bit)
access : read-write

DCDC_V18_TIMEOUT_IRQ_MASK : Mask V18 timeout interrupt
bits : 1 - 2 (2 bit)
access : read-write

DCDC_VDD_TIMEOUT_IRQ_MASK : Mask VDD timeout interrupt
bits : 2 - 4 (3 bit)
access : read-write

DCDC_V18P_TIMEOUT_IRQ_MASK : Mask V18P timeout interrupt
bits : 3 - 6 (4 bit)
access : read-write

DCDC_LOW_VBAT_IRQ_MASK : Mask low VBAT interrupt
bits : 4 - 8 (5 bit)
access : read-write


CTRL1_REG

DCDC First Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1_REG CTRL1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_ENABLE DCDC_FW_ENABLE DCDC_PRIORITY DCDC_IDLE_CLK_DIV DCDC_AUTO_LV_MODE DCDC_MAN_LV_MODE DCDC_FAST_STARTUP DCDC_SW_TIMEOUT DCDC_IDLE_MAX_FAST_DOWNRAMP DCDC_STARTUP_DELAY DCDC_SH_ENABLE

DCDC_ENABLE : Enable setting for DCDC converter
bits : 0 - 0 (1 bit)
access : read-write

DCDC_FW_ENABLE : Freewheel switch enable
bits : 1 - 2 (2 bit)
access : read-write

DCDC_PRIORITY : Charge priority register (4x 2 bit ID) Charge sequence is [1:0] > [3:2] > [5:4] > [7:6] V14 = 00 V18 = 01 VDD = 10 V18P = 11
bits : 2 - 11 (10 bit)
access : read-write

DCDC_IDLE_CLK_DIV : Idle Clock Divider 00 = 2 01 = 4 10 = 8 11 = 16
bits : 10 - 21 (12 bit)
access : read-write

DCDC_AUTO_LV_MODE : Switches to low voltage settings when battery voltage drops below 2.5 V
bits : 12 - 24 (13 bit)
access : read-write

DCDC_MAN_LV_MODE : Manually activates low voltage settings
bits : 13 - 26 (14 bit)
access : read-write

DCDC_FAST_STARTUP : Set current limit to maximum during initial startup
bits : 14 - 28 (15 bit)
access : read-write

DCDC_SW_TIMEOUT : P and N switch timeout, if switch is closed longer than this a timeout is generated and the FSM is forced to the next state Writing 0 disables timeout functionality 62.5 - 1937.5 ns, 62.5 ns step size
bits : 15 - 34 (20 bit)
access : read-write

DCDC_IDLE_MAX_FAST_DOWNRAMP : Maximum output idle time for fast current limit downramping. 0 - 7875 ns, 125 ns step size
bits : 20 - 45 (26 bit)
access : read-write

DCDC_STARTUP_DELAY : Delay between turning bias on and converter becoming active 0 - 31 us, 1 us step size
bits : 26 - 56 (31 bit)
access : read-write

DCDC_SH_ENABLE : Enables sample and hold circuit in output comparators.
bits : 31 - 62 (32 bit)
access : read-write


CTRL2_REG

DCDC Second Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2_REG CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_HSGND_TRIM DCDC_LSSUP_TRIM DCDC_VBTSTRP_TRIM DCDC_SLOPE_CONTROL DCDC_TIMEOUT_IRQ_RES DCDC_TIMEOUT_IRQ_TRIG DCDC_N_COMP_TRIM_VAL DCDC_N_COMP_TRIM_MAN DCDC_V_NOK_CNT_MAX

DCDC_HSGND_TRIM : Trim high side ground V = VBAT - (2 V + 400 mV * N)
bits : 0 - 1 (2 bit)
access : read-write

DCDC_LSSUP_TRIM : Trim low side supply voltage V = 2 V + 300 mV * N
bits : 2 - 5 (4 bit)
access : read-write

DCDC_VBTSTRP_TRIM : Trim bootstrap voltage V = 1.6 V + 100 mV * N
bits : 4 - 9 (6 bit)
access : read-write

DCDC_SLOPE_CONTROL : Sets strength of N and P switch drivers
bits : 6 - 13 (8 bit)
access : read-write

DCDC_TIMEOUT_IRQ_RES : Number of successive non-timed out charge events required to clear timeout event counter
bits : 8 - 19 (12 bit)
access : read-write

DCDC_TIMEOUT_IRQ_TRIG : Number of timeout events before timeout interrupt is generated
bits : 12 - 27 (16 bit)
access : read-write

DCDC_N_COMP_TRIM_VAL : Manual trim value for N side comparator Signed magnitude representation 011111 = +13 mV 000000 = 100000 = -22 mV 111111 = -56 mV
bits : 16 - 37 (22 bit)
access : read-write

DCDC_N_COMP_TRIM_MAN : Enables manual trimming for N side comparator
bits : 22 - 44 (23 bit)
access : read-write

DCDC_V_NOK_CNT_MAX : Maximum number of V_NOK events on an output before V_AVAILABLE is reset
bits : 24 - 51 (28 bit)
access : read-write


V14_REG

DCDC V14 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

V14_REG V14_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCDC_V14_ENABLE_LV DCDC_V14_ENABLE_HV DCDC_V14_IDLE_MIN DCDC_V14_IDLE_HYST DCDC_V14_CUR_LIM_MIN DCDC_V14_CUR_LIM_MAX_LV DCDC_V14_CUR_LIM_MAX_HV DCDC_V14_TRIM DCDC_V14_FAST_RAMPING

DCDC_V14_ENABLE_LV : Output enable (low battery voltage mode) 0 = Disabled 1 = Enabled
bits : 0 - 0 (1 bit)
access : read-write

DCDC_V14_ENABLE_HV : Output enable (high battery voltage mode) 0 = Disabled 1 = Enabled
bits : 1 - 2 (2 bit)
access : read-write

DCDC_V14_IDLE_MIN : Minimum idle time 0 - 3875 ns, 125 ns step size Minimum idle time, CUR_LIM is increased if this limit is not reached
bits : 2 - 8 (7 bit)
access : read-write

DCDC_V14_IDLE_HYST : Idle time hysteresis 0 - 3875 ns, 125 ns step size IDLE_MAX = IDLE_MIN + IDLE_HYST Maximum idle time before decreasing CUR_LIM
bits : 7 - 18 (12 bit)
access : read-write

DCDC_V14_CUR_LIM_MIN : Minimum current limit I = 30 mA * (1 + N)
bits : 12 - 28 (17 bit)
access : read-write

DCDC_V14_CUR_LIM_MAX_LV : Maximum current limit (low battery voltage mode) I = 30 mA * (1 + N)
bits : 17 - 38 (22 bit)
access : read-write

DCDC_V14_CUR_LIM_MAX_HV : Mximum current limit (high battery voltage mode) I = 30 mA * (1 + N)
bits : 22 - 48 (27 bit)
access : read-write

DCDC_V14_TRIM : Output voltage trim Steps of 25 mV
bits : 27 - 54 (28 bit)
access : read-write

DCDC_V14_FAST_RAMPING : Fast current ramping (improves response time at the cost of more ripple)
bits : 31 - 62 (32 bit)
access : read-write



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