Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x110 byte (0x0)
mem_usage : registers
protection :
Start address A of DMA channel 0
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Control register for the DMA channel 0
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
DMA channel assignments
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA01_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 0 and the second on channel 1. 0x0: SPI_rx / SPI_tx 0x1: SPI2_rx / SPI2_tx 0x2: UART_rx / UART_tx 0x3: UART2_rx / UART2_tx 0x4: I2C_rx / I2C_tx 0x5: I2C2_rx / I2C2_tx 0x6: USB_rx / USB_tx 0x7: UART3_rx/UART3_tx 0x8: PCM_rx / PCM_tx 0x9: SRC_out / SRC_in (for all the supported conversions) 0xA: Reserved 0xB: Reserved 0xC: GP_ADC / - 0xD: SD_ADC / - 0xE: Reserved 0xF: None Note: If any of the four available peripheral selector fields (DMA01_SEL, DMA23_SEL, DMA45_SEL, DMA67_SEL) have the same value, the lesser significant selector has higher priority and will control the DMA acknowledge signal driven to the selected peripheral. Hence, if DMA01_SEL = DMA23_SEL, the channels 0 and 1 will provide the Rx and Tx DMA acknowledge signals for the selected peripheral. Consequently, it is suggested to assign the intended peripheral value to a unique selector field.
bits : 0 - 3 (4 bit)
access : read-write
DMA23_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 2 and the second on channel 3. See DMA01_SEL for the peripherals' mapping.
bits : 4 - 11 (8 bit)
access : read-write
DMA45_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 4 and the second on channel 5. See DMA01_SEL for the peripherals' mapping.
bits : 8 - 19 (12 bit)
access : read-write
DMA67_SEL : Select which combination of peripherals are mapped on the DMA channels. The peripherals are mapped as pairs on two channels. Here, the first DMA request is mapped on channel 6 and the second on channel 7. See DMA01_SEL for the peripheral mapping.
bits : 12 - 27 (16 bit)
access : read-write
DMA interrupt status register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_IRQ_CH0 : 0 = IRQ on channel 0 is not set 1 = IRQ on channel 0 is set
bits : 0 - 0 (1 bit)
access : read-only
DMA_IRQ_CH1 : 0 = IRQ on channel 1 is not set 1 = IRQ on channel 1 is set
bits : 1 - 2 (2 bit)
access : read-only
DMA_IRQ_CH2 : 0 = IRQ on channel 2 is not set 1 = IRQ on channel 2 is set
bits : 2 - 4 (3 bit)
access : read-only
DMA_IRQ_CH3 : 0 = IRQ on channel 3 is not set 1 = IRQ on channel 3 is set
bits : 3 - 6 (4 bit)
access : read-only
DMA_IRQ_CH4 : 0 = IRQ on channel 4 is not set 1 = IRQ on channel 4 is set
bits : 4 - 8 (5 bit)
access : read-only
DMA_IRQ_CH5 : 0 = IRQ on channel 5 is not set 1 = IRQ on channel 5 is set
bits : 5 - 10 (6 bit)
access : read-only
DMA_IRQ_CH6 : 0 = IRQ on channel 6 is not set 1 = IRQ on channel 6 is set
bits : 6 - 12 (7 bit)
access : read-only
DMA_IRQ_CH7 : 0 = IRQ on channel 7 is not set 1 = IRQ on channel 7 is set
bits : 7 - 14 (8 bit)
access : read-only
DMA_BUS_ERR0 : 0 = No bus error response is detected for channel 0 1 = Bus error response detected for channel 0 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 8 - 16 (9 bit)
access : read-only
DMA_BUS_ERR1 : 0 = No bus error response is detected for channel 1 1 = Bus error response detected for channel 1 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 9 - 18 (10 bit)
access : read-only
DMA_BUS_ERR2 : 0 = No bus error response is detected for channel 2 1 = Bus error response detected for channel 2 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 10 - 20 (11 bit)
access : read-only
DMA_BUS_ERR3 : 0 = No bus error response is detected for channel 3 1 = Bus error response detected for channel 3 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 11 - 22 (12 bit)
access : read-only
DMA_BUS_ERR4 : 0 = No bus error response is detected for channel 4 1 = Bus error response detected for channel 4 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 12 - 24 (13 bit)
access : read-only
DMA_BUS_ERR5 : 0 = No bus error response is detected for channel 5 1 = Bus error response detected for channel 5 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 13 - 26 (14 bit)
access : read-only
DMA_BUS_ERR6 : 0 = No bus error response is detected for channel 6 1 = Bus error response detected for channel 6 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.
bits : 14 - 28 (15 bit)
access : read-only
DMA_BUS_ERR7 : 0 = No bus error response is detected for channel 7 1 = Bus error response detected for channel 7 NOTE: This bit-field is auto-clear and it is initialized to '0' as soon as a new transfer is started.It is also noted that when the specific channel becomes secure (so when either of the PROT_AES_KEY_READ and PROT_QSPI_KEY_READ bits of SECURE_BOOT_REG is set), this bit-field is overruled to '0', masking the bus error status reporting to the user.
bits : 15 - 30 (16 bit)
access : read-only
DMA clear interrupt register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_RST_IRQ_CH0 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 0 writing a 0 will have no effect
bits : 0 - 0 (1 bit)
access : write-only
DMA_RST_IRQ_CH1 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 1 writing a 0 will have no effect
bits : 1 - 2 (2 bit)
access : write-only
DMA_RST_IRQ_CH2 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 2 writing a 0 will have no effect
bits : 2 - 4 (3 bit)
access : write-only
DMA_RST_IRQ_CH3 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 3 writing a 0 will have no effect
bits : 3 - 6 (4 bit)
access : write-only
DMA_RST_IRQ_CH4 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 4 writing a 0 will have no effect
bits : 4 - 8 (5 bit)
access : write-only
DMA_RST_IRQ_CH5 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 5 writing a 0 will have no effect
bits : 5 - 10 (6 bit)
access : write-only
DMA_RST_IRQ_CH6 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 6 writing a 0 will have no effect
bits : 6 - 12 (7 bit)
access : write-only
DMA_RST_IRQ_CH7 : Writing a 1 will reset the status bit of DMA_INT_STATUS_REG for channel 7 writing a 0 will have no effect
bits : 7 - 14 (8 bit)
access : write-only
DMA Interrupt mask register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_IRQ_ENABLE0 : 0 = disable interrupts on channel 0 1 = enable interrupts on channel 0
bits : 0 - 0 (1 bit)
access : read-write
DMA_IRQ_ENABLE1 : 0 = disable interrupts on channel 1 1 = enable interrupts on channel 1
bits : 1 - 2 (2 bit)
access : read-write
DMA_IRQ_ENABLE2 : 0 = disable interrupts on channel 2 1 = enable interrupts on channel 2
bits : 2 - 4 (3 bit)
access : read-write
DMA_IRQ_ENABLE3 : 0 = disable interrupts on channel 3 1 = enable interrupts on channel 3
bits : 3 - 6 (4 bit)
access : read-write
DMA_IRQ_ENABLE4 : 0 = disable interrupts on channel 4 1 = enable interrupts on channel 4
bits : 4 - 8 (5 bit)
access : read-write
DMA_IRQ_ENABLE5 : 0 = disable interrupts on channel 5 1 = enable interrupts on channel 5
bits : 5 - 10 (6 bit)
access : read-write
DMA_IRQ_ENABLE6 : 0 = disable interrupts on channel 6 1 = enable interrupts on channel 6
bits : 6 - 12 (7 bit)
access : read-write
DMA_IRQ_ENABLE7 : 0 = disable interrupts on channel 7 1 = enable interrupts on channel 7
bits : 7 - 14 (8 bit)
access : read-write
Index value of DMA channel 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
Start address A of DMA channel 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 1
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA1_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
Start address B of DMA channel 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
Start address A of DMA channel 2
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA2_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 2
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA2_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 2
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA2_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 2
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA2_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 2
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address 0 = do not increment 1 = increment according value of BW
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 2
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA2_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
Start address A of DMA channel 3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA3_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA3_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA3_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 3
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA3_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 3
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 3
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA3_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
DMA receive interrupt register channel 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
Start address A of DMA channel 4
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA4_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 4
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA4_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 4
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA4_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 4
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA4_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 4
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 4
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA4_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
Start address A of DMA channel 5
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA5_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 5
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA5_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 5
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA5_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 5
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA5_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 5
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 5
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA5_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
DMA receive length register channel 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA0_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Start address A of DMA channel 6
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA6_A_START : Source start address
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 6
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA6_B_START : Destination start address
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 6
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA6_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 6
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA6_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 6
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG)
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care.
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'.
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 6
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA6_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
Start address A of DMA channel 7
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA7_A_START : Source start address NOTE: See also the DMA chapter of the Datasheet for the allowed range of the DMA7 channel's source address in Secure Boot mode.
bits : 0 - 31 (32 bit)
access : read-write
Start address B of DMA channel 7
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA7_B_START : Destination start address NOTE: See also the DMA chapter of the Datasheet for the allowed range of the DMA7 channel's destination address in Secure Boot mode.
bits : 0 - 31 (32 bit)
access : read-write
DMA receive interrupt register channel 7
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA7_INT : Number of transfers until an interrupt is generated. The interrupt is generated after a transfer, if DMAx_INT_REG is equal to DMAx_IDX_REG and before DMAx_IDX_REG is incremented. The bit-field IRQ_ENABLE of DMAx_CTRL_REG must be set to '1' to let the controller generate the interrupt.
bits : 0 - 15 (16 bit)
access : read-write
DMA receive length register channel 7
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA7_LEN : DMA channel's transfer length. DMAx_LEN of value 0, 1, 2, ... results into an actual transfer length of 1, 2, 3, ...
bits : 0 - 15 (16 bit)
access : read-write
Control register for the DMA channel 7
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA_ON : 0 = DMA channel is off, clocks are disabled 1 = DMA channel is enabled. This bit will be automatically cleared after the completion of a transfer, if circular mode is not enabled. In circular mode, this bit stays set. Note: If DMA_ON is disabled by SW while the DMA channel is active, it cannot be enabled again until the channel has completed the last on-going read-write cycle and has stopped. Thus, the SW has to check that the reading of DMAx_CTRL_REG.DMA_ON returns 0, before setting again the specific bit-field.
bits : 0 - 0 (1 bit)
access : read-write
BW : Bus transfer width: 00 = 1 Byte (suggested for peripherals like UART and 8-bit SPI) 01 = 2 Bytes (suggested for peripherals like I2C and 16-bit SPI) 10 = 4 Bytes (suggested for Memory-to-Memory transfers) 11 = Reserved NOTE: This bit-field is overruled to 10 when channel DMA7 is configured as trusted channel (in Secure Boot mode).
bits : 1 - 3 (3 bit)
access : read-write
DREQ_MODE : 0 = DMA channel starts immediately 1 = DMA channel must be triggered by peripheral DMA request (see also the description of DMA_REQ_MUX_REG) *NOTE: This bit-field is overruled to '0' when channel DMA7 is configured as trusted channel (in Secure Boot mode).
bits : 3 - 6 (4 bit)
access : read-write
BINC : Enable increment of destination address. 0 = do not increment (destination address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 4 - 8 (5 bit)
access : read-write
AINC : Enable increment of source address. 0 = do not increment (source address stays the same during the transfer) 1 = increment according to the value of BW bit-field (by 1, when BW= 00 by 2, when BW= 01 by 4, when BW= 10 )
bits : 5 - 10 (6 bit)
access : read-write
CIRCULAR : 0 = Normal mode. The DMA channel stops after having completed the transfer of length determined by DMAx_LEN_REG. DMA_ON automatically deasserts when the transfer is completed. 1 = Circular mode (applicable only if DREQ_MODE = '1'). In this mode, DMA_ON never deasserts, as the DMA channel automatically resets DMAx_IDX_REG and starts a new transfer.
bits : 6 - 12 (7 bit)
access : read-write
DMA_PRIO : The priority level determines which DMA channel will be granted access for transferring data, in case more than one channels are active and request the bus at the same time. The greater the value, the higher the priority. In specific: 000 = lowest priority 111 = highest priority If different channels with equal priority level values request the bus at the same time, an inherent priority mechanism is applied. According to this mechanism, if, for example, both the DMA0 and DMA1 channels have the same priority level, then DMA0 will first be granted access to the bus.
bits : 7 - 16 (10 bit)
access : read-write
DMA_IDLE : 0 = Blocking mode, the DMA performs a fast back-to-back copy, disabling bus access for any bus master with lower priority. 1 = Interrupting mode, the DMA inserts a wait cycle after each store allowing the CPU to steal cycles or cache to perform a burst read. If DREQ_MODE='1', DMA_IDLE is don't care. *NOTE: This bit-field is overruled to '0' when the DMA7 channel is configured as trusted channel (in Secure Boot mode).
bits : 10 - 20 (11 bit)
access : read-write
DMA_INIT : 0 = DMA performs copy A1 to B1, A2 to B2, etc ... 1 = DMA performs copy of A1 to B1, B2, etc ... This feature is useful for memory initialization to any value. Thus, BINC must be set to '1', while AINC is don't care, as only one fetch from A is done. This process cannot be interrupted by other DMA channels. It is also noted that DMA_INIT should not be used when DREQ_MODE='1'. NOTE: This bit-field is overruled to '0' when the DMA7 channel is configured as trusted channel (in Secure Boot mode).
bits : 11 - 22 (12 bit)
access : read-write
REQ_SENSE : 0 = DMA operates with level-sensitive peripheral requests (default) 1 = DMA operates with (positive) edge-sensitive peripheral requests
bits : 12 - 24 (13 bit)
access : read-write
BURST_MODE : Enables the DMA read/write bursts, according to the following configuration: 00 = Bursts are disabled 01 = Bursts of 4 are enabled 10 = Bursts of 8 are enabled 11 = Reserved
bits : 13 - 27 (15 bit)
access : read-write
BUS_ERROR_DETECT : 0 = Ignores bus error response from the AHB bus, so DMA continues normally. 1 = Detects the bus response and tracks any bus error may occur during the transfer. If a bus error is detected, the channel completes the current read-write DMA cycle (either in burst or single transfers mode) and then closes the transfer, de-asserting DMA_ON bit automatically. It is noted that the respective bus error detection status bit of DMA_INT_STATUS_REG is automatically cleared as soon as the channel is switched-on again, in order to perform a new transfer. NOTE: In secure boot mode, the bus error detection mode of DMA7 channel is always enabled, overruling the specific bit-field's programmed value.
bits : 15 - 30 (16 bit)
access : read-write
Index value of DMA channel 7
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DMA7_IDX : This (read-only) register determines the data items already transferred by the DMA channel. Hence, if its value is 1, then the DMA channel has already copied one data item and it is currently performing the next copy. If its value is 2, then two items have already been copied and so on. When the transfer is completed (so when DMAx_CTRL_REG.DMA_ON has been cleared) and DMAx_CTRL_REG.CIRCULAR is not set, the register keeps its (last) value (which should be equal to DMAx_LEN_REG) and it is automatically reset to 0 upon starting a new transfer. In CIRCULAR mode, the register is automatically initialized to 0 as soon as the DMA channel starts-over again.
bits : 0 - 15 (16 bit)
access : read-only
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