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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x94 byte (0x0)
mem_usage : registers
protection :

Registers

AHB_DMA_PL1_REG

AHB_DMA_PL2_REG

AHB_DMA_DFLT_MASTER_REG

AHB_DMA_WTEN_REG

AHB_DMA_TCL_REG

AHB_DMA_CCLM1_REG

AHB_DMA_CCLM2_REG

AHB_DMA_CCLM3_REG

AHB_DMA_CCLM4_REG

AHB_DMA_PL3_REG

AHB_DMA_VERSION_REG

AHB_DMA_PL4_REG


AHB_DMA_PL1_REG

AHB-DMA layer priority level for RFTP (AHB DMA layer only)
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_PL1_REG AHB_DMA_PL1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_PL1

AHB_DMA_PL1 : Arbitration priority for master RFPT. 0: lowest, 15: highest.
bits : 0 - 3 (4 bit)
access : read-write


AHB_DMA_PL2_REG

AHB-DMA layer priority level for LCD (AHB DMA layer only)
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_PL2_REG AHB_DMA_PL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_PL2

AHB_DMA_PL2 : Arbitration priority for master LCD. 0: lowest, 15: highest.
bits : 0 - 3 (4 bit)
access : read-write


AHB_DMA_DFLT_MASTER_REG

Default master ID number (AHB DMA layer only)
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_DFLT_MASTER_REG AHB_DMA_DFLT_MASTER_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_DFLT_MASTER

AHB_DMA_DFLT_MASTER : Default master ID number register. The default master is the master that is granted by the bus when no master has requested ownership. 0: Dummy master 1: RFPT 2: LCD 3: GEN-DMA 3: CRYPTO-DMA
bits : 0 - 3 (4 bit)
access : read-write


AHB_DMA_WTEN_REG

Weighted-Token Arbitration Scheme Enable (AHB DMA layer only)
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_WTEN_REG AHB_DMA_WTEN_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_WTEN

AHB_DMA_WTEN : Weighted-token arbitration scheme enable.
bits : 0 - 0 (1 bit)
access : read-write


AHB_DMA_TCL_REG

Master clock refresh period (AHB DMA layer only)
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_TCL_REG AHB_DMA_TCL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_TCL

AHB_DMA_TCL : Master clock refresh period, counting clock cycles. An arbitration period is defined over this number of tokens. When a new arbitration period starts, the master counters are reloaded. Recommended value is the sum of the AHB_DMA_CCLMx_REG valuesplus 2 tokens for each master, i.e. plus 6.
bits : 0 - 15 (16 bit)
access : read-write


AHB_DMA_CCLM1_REG

USB Master clock tokens (AHB DMA layer only)
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_CCLM1_REG AHB_DMA_CCLM1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_CCLM

AHB_DMA_CCLM : Number of tokens (counted in AHB clock cycles) that a master can use on the bus before it has to arbitrate on a bus master with low priority and having tokens. Masters with tokens remaining have priority over masters that have used all of their tokens. User should configure all the token values ensuring that the sum does not exceeds the total allocated number of tokens. If a value of zero is configured, then the bus is deemed to have infinite tokens and will always operate in the upper-tier of arbitration.
bits : 0 - 15 (16 bit)
access : read-write


AHB_DMA_CCLM2_REG

GenDMA Master clock tokens (AHB DMA layer only)
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_CCLM2_REG AHB_DMA_CCLM2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_CCLM

AHB_DMA_CCLM : Refer to AHB_DMA_CCLM1_REG
bits : 0 - 15 (16 bit)
access : read-write


AHB_DMA_CCLM3_REG

CRYPTO Master clock tokens (AHB DMA layer only)
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_CCLM3_REG AHB_DMA_CCLM3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_CCLM

AHB_DMA_CCLM : AHB_DMA_CCLM1_REG
bits : 0 - 15 (16 bit)
access : read-write


AHB_DMA_CCLM4_REG

CRYPTO Master clock tokens (AHB DMA layer only)
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_CCLM4_REG AHB_DMA_CCLM4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_CCLM

AHB_DMA_CCLM : AHB_DMA_CCLM1_REG
bits : 0 - 15 (16 bit)
access : read-write


AHB_DMA_PL3_REG

AHB-DMA layer Priority level for GEN-DMA (AHB DMA layer only)
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_PL3_REG AHB_DMA_PL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_PL3

AHB_DMA_PL3 : Arbitration priority for master GEN-DMA. 0: lowest, 15: highest.
bits : 0 - 3 (4 bit)
access : read-write


AHB_DMA_VERSION_REG

Version ID (AHB DMA layer only)
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_VERSION_REG AHB_DMA_VERSION_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_VERSION

AHB_DMA_VERSION :
bits : 0 - 31 (32 bit)
access : read-only


AHB_DMA_PL4_REG

AHB-DMA layer Priority level for CRYPTO-DMA (AHB DMA layer only)
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AHB_DMA_PL4_REG AHB_DMA_PL4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_DMA_PL4

AHB_DMA_PL4 : Arbitration priority for master CRYPTO-DMA. 0: lowest, 15: highest.
bits : 0 - 3 (4 bit)
access : read-write



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