GP_ADC_CTRL_REG

GP_ADC_OFFN_REG

GP_ADC_CLEAR_INT_REG

GP_ADC_RESULT_REG

GP_ADC_CTRL2_REG

GP_ADC_CTRL3_REG

GP_ADC_OFFP_REG

GP_ADC_EN : 0: LDO is off and ADC is disabled.. 1: LDO is turned on and afterwards the ADC is enabled.
bits : 0 - 0 (1 bit)
access : read-write

GP_ADC_START : 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero.
bits : 1 - 2 (2 bit)
access : read-write

GP_ADC_CONT : 0: Manual ADC mode, a single result will be generated after setting the GP_ADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in GP_ADC_RESULT_REG. Still GP_ADC_START has to be set to start the execution. The time between conversions is configurable with GP_ADC_INTERVAL.
bits : 2 - 4 (3 bit)
access : read-write

GP_ADC_CLK_SEL : 0: Internal high-speed ADC clock used (recommended). 1: Digital clock used (ADC_CLK).
bits : 3 - 6 (4 bit)
access : read-write

GP_ADC_INT : 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to GP_ADC_CLEAR_INT_REG.
bits : 4 - 8 (5 bit)
access : read-only

GP_ADC_MINT : 0: Disable (mask) GP_ADC_INT. 1: Enable GP_ADC_INT to ICU.
bits : 5 - 10 (6 bit)
access : read-write

GP_ADC_SE : 0: Differential mode 1: Single ended mode
bits : 6 - 12 (7 bit)
access : read-write

GP_ADC_MUTE : 0: Normal operation 1: Mute ADC input. Takes sample at mid-scale (to dertermine the internal offset and/or noise of the ADC with regards to VDD_REF which is also sampled by the ADC).
bits : 7 - 14 (8 bit)
access : read-write

GP_ADC_SEL : ADC input selection. If GP_ADC_SE = 1 (single ended mode): 0: GP ADC0 (P1_09) 1: GP ADC1 (P0_25) 2: GP ADC2 (P0_08) 3: MUX ( CH 21:16)] 4: VDDD ( internal) 5: V30 (GP_ADC_ATTN3X scaler automatically selected) 6: V30 (GP_ADC_ATTN3X scaler automatically selected) 7: DCDC (GP_ADC_ATTN3X scaler automatically selected) 8: VBAT (5V to 1.2V scaler selected) 9: VSSA 10: Radio Test Out<0> 11 :Radio Test Out<1> 12: Radio Test In<0> 13: Radio Test In<1> 14: 3V3 Testbus 15: 1V2 Testbus 16: GP ADC3 (P0_09) 17: GP ADC4 (P1_13) 18: GP ADC5 (P1_12) 19: GP ADC6 (P1_18) 20: GP ADC7 (P1_19) 21: Diff Temperature sensor, See GP_ADC_DIFF_TEMP_SEL All other combinations are reserved. If GP_ADC_SE = 0 (differential mode): 0: P1[09] vs P0[25] All other combinations are P0[08] vs P0[09].
bits : 8 - 20 (13 bit)
access : read-write

GP_ADC_SIGN : 0: Default 1: Conversion with opposite sign at input and output to cancel out the internal offset of the ADC and low-frequency
bits : 13 - 26 (14 bit)
access : read-write

GP_ADC_CHOP : 0: Chopper mode off 1: Chopper mode enabled. Takes two samples with opposite GP_ADC_SIGN to cancel the internal offset voltage of the ADC Highly recommended for DC-measurements.
bits : 14 - 28 (15 bit)
access : read-write

GP_ADC_LDO_ZERO : 1: Samples and disconnects VREF, should be refreshed frequently. Note that the LDO consumpes power when bit is set.
bits : 15 - 30 (16 bit)
access : read-write

GP_ADC_DIFF_TEMP_SEL : 0= Gnd, 1 =sensor near radio, 2 =sensor near charger, 3 =sensor near bandgap with sensors disabled (GP_ADC_DIFF_TEMP_EN = 0) :0 = GND 1 = Z, 2= V(ntc) from charger, 3 = V(temp) from charger
bits : 16 - 33 (18 bit)
access : read-write

GP_ADC_DIFF_TEMP_EN : 1: Enable the on-chip temperature sensors
bits : 18 - 36 (19 bit)
access : read-write

GP_ADC_OFFN : Offset adjust of 'negative' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=1 )
bits : 0 - 9 (10 bit)
access : read-write

GP_ADC_CLR_INT : Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0.
bits : 0 - 15 (16 bit)
access : write-only

GP_ADC_VAL : Returns the 10 up to 16 bits linear value of the last AD conversion. The upper 10 bits are always valid, the lower 6 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 64 samples results in six extra bits.
bits : 0 - 15 (16 bit)
access : read-only

GP_ADC_ATTN3X : 0: Input voltages up to 1.2V allowed. 1: Input voltages up to 3.6V allowed by enabling 3x attenuator. (if ADC_SEL=7 or 8, this bit is automatically set to 1) Enabling the attenuator requires a longer sampling time.
bits : 0 - 0 (1 bit)
access : read-write

GP_ADC_IDYN : 1: Enables dynamic load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
bits : 1 - 2 (2 bit)
access : read-write

GP_ADC_I20U : 1: Adds 20uA constant load current at the ADC LDO to minimize ripple on the reference voltage of the ADC.
bits : 2 - 4 (3 bit)
access : read-write

GP_ADC_DMA_EN : 0: DMA functionality disabled 1: DMA functionality enabled
bits : 3 - 6 (4 bit)
access : read-write

GP_ADC_CONV_NRS : 0: 1 sample is taken or 2 in case ADC_CHOP is active. 1: 2 samples are taken. 2: 4 samples are taken. 7: 128 samples are taken.
bits : 5 - 12 (8 bit)
access : read-write

GP_ADC_SMPL_TIME : 0: The sample time (switch is closed) is one ADC_CLK cycle 1: The sample time is 1*32 ADC_CLK cycles 2: The sample time is 2*32 ADC_CLK cycles 15: The sample time is 15*32 ADC_CLK cycles
bits : 8 - 19 (12 bit)
access : read-write

GP_ADC_STORE_DEL : 0: Data is stored after handshake synchronisation 1: Data is stored two ADC_CLK cycles after internal start trigger 15: Data is stored sixteen ADC_CLK cycles after internal start trigger
bits : 12 - 27 (16 bit)
access : read-write

GP_ADC_EN_DEL : Defines the delay for enabling the ADC after enabling the LDO. 0: Not allowed 1: 32x ADC_CLK period. n: n*32x ADC_CLK period.
bits : 0 - 7 (8 bit)
access : read-write

GP_ADC_INTERVAL : Defines the interval between two ADC conversions in case GP_ADC_CONT is set. 0: No extra delay between two conversions. 1: 1.024ms interval between two conversions. 2: 2.048ms interval between two conversions. 255: 261.12ms interval between two conversions.
bits : 8 - 23 (16 bit)
access : read-write

GP_ADC_OFFP : Offset adjust of 'positive' array of ADC-network (effective if GP_ADC_SE=0 , or GP_ADC_SE=1 AND GP_ADC_SIGN=0 )
bits : 0 - 9 (10 bit)
access : read-write