\n
address_offset : 0x0 Bytes (0x0)
size : 0x104 byte (0x0)
mem_usage : registers
protection :
P0 Data input / output Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_DATA : Set P0 output register when written Returns the value of P0 port when read
bits : 0 - 31 (32 bit)
access : read-write
P0 Reset port pins Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_RESET : Writing a 1 to P0[y] sets P0[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 31 (32 bit)
access : write-only
Weak Pads Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_06_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_06 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 0 - 0 (1 bit)
access : read-write
P0_07_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_07 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 1 - 2 (2 bit)
access : read-write
P0_16_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_16 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 2 - 4 (3 bit)
access : read-write
P0_17_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_17 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 3 - 6 (4 bit)
access : read-write
P0_18_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_18 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 4 - 8 (5 bit)
access : read-write
P0_25_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_25 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 5 - 10 (6 bit)
access : read-write
P0_26_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_26 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 6 - 12 (7 bit)
access : read-write
P0_27_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P0_27 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P0_PADPWDR_CTRL_REG).
bits : 7 - 14 (8 bit)
access : read-write
P1_00_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P1_00 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG).
bits : 8 - 16 (9 bit)
access : read-write
P1_01_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P1_01 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG).
bits : 9 - 18 (10 bit)
access : read-write
P1_02_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P1_02 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG).
bits : 10 - 20 (11 bit)
access : read-write
P1_06_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P1_06 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG).
bits : 11 - 22 (12 bit)
access : read-write
P1_09_LOWDRV : 0 = Normal operation 1 = Reduces the driving strength of P1_09 pad Note: This mode should be coupled with the selection of VDD1V8P supply rail for the specific pad (see also the description of P1_PADPWDR_CTRL_REG).
bits : 12 - 24 (13 bit)
access : read-write
P1 Reset port pins Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_RESET : Writing a 1 to P1[y] sets P1[y] to 0. Writing 0 is discarded Reading returns 0
bits : 0 - 22 (23 bit)
access : write-only
P0_00 Mode Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : Function of port: 0: GPIO (see also the PUPD bit-field) 1: UART_RX 2: UART_TX 3: UART2_RX 4: UART2_TX 5: UART2_CTSN 6: UART2_RTSN 7: UART3_RX 8: UART3_TX 9: UART3_CTSN 10: UART3_RTSN 11: ISO_CLK 12: ISO_DATA 13: SPI_DI 14: SPI_DO 15: SPI_CLK16: SPI_EN 17: SPI2_DI 18: SPI2_DO 19: SPI2_CLK 20: SPI2_EN 21: I2C_SCL 22: I2C_SDA 23: I2C2_SCL 24: I2C2_SDA 25: USB_SOF 26: ADC (dedicated pins, see also the Input/Output Ports chapter of Datasheet) 27: USB (dedicated pins P0_14 and P0_15) 28: PCM_DI 29: PCM_DO 30: PCM_FSC 31: PCM_CLK 32: PDM_DATA 33: PDM_CLK 34: COEX_EXT_ACT 35: COEX_SMART_ACT 36: COEX_SMART_PRI 37: PORT0_DCF 38: PORT1_DCF 39: PORT2_DCF 40: PORT3_DCF 41: PORT4_DCF 42: CLOCK (see also GPIO_CLK_SEL_REG for the dedicated pins mapping of supported clocks) 43: PG (dedicated pins, see also the Input/Output Ports chapter of Datasheet) 44: LCD (dedicated pins see also the Input/Output Ports chapter of Datasheet) 45: LCD_SPI_DC 46: LCD_SPI_DO 47: LCD_SPI_CLK 48: LCD_SPI_EN 49: TIM_PWM 50: TIM2_PWM 51: TIM_1SHOT 52: TIM2_1SHOT 53: TIM3_PWM 54: TIM4_PWM 55: Reserved 56: CMAC_DIAG0 57: CMAC_DIAG1 58: CMAC_DIAG2 59: CMAC_DIAGX (dedicated pins, see also the Input/Output Ports chapter of Datasheet) 60: Reserved 61: Reserved 62: Reserved 63: Reserved
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_01 Mode Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_02 Mode Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_03 Mode Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_04 Mode Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_05 Mode Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_06 Mode Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_07 Mode Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_08 Mode Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_09 Mode Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1 Data input / output Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_DATA : Set P1 output register when written Returns the value of P1 port when read
bits : 0 - 22 (23 bit)
access : read-write
P0_10 Mode Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_11 Mode Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_12 Mode Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_13 Mode Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_14 Mode Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_15 Mode Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_16 Mode Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_17 Mode Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_18 Mode Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_19 Mode Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_20 Mode Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_21 Mode Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_22 Mode Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_23 Mode Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_24 Mode Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_25 Mode Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0 Set port pins Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_SET : Writing a 1 to P0[y] sets P0[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 31 (32 bit)
access : write-only
P0_26 Mode Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_27 Mode Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_28 Mode Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_29 Mode Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_30 Mode Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0_31 Mode Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_00 Mode Register
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_01 Mode Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_02 Mode Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_03 Mode Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_04 Mode Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_05 Mode Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_06 Mode Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_07 Mode Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_08 Mode Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_09 Mode Register
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1 Set port pins Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_SET : Writing a 1 to P1[y] sets P1[y] to 1. Writing 0 is discarded Reading returns 0
bits : 0 - 22 (23 bit)
access : write-only
P1_10 Mode Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_11 Mode Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_12 Mode Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_13 Mode Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_14 Mode Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_15 Mode Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_16 Mode Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_17 Mode Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_18 Mode Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_19 Mode Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_20 Mode Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_21 Mode Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P1_22 Mode Register
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PID : See P0_00_MODE_REG[PID]
bits : 0 - 5 (6 bit)
access : read-write
PUPD : 00 = Input, no resistors selected 01 = Input, pull-up selected 10 = Input, pull-down selected 11 = Output, no resistors selected In ADC mode, these bits are don't care.
bits : 8 - 17 (10 bit)
access : read-write
PPOD : 0: Push pull 1: Open drain
bits : 10 - 20 (11 bit)
access : read-write
P0 Output Power Control Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_OUT_CTRL : 0 = P0_x port output is powered by the V30 rail (default) 1 = P0_x port output is powered by the 1V8P rail bit x controls the power supply of P0[x]
bits : 6 - 37 (32 bit)
access : read-write
P1 Output Power Control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_OUT_CTRL : 0 = P1_x port output is powered by the V30 rail (default) 1 = P1_x port output is powered by the 1V8P rail bit x controls the power supply of P1[x]
bits : 0 - 22 (23 bit)
access : read-write
Select which clock to map on ports P0/P1
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FUNC_CLOCK_SEL : Select which clock to map when PID = FUNC_CLOCK. 0x0: XTAL32K 0x1: RC32K 0x2: RCX 0x3: XTAL32M 0x4: RC32M 0x5: DIVN 0x6: Reserved 0x7: Reserved
bits : 0 - 2 (3 bit)
access : read-write
FUNC_CLOCK_EN : If set, it enables the mapping of the selected clock signal, according to FUNC_CLOCK_SEL bit-field.
bits : 3 - 6 (4 bit)
access : read-write
XTAL32K_OUTPUT_EN : XTAL32K output enable bit-field. When set, it enables the mapping of XTAL32K clock on dedicated GPIO (P0_14).The specific GPIO must be configured as GPIO output.
bits : 4 - 8 (5 bit)
access : read-write
RC32K_OUTPUT_EN : RC32K output enable bit-field. When set, it enables the mapping of RC32K clock on dedicated GPIO (P0_17). The specific GPIO must be configured as GPIO output.
bits : 5 - 10 (6 bit)
access : read-write
RCX_OUTPUT_EN : RCX output enable bit-field. When set, it enables the mapping of RCX clock on dedicated GPIO (P0_16). The specific GPIO must be configured as GPIO output.
bits : 6 - 12 (7 bit)
access : read-write
XTAL32M_OUTPUT_EN : XTAL32M output enable bit-field. When set, it enables the mapping of XTAL32M clock on dedicated GPIO (P0_12). The specific GPIO must be configured as GPIO output.
bits : 7 - 14 (8 bit)
access : read-write
RC32M_OUTPUT_EN : RC32M output enable bit-field. When set, it enables the mapping of RC32M clock on dedicated GPIO (P0_13). The specific GPIO must be configured as GPIO output.
bits : 8 - 16 (9 bit)
access : read-write
DIVN_OUTPUT_EN : DIVN output enable bit-field. When set, it enables the mapping of DIVN clock on dedicated GPIO (P0_15). The specific GPIO must be configured as GPIO output.
bits : 9 - 18 (10 bit)
access : read-write
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