SET_FREEZE_REG

GP_CONTROL_REG

USBPAD_REG

RESET_FREEZE_REG

DEBUG_REG

GP_STATUS_REG

FRZ_WKUPTIM : If '1', the Wake Up Timer is frozen, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM : If '1', the SW Timer is frozen, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_RESERVED :
bits : 2 - 4 (3 bit)
access : read-write

FRZ_SYS_WDOG : If '1', the SYS SW Watchdog Timer is frozen, '0' is discarded. WATCHDOG_CTRL_REG[NMI_RST] must be '0' to allow the freeze function.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_USB : If '1', the USB is frozen, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

FRZ_DMA : If '1', the DMA is frozen, '0' is discarded.
bits : 5 - 10 (6 bit)
access : read-write

FRZ_SWTIM2 : If '1', the SW Timer2 is frozen, '0' is discarded.
bits : 6 - 12 (7 bit)
access : read-write

FRZ_PWMLED : If '1', the PWM LED is frozen, '0' is discarded.
bits : 7 - 14 (8 bit)
access : read-write

FRZ_SWTIM3 : If '1', the SW Timer3 is frozen, '0' is discarded.
bits : 8 - 16 (9 bit)
access : read-write

FRZ_SWTIM4 : If '1', the SW Timer4 is frozen, '0' is discarded.
bits : 9 - 18 (10 bit)
access : read-write

FRZ_CMAC_WDOG : If '1', the CMAC SW Watchdog Timer is frozen, '0' is discarded.
bits : 10 - 20 (11 bit)
access : read-write

CMAC_H2H_BRIDGE_BYPASS : If '1', the AHB-to-AHB bridge is bypassed, reducing the wait cycles needed to access the CMAC Register File, only when the system clock source is the XTAL and both hclk and cmac_hclk are running at 32 MHz, i.e. at the XTAL clock rate.
bits : 1 - 2 (2 bit)
access : read-write

USBPAD_EN : 0: The power for the USB PHY and USB pads is switched on when the USB is enabled. 1: The power for the USB PHY and USB pads is forced on.
bits : 0 - 0 (1 bit)
access : read-write

USBPHY_FORCE_SW1_OFF : 0: Pull up resistor SW1 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be switched off.
bits : 1 - 2 (2 bit)
access : read-write

USBPHY_FORCE_SW2_ON : 0: Pull up resistor SW2 is controlled by the USB controller. It is off when the USB is not enabled. 1: Force the pull up resistor on USBP to be 2.3Kohm
bits : 2 - 4 (3 bit)
access : read-write

FRZ_WKUPTIM : If '1', the Wake Up Timer continues, '0' is discarded.
bits : 0 - 0 (1 bit)
access : read-write

FRZ_SWTIM : If '1', the SW Timer continues, '0' is discarded.
bits : 1 - 2 (2 bit)
access : read-write

FRZ_RESERVED :
bits : 2 - 4 (3 bit)
access : read-write

FRZ_SYS_WDOG : If '1', the SYS SW Watchdog Timer continues, '0' is discarded.
bits : 3 - 6 (4 bit)
access : read-write

FRZ_USB : If '1', the USB continues, '0' is discarded.
bits : 4 - 8 (5 bit)
access : read-write

FRZ_DMA : If '1', the DMA continues, '0' is discarded.
bits : 5 - 10 (6 bit)
access : read-write

FRZ_SWTIM2 : If '1', the SW Timer2 continues, '0' is discarded.
bits : 6 - 12 (7 bit)
access : read-write

FRZ_PWMLED : If '1', the PWM LED continues, '0' is discarded.
bits : 7 - 14 (8 bit)
access : read-write

FRZ_SWTIM3 : If '1', the SW Timer3 continues, '0' is discarded.
bits : 8 - 16 (9 bit)
access : read-write

FRZ_SWTIM4 : If '1', the SW Timer4 continues, '0' is discarded.
bits : 9 - 18 (10 bit)
access : read-write

FRZ_CMAC_WDOG : If '1', the CMAC SW Watchdog Timer continues, '0' is discarded.
bits : 10 - 20 (11 bit)
access : read-write

SYS_CPU_FREEZE_EN : 1: Enable Freezing on-chip peripherals (see Note 2) by the SYS CPU (ARM CM33). Default '1', freezing of the on-chip peripherals is enabled when the Cortex-M33 is halted in DEBUG State. If '0', freezing of the on-chip peripherals is only depending on [RE]SET_FREEZE_REG except the system watchdog timer. The system watchdog timer is always frozen when the Cortex-M33 is halted in DEBUG State. Note 1: This bit is retained. Note 2: See [RE]SET_FREEZE_REG for the specific on-chip peripherals.
bits : 0 - 0 (1 bit)
access : read-write

CMAC_CPU_FREEZE_EN : 1: Enable Freezing on-chip peripherals (see Note 2) by the CMAC CPU. Note 1: This bit is retained. Note 2: See [RE]SET_FREEZE_REG for the specific on-chip peripherals.
bits : 1 - 2 (2 bit)
access : read-write

HALT_SYS_CMAC_CPU_EN : 1: Enable SYS CPU (ARM CM33) halting to the CMAC CPU. Note 1: This bit is retained. Note 2: Set this bit to '0' before going into deep sleep to prevent unpredictable halting behavior after waking up.
bits : 2 - 4 (3 bit)
access : read-write

HALT_CMAC_SYS_CPU_EN : 1: Enable CMAC CPU halting to the SYS CPU (ARM CM33). Note 1: This bit is retained. Note 2: Set this bit to '0' before going into deep sleep to prevent unpredictable halting behavior after waking up.
bits : 3 - 6 (4 bit)
access : read-write

SYS_CPU_IS_HALTED : 1: SYS CPU (ARM CM33) is halted.
bits : 4 - 8 (5 bit)
access : read-only

CMAC_CPU_IS_HALTED : 1: CMAC CPU is halted.
bits : 5 - 10 (6 bit)
access : read-only

SYS_CPUWAIT : 1: Stall the processor core out of reset (always after a wake-up). Debugger access continue when the core is stalled. When set to '0' again the core resumes instruction execution. Note: This bit is retained.
bits : 6 - 12 (7 bit)
access : read-write

SYS_CPUWAIT_ON_JTAG : 1: Stall the processor core out of reset (only after a wake-up from JTAG). Debugger access continue when the core is stalled. When set to '0' again the core resumes instruction execution. This feature is independent of the PDC (Power Domain Controller) settings. If this bit is set and there is SW/JTAG activity during deep sleep, the SYS CPU is stalled after the wake-up. Note: This bit is retained.
bits : 7 - 14 (8 bit)
access : read-write

CROSS_CPU_HALT_SENSITIVITY : Select the cross CPU halt sensitivity. 0: Level triggered, 1: Pulse triggered. Note: This bit is retained.
bits : 8 - 16 (9 bit)
access : read-write

CAL_PHASE : If '1', it designates that the chip is in Calibration Phase i.e. the OTP has been initially programmed but no Calibration has occured.
bits : 0 - 0 (1 bit)
access : read-write