MODE_REG

FRONTPORCHXY_REG

BLANKINGXY_REG

CRC_REG

LAYER0_OFFSETX_REG

BACKPORCHXY_REG

DBIB_CFG_REG

GPIO_REG

LAYER0_MODE_REG

LAYER0_STARTXY_REG

LAYER0_SIZEXY_REG

LAYER0_BASEADDR_REG

CLKCTRL_REG

LAYER0_STRIDE_REG

LAYER0_RESXY_REG

BGCOLOR_REG

JDI_RESXY_REG

JDI_FBX_BLANKING_REG

JDI_FBY_BLANKING_REG

JDI_HCK_WIDTH_REG

JDI_XRST_WIDTH_REG

JDI_VST_DELAY_REG

JDI_VST_WIDTH_REG

JDI_VCK_DELAY_REG

JDI_HST_DELAY_REG

JDI_HST_WIDTH_REG

JDI_ENB_START_HLINE_REG

JDI_ENB_END_HLINE_REG

RESXY_REG

JDI_ENB_START_CLK_REG

JDI_ENB_WIDTH_CLK_REG

DBIB_CMD_REG

IDREG_REG

INTERRUPT_REG

STATUS_REG

LCDC_TMODE : Test mode 0: disabled 1: enabled
bits : 0 - 0 (1 bit)
access : read-write

LCDC_DSCAN : Double horizontal scan 0: disabled 1: enabled
bits : 1 - 2 (2 bit)
access : read-write

LCDC_FORM_OFF : Formating off 0: disabled 1: enabled
bits : 3 - 6 (4 bit)
access : read-write

LCDC_MIPI_OFF : MIPI off. (SPI mode of MIPI standard) 0: disabled 1: enabled
bits : 4 - 8 (5 bit)
access : read-write

LCDC_OUT_MODE : Selection of the output mode 0000: Parallel RGB 1000: JDI MIP All the other values are reserved.
bits : 5 - 13 (9 bit)
access : read-write

LCDC_PIXCLKOUT_SEL : Selects the pixel out clock for the display. 0: based on the pixel pipeline clock 1: based on the format pipeline clock See also the LCDC_CLKCTRL_REG.
bits : 11 - 22 (12 bit)
access : read-write

LCDC_SFRAME_UPD : Single frame update. 0: disable 1: enable
bits : 17 - 34 (18 bit)
access : read-write

LCDC_FORCE_BLANK : Forces output to blank. 0: disable 1: enable
bits : 19 - 38 (20 bit)
access : read-write

LCDC_PIXCLKOUT_POL : Pixel clock out polarity. 0: positive 1: negative
bits : 22 - 44 (23 bit)
access : read-write

LCDC_VSYNC_SCPL : Set VSYNC for a single cycle per line. 0: disable 1: enable
bits : 23 - 46 (24 bit)
access : read-write

LCDC_DE_POL : DE polarity. 0: positive 1: negative
bits : 26 - 52 (27 bit)
access : read-write

LCDC_HSYNC_POL : HSYNC polarity. 0: positive 1: negative
bits : 27 - 54 (28 bit)
access : read-write

LCDC_VSYNC_POL : VSYNC polarity. 0: positive 1: negative
bits : 28 - 56 (29 bit)
access : read-write

LCDC_MODE_EN : Mode register. 0 : disable 1 : enable
bits : 31 - 62 (32 bit)
access : read-write

LCDC_FPORCH_Y : Front porch Y (pixel clocks)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_FPORCH_X : Front porch X (lines)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_BLANKING_Y : Blanking period Y (HSYNC pulse length)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_BLANKING_X : Blanking period X (VSYNC lines)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_CRC : CRC check.
bits : 0 - 31 (32 bit)
access : read-only

LCDC_L0_OFFSETX : Offset X (negative) of X start pixel (range [n-1,0], n : pixels /8)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_L0_DMA_PREFETCH : DMA fifo prefetch level (range: 0-4) 0x0 : Prefetch mechanism is disabled 0x1 : Prefetch at least 44 bytes 0x2 : Prefetch at least 84 bytes 0x3 : Prefetch at least 116 bytes 0x4 : Prefetch at least 108 bytes Any other value : Reserved
bits : 16 - 47 (32 bit)
access : read-write

LCDC_BPORCH_Y : Back porch Y (pixel clocks)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_BPORCH_X : Back porch X (lines)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_DBIB_FMT : Defines the output format and depends of the type of the output interface. For the SPI3/SPI4 are supported the following formats: 0x06 : RGB111-1 {2b00, R(n), G(n), B(n), R(n+1), G(n+1), B(n+1)} 0x07 : RGB111-2 {R(n), G(n), B(n), 1b0, R(n+1), G(n+1), B(n+1), 1b0} 0x08 : RGB111-3 {R(n), G(n), B(n), R(n+1), G(n+1), B(n+1), R(n+2), G(n+2), B(n+2),... } 0x09 : RGB111-4 {D(n), D(n+1), D(n+2),...} 0x10 : RGB332 0x11 : RGB444 0x12 : RGB565 0x13 : RGB666 0x14 : RGB888 For the JDI parallel interface should be used the format : 0x0A : RGB222
bits : 0 - 4 (5 bit)
access : read-write

LCDC_DBIB_JDI_SOFT_RST : JDI timing generation soft reset. 0 : disable 1 : enable
bits : 13 - 26 (14 bit)
access : read-write

LCDC_DBIB_JDI_INV_PIX : MSB-LSB bit selection for JDI parallel interface 0 : disable (MSB - LSB) 1 : enable (LSB -MSB)
bits : 14 - 28 (15 bit)
access : read-write

LCDC_DBIB_INV_DATA : Data inversion 0 : disable 1 : enable
bits : 15 - 30 (16 bit)
access : read-write

LCDC_DBIB_SPI_INV_ADDR : Enables horizontal line address inversion. 0 : disable 1 : enable
bits : 16 - 32 (17 bit)
access : read-write

LCDC_DBIB_SPI_HOLD : Enables the command HOLD mode of operation. Commands and data transmissions binding. 0 : disable 1 : enable
bits : 17 - 34 (18 bit)
access : read-write

LCDC_DBIB_SPI_JDI : Enables the line addressing between the horizontal lines (JDI SPI output format). 0 : disable 1 : enable
bits : 18 - 36 (19 bit)
access : read-write

LCDC_DBIB_SPI_CPOL : Sets the polarity of the clock (SCL)
bits : 19 - 38 (20 bit)
access : read-write

LCDC_DBIB_SPI_CPHA : Sets the data phase for the SPI interface
bits : 20 - 40 (21 bit)
access : read-write

LCDC_DBIB_SPI4_EN : Enable SPI4 interface. 0 : disable 1 : enable
bits : 22 - 44 (23 bit)
access : read-write

LCDC_DBIB_SPI3_EN : Enable SPI3 interface. 0 : disable 1 : enable
bits : 23 - 46 (24 bit)
access : read-write

LCDC_DBIB_DMA_EN : Send pixels from DMA to DBIB display. 0 : disable 1 : enable
bits : 24 - 48 (25 bit)
access : read-write

LCDC_DBIB_RESX : DBIB RESX, reset signal for MIPI DBIB display.
bits : 25 - 50 (26 bit)
access : read-write

LCDC_DBIB_SPI_PAD : Data padding : 0 : disable 1 : enable
bits : 28 - 56 (29 bit)
access : read-write

LCDC_DBIB_CSX_FORCE_VAL : Value of DBIB CSX to be forced, if bit 30 is set. Defines also the active level of the DBIB CSX even if the bit 30 is not set.
bits : 29 - 58 (30 bit)
access : read-write

LCDC_DBIB_CSX_FORCE : Forces the DBIB CSX value. When is enabled the DBIB CSX takes the value of the LCDC_DBIB_CSX_FORCE_VAL. 0 : disable 1 : enable
bits : 30 - 60 (31 bit)
access : read-write

LCDC_DBIB_TE_DIS : Disable the sampling of the tearing effect signal, which is provided by the LCD device. 0: the tearing effect signal is sampled 1: the tearing effect signal is not sampled.
bits : 31 - 62 (32 bit)
access : read-write

LCDC_PARIF_SEL : Selection of the parallel interface type that is forwarded to the gpio pins. 0 : JDI interface signals 1 : Clasic parallel interface
bits : 0 - 0 (1 bit)
access : read-write

LCDC_TE_INV : Applies an inversion on the TE (tearing effect) signal. 0 : the inversion is not applied on the TE signal 1 : the inversion is applied on TE signal
bits : 1 - 2 (2 bit)
access : read-write

LCDC_L0_COLOUR_MODE : Colour Mode: 00001: 16-bit RGBX5551 color format, 00010: 32-bit RGBX8888 color format, 00100: 8-bit RGB332 color format, 00101: 16-bit RGB565 color format, 00110: 32-bit XRGB8888, 00111: L8 Grayscale/Palette format, 01000: L1 Grayscale/Palette format, 01001: L4 Grayscale/Palette format, 01101: ABGR8888, 01110: BGRA8888
bits : 0 - 4 (5 bit)
access : read-write

LCDC_L0_EN : Enable layer. 0 : disable 1 : enable
bits : 31 - 62 (32 bit)
access : read-write

LCDC_L0_START_Y : Start Y (offset pixels)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_L0_START_X : Start X (offset pixels)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_L0_SIZE_Y : Size Y (Size of layer in pixels)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_L0_SIZE_X : Size X (Size of layer in pixels)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_L0_FB_ADDR : Base Address of the frame buffer
bits : 0 - 31 (32 bit)
access : read-write

LCDC_CLK_DIV : Clock divider that generates the pixel pipeline clock. Source clock of this divider is the format pipeline clock (see also LCDC_SEC_CLK_DIV). The period of the generated clock is defines as : LCDC_CLK_DIV x period_of_format_clk. A zero value gives division by one.
bits : 0 - 5 (6 bit)
access : read-write

LCDC_DMA_HOLD : Hold time before DMA activated.
bits : 8 - 21 (14 bit)
access : read-write

LCDC_SEC_CLK_DIV : Secondary clock divider that generates the format pipeline clock. Source clock of this divider is the main clock of LCD controller. The period of the generated clock is defined as : (LCDC_SEC_CLK_DIV + 1) x period_of_main_clock.
bits : 27 - 58 (32 bit)
access : read-write

LCDC_L0_STRIDE : Layer Stride (distance from line to line in bytes)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_L0_BURST_LEN : Layer burst length 000: 16-beats (default) 001: 2-beats 010: 4-beats 011: 8-beats 100: 16-beats
bits : 16 - 34 (19 bit)
access : read-write

LCDC_L0_FIFO_THR : Layer dma fifo threshold burst start 00: half fifo (default) 01: 2 burst size 10: 4 burst size 11: 8 burst size
bits : 19 - 39 (21 bit)
access : read-write

LCDC_L0_RES_Y : Resolution Y (Resolution of layer in pixels)
bits : 0 - 15 (16 bit)
access : read-write

LCDC_L0_RES_X : Resolution X (Resolution of layer in pixels)
bits : 16 - 47 (32 bit)
access : read-write

LCDC_BG_ALPHA : Alpha color used as background.
bits : 0 - 7 (8 bit)
access : read-write

LCDC_BG_BLUE : Blue color used as background.
bits : 8 - 23 (16 bit)
access : read-write

LCDC_BG_GREEN : Green color used as background.
bits : 16 - 39 (24 bit)
access : read-write

LCDC_BG_RED : Red color used as background.
bits : 24 - 55 (32 bit)
access : read-write

LCDC_JDI_RES_Y : Number of vertical transfers. Should be equal to the double of the vertical resolution (in lines).
bits : 0 - 15 (16 bit)
access : read-write

LCDC_JDI_RES_X : Number of horizontal transfers. Should be equal to the half of the horizontal resolution (in pixels).
bits : 16 - 47 (32 bit)
access : read-write

LCDC_JDI_BXBLANKING : Horizontal back blanking as a number of hck half periods
bits : 0 - 15 (16 bit)
access : read-write

LCDC_JDI_FXBLANKING : Horizontal front blanking as a number of hck half periods
bits : 16 - 47 (32 bit)
access : read-write

LCDC_JDI_BYBLANKING : Vertical back blanking as a number of vck half periods
bits : 0 - 15 (16 bit)
access : read-write

LCDC_JDI_FYBLANKING : Vertical front blanking as a number of vck half periods
bits : 16 - 47 (32 bit)
access : read-write

LCDC_JDI_HCK_WIDTH : Number of format pipeline clock cycles that define the half period of the of the HCK (high and low width). The minimum allowed value is 2.
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_XRST_WIDTH : Number of format pipeline clock cycles of XRST width
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_VST_DELAY : XRST-to-VST delay in format pipeline clock cycles
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_VST_WIDTH : VST width in format pipeline clock cycles
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_VCK_DELAY : XRST-to-VCK delay in format pipeline clock cycles
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_HST_DELAY : VCK-to-HST delay in format pipeline clock cycles
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_HST_WIDTH : HST width in format pipeline clock cycles
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_ENB_START_HLINE : The number of the first horizontal line where the ENB signal is asserted
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_ENB_END_HLINE : The number of the last horizontal line where the ENB signal is asserted
bits : 0 - 31 (32 bit)
access : read-write

LCDC_RES_Y : Resolution Y in pixels.
bits : 0 - 15 (16 bit)
access : read-write

LCDC_RES_X : Resolution X in pixels.
bits : 16 - 47 (32 bit)
access : read-write

LCDC_JDI_ENB_START_CLK : Defines the number of the HCK half periods that should take place after a transtion in the VCK and before to be enabled of the ENB.
bits : 0 - 31 (32 bit)
access : read-write

LCDC_JDI_ENB_WIDTH_CLK : ENB (high) width in HCK half periods
bits : 0 - 31 (32 bit)
access : read-write

LCDC_DBIB_CMD_VAL : Data to send to the DBI interface
bits : 0 - 15 (16 bit)
access : read-write

LCDC_DBIB_CMD_STORE : This bit has meaning only when LCDC_DBIB_CFG_REG[LCDC_DBIB_SPI_JDI] = 1. When is enabled, stores the LCDC_DBIB_CMD_VAL to the register that keeps the Y position.
bits : 27 - 54 (28 bit)
access : read-write

LCDC_DBIB_CMD_SEND : Send command to the DBI interface
bits : 30 - 60 (31 bit)
access : read-write

LCDC_ID : Identification register
bits : 0 - 31 (32 bit)
access : read-only

LCDC_VSYNC_IRQ_EN : VSYNC or TE interrupt enabled. See also the configuration bit LCDC_DBIB_CFG_REG[LCDC_DBIB_TE_DIS] for the TE signal.
bits : 0 - 0 (1 bit)
access : read-write

LCDC_HSYNC_IRQ_EN : HSYNC interrupt enabled
bits : 1 - 2 (2 bit)
access : read-write

LCDC_TE_IRQ_EN : TE interrupt enable. See also the configuration bit LCDC_DBIB_CFG_REG[LCDC_DBIB_TE_DIS]
bits : 3 - 6 (4 bit)
access : read-write

LCDC_FRAME_END_IRQ_EN : Continuous mode: frame end. Single mode: frame end or idle.
bits : 5 - 10 (6 bit)
access : read-write

LCDC_IRQ_TRIGGER_SEL : IRQ trigger control 0: Level triggering 1: Edge triggering In the case of the level triggering, the request remains active in the LCDC until to be cleared. The request can be cleared by performing a write access in the LCDC_INTERRUPT_REG. This is not required in the case of the edge triggering.
bits : 31 - 62 (32 bit)
access : read-write

LCDC_STAT_ACTIVE : Active (When not in vertical blanking)
bits : 0 - 0 (1 bit)
access : read-only

LCDC_FRAMEGEN_BUSY : The frame generator is busy (active high).
bits : 1 - 2 (2 bit)
access : read-only

LCDC_STAT_HSYNC : HSYNC signal level
bits : 2 - 4 (3 bit)
access : read-only

LCDC_STAT_VSYNC : VSYNC signal level
bits : 3 - 6 (4 bit)
access : read-only

LCDC_STAT_CSYNC : CSYNC signal level
bits : 4 - 8 (5 bit)
access : read-only

LCDC_LAST_ROW : Last row (Last row is currently displayed)
bits : 5 - 10 (6 bit)
access : read-only

LCDC_UNDERFLOW : Underflow on the current transfer. 0: There is no underflow 1: Underflow has been detected.
bits : 6 - 12 (7 bit)
access : read-only

LCDC_STICKY_UNDERFLOW : Sticky underflow(clear with write in the LCDC_INTERRUPT_REG) 0: There is no underflow 1: Underflow has been detected.Remains high until to be cleared by performing a write access on the register LCDC_INTERRUPT_REG.
bits : 7 - 14 (8 bit)
access : read-only

LCDC_DBIB_TE : The DBIB tearing effect signal
bits : 8 - 16 (9 bit)
access : read-only

LCDC_DBIB_CMD_FIFO_EMPTY_N : Command fifo empty indication (negative) 0: the fifo is empty 1: the fifo is not empty
bits : 10 - 20 (11 bit)
access : read-only

LCDC_DBIB_CMD_FIFO_FULL : Command fifo full indication. 0: is not full 1: is full
bits : 11 - 22 (12 bit)
access : read-only

LCDC_DBIB_CMD_PENDING : Transferring of command in progress. 0: idle 1: in progress
bits : 12 - 24 (13 bit)
access : read-only

LCDC_FRAME_END : Frame end (active high)
bits : 13 - 26 (14 bit)
access : read-only

LCDC_FRAME_START : Frame start (active high)
bits : 14 - 28 (15 bit)
access : read-only

LCDC_JDI_TIM_SW_RST : JDI timing generation soft reset (active high)
bits : 15 - 30 (16 bit)
access : read-only