CTRL1_REG

FLT_SMP2_REG

FLT_SMP3_REG

FLT_SMP4_REG

FLT_SMP5_REG

FLT_SMP6_REG

FLT_SMP7_REG

FLT_SMP8_REG

FLT_COEF1_REG

FLT_COEF2_REG

FLT_COEF3_REG

BRD_LS_REG

BRD_HS_REG

CTRL2_REG

BRD_STAT_REG

ADC_CTRL1_REG

ADC_RESULT_REG

LDO_REG

DFT_REG

FLT_SMP1_REG

LRA_EN : 0=lra controller disabled 1=lra controller enabled
bits : 0 - 0 (1 bit)
access : read-write

HBRIDGE_EN : 0=hbridge disabled 1=hbridge enabled
bits : 1 - 2 (2 bit)
access : read-write

ADC_EN : 0=lra adc disabled 1=lra adc enabled
bits : 2 - 4 (3 bit)
access : read-write

LDO_EN : 0=lra ldo disabled 1=lra ldo enabled
bits : 3 - 6 (4 bit)
access : read-write

LOOP_EN : 0=disable loop 1=enable loop
bits : 4 - 8 (5 bit)
access : read-write

PULLDOWN_EN : LXP and LXN node pull down enbale, when SC_EVENT=0 and and LOOP_EN=0
bits : 5 - 10 (6 bit)
access : read-write

SMP_SEL : Select which samples to store for the resonance control algorithm. 0=Sense voltage after down-sampling 1=Error voltage (after subtraction of VREF and down-sampled sense voltgae input) 2=Duty cycle signal after loop-filter 3=Duty cycle signal after summation with DREF
bits : 6 - 13 (8 bit)
access : read-write

IRQ_DIV : Divider value of the interrupt request. Number of LRA/ERM periods, between successive IRQs. 0,1=every (half) cycle, depending on IRQ_IDX 2=every second cycle, IRQ at the end of first or both half cycles (based on IRQ_IDX), etc.
bits : 8 - 19 (12 bit)
access : read-write

IRQ_IDX : At which sample index an IRQ will be generated (0-15). When IRQ_IDX < 8, IRQs are generated at both half cycles (IRQ_IDX and IRQ_IDX+8), otherwise only in the second half cycle.
bits : 12 - 27 (16 bit)
access : read-write

IRQ_CTRL_EN : 0 = interrupt controller disabled 1 = interupt controller enabled
bits : 16 - 32 (17 bit)
access : read-write

IRQ_ADC_EN : 0 = interrupt adc disabled 1 = interupt adc enabled
bits : 17 - 34 (18 bit)
access : read-write

IRQ_SCP_EVENT_EN : 0 = interrupt scp event disabled 1 = interupt scp event enabled
bits : 18 - 36 (19 bit)
access : read-write

SMP_IDX : Current bin index (0-15). Check if equal to IRQ_IDX before and/or after updating HALF_PERIOD with ISR.
bits : 24 - 51 (28 bit)
access : read-only

LRA_SMP_3 : Third sample in first half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_4 : Fourth sample in first half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_5 : Fifth sample in first half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_6 : Sixth sample in first half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_7 : Seventh sample in first half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_8 : Eighth sample in first half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_9 : First sample in second half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_10 : Second sample in second half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_11 : Third sample in second half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_12 : Fourth sample in second half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_13 : Fifth sample in second half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_14 : Sixth sample in second half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

LRA_SMP_15 : Seventh sample in second half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_16 : Eighth sample in second half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only

FLT_COEF_00 : Loop filter state-space coefficient a11 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).
bits : 0 - 15 (16 bit)
access : read-write

FLT_COEF_01 : Loop filter state-space coefficient a12 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).
bits : 16 - 47 (32 bit)
access : read-write

FLT_COEF_02 : Loop filter state-space coefficient b1 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999). Note: For correct intended loop gain, modify the intended value of b1 to b1/ADC_GAIN, where ADC_GAIN is the normalized gain of the ADC (i.e. ADC_GAIN = GP_ADC_VALUE´300 mA/[ILRA´128]).
bits : 0 - 15 (16 bit)
access : read-write

FLT_COEF_10 : Loop filter state-space coefficient a21 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).
bits : 16 - 47 (32 bit)
access : read-write

FLT_COEF_11 : Loop filter state-space coefficient a22 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999).
bits : 0 - 15 (16 bit)
access : read-write

FLT_COEF_12 : Loop filter state-space coefficient b2 (1 sign bit, 1 integer bit, 14 fractional bits, range -2.000 .. +1.999). Note: For correct intended loop gain, modify the intended value of b1 to b1/ADC_GAIN, where ADC_GAIN is the normalized gain of the ADC (i.e. ADC_GAIN = GP_ADC_VALUE´300 mA/[ILRA´128]).
bits : 16 - 47 (32 bit)
access : read-write

ERC_LS_EN : LS edge-rate control enable
bits : 0 - 0 (1 bit)
access : read-write

ERC_LS_TRIM : LS edge-rate control trimming. High-to-Low switching slewing: 00: 25 MV/s 01: 50 MV/s 10: 75 MV/s 11: 100 MV/s
bits : 1 - 3 (3 bit)
access : read-write

SCP_LS_EN : LS short-circuit protection enable
bits : 3 - 6 (4 bit)
access : read-write

SCP_LS_TRIM_P : LSP short-circuit protection limit trimming
bits : 4 - 11 (8 bit)
access : read-write

SCP_LS_TRIM_N : LSN short-circuit protection limit trimming
bits : 8 - 19 (12 bit)
access : read-write

ERC_HS_EN : HS edge-rate control enable
bits : 0 - 0 (1 bit)
access : read-write

ERC_HS_TRIM : HS edge-rate control trimming. Lowto-High switching slewing: 00: 25 MV/s 01: 50 MV/s 10: 75 MV/s 11: 100 MV/s
bits : 1 - 3 (3 bit)
access : read-write

SCP_HS_EN : HS short-circuit protection enable
bits : 3 - 6 (4 bit)
access : read-write

SCP_HS_TRIM : HS short-circuit protection limit trimming
bits : 4 - 11 (8 bit)
access : read-write

HSGND_TRIM : HS gnd trim, default at 100 000: 2.2V and 111:3.6V with 0.2V per step
bits : 8 - 18 (11 bit)
access : read-write

TRIM_GAIN : Current-sensing amplifier gain settings: 0001: x6 0010: x8 0100: x10 1000: x12
bits : 11 - 25 (15 bit)
access : read-write

PWM_MODE : PWM pulse placement: 0=middle, 1=left, 2=right, 3=alternate
bits : 0 - 1 (2 bit)
access : read-write

FLT_IN_SEL : 0 = normal operation 1 = ADC output overruled by register field MAN_FLT_IN
bits : 2 - 4 (3 bit)
access : read-write

POLARITY : Polarity of the square wave (0=normal 1=inverted) Use for rapid stop.
bits : 3 - 6 (4 bit)
access : read-write

SMP_MODE : Sampling mode for data aiding automatic resonance control (0=averaging, 1=last sample)
bits : 4 - 8 (5 bit)
access : read-write

AUTO_MODE : Automatic frequency control (0=disabled , 1=enabled, not yet implemented)
bits : 5 - 10 (6 bit)
access : read-write

HALF_PERIOD : Half of the LRA period, in units of 4 ms (= 125 kHz divided by the resonant frequency of the LRA).
bits : 16 - 47 (32 bit)
access : read-write

HSP_STAT : HSP power FET gate actual status
bits : 0 - 0 (1 bit)
access : read-only

HSN_STAT : HSN power FET gate actual status
bits : 1 - 2 (2 bit)
access : read-only

LSP_STAT : LSP power FET gate actual status
bits : 2 - 4 (3 bit)
access : read-only

LSN_STAT : LSN power FET gate actual status
bits : 3 - 6 (4 bit)
access : read-only

HSP_ON : HSP control status
bits : 4 - 8 (5 bit)
access : read-only

HSN_ON : HSN control status
bits : 5 - 10 (6 bit)
access : read-only

LSP_ON : LSP control status
bits : 6 - 12 (7 bit)
access : read-only

LSN_ON : LSN control status
bits : 7 - 14 (8 bit)
access : read-only

LOOP_STAT : 1: Loop saturation detected 0: Loop not saturated
bits : 8 - 16 (9 bit)
access : read-only

SC_EVENT_HS : 1: HS short-circuit event detected 0: no HS short-circuit event detected
bits : 9 - 18 (10 bit)
access : read-only

SC_EVENT_LS : 1: LS short-circuit event detected 0: no LS short-circuit event detected
bits : 10 - 20 (11 bit)
access : read-only

SCP_LS_COMP_OUT_P : LSP short circuit comparator output
bits : 11 - 22 (12 bit)
access : read-only

SCP_LS_COMP_OUT_N : LSN short circuit comparator output
bits : 12 - 24 (13 bit)
access : read-only

SCP_HS_OUT : HS short circuit comparator output
bits : 13 - 26 (14 bit)
access : read-only

LRA_ADC_START : 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the GP_ADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero.
bits : 0 - 0 (1 bit)
access : write-only

LRA_ADC_MUTE : 0: Normal operation 1: Short the inputs of the ADC (used for DC offset cal)
bits : 1 - 2 (2 bit)
access : read-write

LRA_ADC_SIGN : Change polarity of ADC input
bits : 2 - 4 (3 bit)
access : read-write

LRA_ADC_FREQ : ADC clock divider
bits : 3 - 9 (7 bit)
access : read-write

LRA_ADC_TEST_IN_SEL : Select analog testbus on ADC input.
bits : 7 - 14 (8 bit)
access : read-write

LRA_ADC_TEST_PARAM : Select which inputs will be enabled on the ADC. 0,1 = normal inputs (i.e. both I and Q inputs connected to LRA-current-sense voltage source) 2 = I channel connected to the analog input testbus on PORTS P14 and P15, Q channel is muted. 3 =Q channel connected to the analog input testbus on PORTS P14 and P15, I channel is muted. Note: The LRA_ADC_CTRL1_REG[ADC_MUTE] field takes precedence over this test functionality.
bits : 8 - 16 (9 bit)
access : read-write

LRA_ADC_OFFSET : ADC offset compensation value. Signed value with 3 fractional bits. -16 (0x80) to +15.875 (0x7F) in intervals of 0.125 (0x01). Note: ADC gain error must be compensated in the calculation of VREF.
bits : 9 - 25 (17 bit)
access : read-write

LRA_ADC_BUSY : 0:ADC conversion ready. 1:ADC conversion in progress.
bits : 31 - 62 (32 bit)
access : read-only

GP_ADC_VAL : Returns the 10 up to 16 bits linear value of the last AD conversion as a signed value. The most significant 11 bits are always valid, the lower 5 bits are only valid in case oversampling has been applied. Two samples results in one extra bit and 32 samples results in 5 extra bits. In the context of the LRA constant current or constant duty cycle control systems, the (non-oversampled) value is interpreted as a signed value with 7 integer bits and 3 fractional bits: -128.000 (0x8000) to +127.875 (0x7FE0) in steps of 0.125 (0x0010). Note that the measured values in this context are always positive.
bits : 0 - 15 (16 bit)
access : read-only

MAN_FLT_IN : Manual value to replace the ADC output. Select its use by FLT_IN_SEL.
bits : 16 - 47 (32 bit)
access : read-write

LDO_VREF_HOLD : 0: Indicates that the reference input is tracked, 1: Indicates that the reference input is sampled
bits : 0 - 0 (1 bit)
access : read-write

LDO_TST : When set to 1, LDO output is connected to the testbus through a test switch
bits : 1 - 2 (2 bit)
access : read-write

LDO_OK : 0: LDO not yet ok 1: LDO voltage is ready
bits : 31 - 62 (32 bit)
access : read-only

DFT_CTRL : Selection of test bus connection
bits : 0 - 15 (16 bit)
access : read-write

DFT_STALL : Force state machine in a certain state: 00: No test 01: High-Z 10: Mag 11: Demag
bits : 16 - 33 (18 bit)
access : read-write

DFT_EN_TIMER : Enable for the timer trimming
bits : 18 - 36 (19 bit)
access : read-write

DFT_FORCE_HSPN : Force HSP and HSN power FETs on: 0: not actived 1: HSP and HSN are forced on
bits : 19 - 38 (20 bit)
access : read-write

DFT_SEL :
bits : 20 - 40 (21 bit)
access : read-write

TIMER_SCALE_TRIM : Selection of delay of MAG and DEMAG signal: 00: 60ns 01: 80ns 10: 100ns 11: 120ns
bits : 21 - 43 (23 bit)
access : read-write

TIMER_TRIM : 20ns unit delay cell trimming bits
bits : 23 - 47 (25 bit)
access : read-write

PWM_MAN : pwm manual
bits : 25 - 50 (26 bit)
access : read-write

PWM_SEL : 0=use PWM from controller 1=use PWM_MAN
bits : 26 - 52 (27 bit)
access : read-write

SWM_MAN : swm manual
bits : 27 - 54 (28 bit)
access : read-write

SWM_SEL : 0=use SWM from controller 1=use SWM_MAN
bits : 28 - 56 (29 bit)
access : read-write

SPARE : spare registers bits , currently not used
bits : 29 - 60 (32 bit)
access : read-write

LRA_SMP_1 : First sample in first half-cycle used for resonance control algorithm.
bits : 0 - 15 (16 bit)
access : read-only

LRA_SMP_2 : Second sample in first half-cycle used for resonance control algorithm.
bits : 16 - 47 (32 bit)
access : read-only