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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x80 byte (0x0)
mem_usage : registers
protection :

Registers

MEM_STATUS2_REG

CMI_CODE_BASE_REG

CMI_DATA_BASE_REG

CMI_SHARED_BASE_REG

CMI_END_REG

SNC_BASE_REG

MEM_PRIO_REG

BUSY_SET_REG

BUSY_RESET_REG

BUSY_STAT_REG

MEM_STALL_REG

MEM_STATUS_REG


MEM_STATUS2_REG

RAM cells Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_STATUS2_REG MEM_STATUS2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RAM1_OFF_BUT_ACCESS RAM2_OFF_BUT_ACCESS RAM3_OFF_BUT_ACCESS RAM4_OFF_BUT_ACCESS RAM5_OFF_BUT_ACCESS RAM6_OFF_BUT_ACCESS RAM7_OFF_BUT_ACCESS RAM8_OFF_BUT_ACCESS

RAM1_OFF_BUT_ACCESS : Reading a '1' indicates RAM1 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 0 - 0 (1 bit)
access : read-write

RAM2_OFF_BUT_ACCESS : Reading a '1' indicates RAM2 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 1 - 2 (2 bit)
access : read-write

RAM3_OFF_BUT_ACCESS : Reading a '1' indicates RAM3 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 2 - 4 (3 bit)
access : read-write

RAM4_OFF_BUT_ACCESS : Reading a '1' indicates RAM4 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 3 - 6 (4 bit)
access : read-write

RAM5_OFF_BUT_ACCESS : Reading a '1' indicates RAM5 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 4 - 8 (5 bit)
access : read-write

RAM6_OFF_BUT_ACCESS : Reading a '1' indicates RAM6 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 5 - 10 (6 bit)
access : read-write

RAM7_OFF_BUT_ACCESS : Reading a '1' indicates RAM7 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 6 - 12 (7 bit)
access : read-write

RAM8_OFF_BUT_ACCESS : Reading a '1' indicates RAM8 was off but still access was performed. Writing a '1' will clear the status back to '0'.
bits : 7 - 14 (8 bit)
access : read-write


CMI_CODE_BASE_REG

CMAC code Base Address Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMI_CODE_BASE_REG CMI_CODE_BASE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMI_CODE_BASE_ADDR

CMI_CODE_BASE_ADDR : Base address for CMAC code with steps of 1 kB. 0x001: 1 kB base address 0x010: 16 kB base address 0x100: 256 kB base address
bits : 10 - 28 (19 bit)
access : read-write


CMI_DATA_BASE_REG

CMAC data Base Address Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMI_DATA_BASE_REG CMI_DATA_BASE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMI_DATA_BASE_ADDR

CMI_DATA_BASE_ADDR : Base address for CMAC data with steps of 4 bytes. 0x00001: 4 byte base address 0x00010: 64 byte base address 0x00100: 1 kB base address 0x01000: 16 kB base address 0x10000: 256 kB base address
bits : 2 - 20 (19 bit)
access : read-write


CMI_SHARED_BASE_REG

CMAC shared data Base Address Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMI_SHARED_BASE_REG CMI_SHARED_BASE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMI_SHARED_BASE_ADDR

CMI_SHARED_BASE_ADDR : Base address for CMAC shared data with steps of 1 kB. 0x001: 1 kB base address 0x010: 16 kB base address 0x100: 256 kB base address
bits : 10 - 28 (19 bit)
access : read-write


CMI_END_REG

CMAC end Address Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMI_END_REG CMI_END_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMI_END_ADDR

CMI_END_ADDR : End address for CMAC code and data accesses with steps of 1 kB. 0x000: accesses up to 1kB are allowed 0x001: accesses up to 2kB are allowed 0x01F: accesses up to 32kB are allowed 0x1FF: accesses up to 512kB are allowed
bits : 10 - 28 (19 bit)
access : read-write


SNC_BASE_REG

Sensor Node Controller Base Address Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SNC_BASE_REG SNC_BASE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNC_BASE_ADDRESS

SNC_BASE_ADDRESS : Base address for SNC interface with steps of 4 bytes. 0x00001: 4 byte base address 0x00010: 64 byte base address 0x00100: 1 kB base address 0x01000: 16 kB base address 0x10000: 256 kB base address
bits : 2 - 20 (19 bit)
access : read-write


MEM_PRIO_REG

Priority Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_PRIO_REG MEM_PRIO_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNC_PRIO AHB2_PRIO AHB_PRIO

SNC_PRIO : Priority for the SNC interface. 00: low priority (default) 01: mid priority 1x: high priority
bits : 0 - 1 (2 bit)
access : read-write

AHB2_PRIO : Priority for the AHB2 interface. 00: low priority (default) 01: mid priority 1x: high priority
bits : 2 - 5 (4 bit)
access : read-write

AHB_PRIO : Priority for the AHB interface. 00: low priority (default) 01: mid priority 1x: high priority
bits : 4 - 9 (6 bit)
access : read-write


BUSY_SET_REG

BSR Set Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSY_SET_REG BUSY_SET_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY_UART BUSY_UART2 BUSY_SPI BUSY_SPI2 BUSY_I2C BUSY_I2C2 BUSY_SDADC BUSY_PCM BUSY_SRC BUSY_PDM BUSY_GPADC BUSY_UART3 BUSY_TIMER BUSY_TIMER2 BUSY_MOTOR BUSY_SPARE

BUSY_UART : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 0 - 1 (2 bit)
access : writeonce

BUSY_UART2 : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 2 - 5 (4 bit)
access : writeonce

BUSY_SPI : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 4 - 9 (6 bit)
access : writeonce

BUSY_SPI2 : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 6 - 13 (8 bit)
access : writeonce

BUSY_I2C : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 8 - 17 (10 bit)
access : writeonce

BUSY_I2C2 : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 10 - 21 (12 bit)
access : writeonce

BUSY_SDADC : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 12 - 25 (14 bit)
access : writeonce

BUSY_PCM : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 14 - 29 (16 bit)
access : writeonce

BUSY_SRC : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 16 - 33 (18 bit)
access : writeonce

BUSY_PDM : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 18 - 37 (20 bit)
access : writeonce

BUSY_GPADC : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 20 - 41 (22 bit)
access : writeonce

BUSY_UART3 : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 22 - 45 (24 bit)
access : writeonce

BUSY_TIMER : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 24 - 49 (26 bit)
access : writeonce

BUSY_TIMER2 : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 26 - 53 (28 bit)
access : writeonce

BUSY_MOTOR : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 28 - 57 (30 bit)
access : writeonce

BUSY_SPARE : Writing a non-zero value to this field sets the corresponding BUSY bit, but only if it was not claimed (BUSY=0). Reading returns 0 to allow read/modify/write to the register.
bits : 30 - 61 (32 bit)
access : writeonce


BUSY_RESET_REG

BSR Reset Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSY_RESET_REG BUSY_RESET_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY_UART BUSY_UART2 BUSY_SPI BUSY_SPI2 BUSY_I2C BUSY_I2C2 BUSY_SDADC BUSY_PCM BUSY_SRC BUSY_PDM BUSY_GPADC BUSY_UART3 BUSY_TIMER BUSY_TIMER2 BUSY_MOTOR BUSY_SPARE

BUSY_UART : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 0 - 1 (2 bit)
access : read-write

BUSY_UART2 : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 2 - 5 (4 bit)
access : read-write

BUSY_SPI : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 4 - 9 (6 bit)
access : read-write

BUSY_SPI2 : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 6 - 13 (8 bit)
access : read-write

BUSY_I2C : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 8 - 17 (10 bit)
access : read-write

BUSY_I2C2 : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 10 - 21 (12 bit)
access : read-write

BUSY_SDADC : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 12 - 25 (14 bit)
access : read-write

BUSY_PCM : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 14 - 29 (16 bit)
access : read-write

BUSY_SRC : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 16 - 33 (18 bit)
access : read-write

BUSY_PDM : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 18 - 37 (20 bit)
access : read-write

BUSY_GPADC : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 20 - 41 (22 bit)
access : read-write

BUSY_UART3 : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 22 - 45 (24 bit)
access : read-write

BUSY_TIMER : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 24 - 49 (26 bit)
access : read-write

BUSY_TIMER2 : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 26 - 53 (28 bit)
access : read-write

BUSY_MOTOR : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 28 - 57 (30 bit)
access : read-write

BUSY_SPARE : Clear the BUSY bitfield, by writing the master code which has claimed to this field Reading returns 0 to allow read/modify/write to the register.
bits : 30 - 61 (32 bit)
access : read-write


BUSY_STAT_REG

BSR Status Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BUSY_STAT_REG BUSY_STAT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY_UART BUSY_UART2 BUSY_SPI BUSY_SPI2 BUSY_I2C BUSY_I2C2 BUSY_SDADC BUSY_PCM BUSY_SRC BUSY_PDM BUSY_GPADC BUSY_UART3 BUSY_TIMER BUSY_TIMER2 BUSY_MOTOR BUSY_SPARE

BUSY_UART : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 0 - 1 (2 bit)
access : read-only

BUSY_UART2 : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 2 - 5 (4 bit)
access : read-only

BUSY_SPI : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 4 - 9 (6 bit)
access : read-only

BUSY_SPI2 : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 6 - 13 (8 bit)
access : read-only

BUSY_I2C : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 8 - 17 (10 bit)
access : read-only

BUSY_I2C2 : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 10 - 21 (12 bit)
access : read-only

BUSY_SDADC : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 12 - 25 (14 bit)
access : read-only

BUSY_PCM : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 14 - 29 (16 bit)
access : read-only

BUSY_SRC : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 16 - 33 (18 bit)
access : read-only

BUSY_PDM : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 18 - 37 (20 bit)
access : read-only

BUSY_GPADC : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 20 - 41 (22 bit)
access : read-only

BUSY_UART3 : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 22 - 45 (24 bit)
access : read-only

BUSY_TIMER : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 24 - 49 (26 bit)
access : read-only

BUSY_TIMER2 : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 26 - 53 (28 bit)
access : read-only

BUSY_MOTOR : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 28 - 57 (30 bit)
access : read-only

BUSY_SPARE : A non-zero value indicates the resource is busy. The value represents which master is using it.
bits : 30 - 61 (32 bit)
access : read-only


MEM_STALL_REG

Maximum Stall cycles Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_STALL_REG MEM_STALL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SNC_MAX_STALL AHB2_MAX_STALL AHB_MAX_STALL

SNC_MAX_STALL : Maximum allowed number of stall cycles for the SNC interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles. 0: don't use, not feasible and can block other interfaces 1: max 1 stall cycle 15: max 15 stall cycles
bits : 0 - 3 (4 bit)
access : read-write

AHB2_MAX_STALL : Maximum allowed number of stall cycles for the AHB2 interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles. 0: don't use, not feasible and can block other interfaces 1: max 1 stall cycle 15: max 15 stall cycles
bits : 4 - 11 (8 bit)
access : read-write

AHB_MAX_STALL : Maximum allowed number of stall cycles for the AHB interface. If exceeded, the interface will get top priority (above high priority). Valid for a single access so the next access (of a burst) might end up in the que for the same number of wait cycles. 0: don't use, not feasible and can block other interfaces 1: max 1 stall cycle 15: max 15 stall cycles
bits : 8 - 19 (12 bit)
access : read-write


MEM_STATUS_REG

Memory Arbiter Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MEM_STATUS_REG MEM_STATUS_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AHB_WRITE_BUFF AHB2_WRITE_BUFF AHB_CLR_WR_BUFF AHB2_CLR_WR_BUFF AHB_WR_BUFF_CNT AHB2_WR_BUFF_CNT CMI_NOT_READY CMI_CLEAR_READY

AHB_WRITE_BUFF : 0: No AHB write access is buffered. 1: Currently a single AHB write access is buffered in the arbiter.
bits : 0 - 0 (1 bit)
access : read-only

AHB2_WRITE_BUFF : 0: No AHB2 write access is buffered. 1: Currently a single AHB2 write access is buffered in the arbiter.
bits : 1 - 2 (2 bit)
access : read-only

AHB_CLR_WR_BUFF : Writing a '1' clears AHB_WR_BUFF_CNT.
bits : 2 - 4 (3 bit)
access : write-only

AHB2_CLR_WR_BUFF : Writing a '1' clears AHB2_WR_BUFF_CNT.
bits : 3 - 6 (4 bit)
access : write-only

AHB_WR_BUFF_CNT : The maximum number of arbiter clock cycles that an AHB access has been buffered.
bits : 4 - 11 (8 bit)
access : read-only

AHB2_WR_BUFF_CNT : The maximum number of arbiter clock cycles that an AHB2 access has been buffered.
bits : 8 - 19 (12 bit)
access : read-only

CMI_NOT_READY : 0: Normal operation 1: CMI access performed which couldn't be handled right away (interface doesn't allow wait cycles)
bits : 12 - 24 (13 bit)
access : read-only

CMI_CLEAR_READY : Writing a '1' clears CMI_NOT_READY bit.
bits : 13 - 26 (14 bit)
access : write-only



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