\n

Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x98 byte (0x0)
mem_usage : registers
protection :

Registers

CTRL0_REG

CTRL4_REG

CTRL5_REG

CTRL6_REG

CTRL7_REG

CTRL8_REG

CTRL9_REG

CTRL10_REG

CTRL11_REG

CTRL12_REG

CTRL13_REG

CTRL14_REG

CTRL15_REG

CTRL1_REG

CTRL2_REG

ACKNOWLEDGE_REG

PENDING_REG

PENDING_SNC_REG

PENDING_CM33_REG

PENDING_CMAC_REG

SET_PENDING_REG

CTRL3_REG


CTRL0_REG

PDC control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL0_REG CTRL0_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : Selects which bank is used as wakeup trigger When TRIG_SELECT is 0x0, selects GPIO port0 through the WAKEUP block. When TRIG_SELECT is 0x1, selects GPIO port1 through the WAKEUP block. When TRIG_SELECT is 0x2 or 0x3, selects the peripheral IRQ. peripheral IRQ table: 0x0: Timer 0x1: Timer2 0x2: Timer3 0x3: Timer4 0x4: RTC Alarm/Rollover 0x5: RTC Timer 0x6: CMAC Timer OR wake up from CMAC debugger 0x7: Motor Controller 0x8: XTAL32MRDY_IRQ 0x9: RFDIAG_IRQ 0xA: CMAC2SYS_IRQ OR VBUS Present IRQ OR JTAG present OR Debounced IO 0xB: Sensor Node Controller 0xC to 0xE: reserved 0xF: Software trigger only
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : Selects which individual bit from the selected bank is used for wakup. For the peripheral banks, selected with TRIG_SELECT = 0x2 or 0x3, only the lower 4 bits are considered.
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL4_REG

PDC control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL4_REG CTRL4_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL5_REG

PDC control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL5_REG CTRL5_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL6_REG

PDC control register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL6_REG CTRL6_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL7_REG

PDC control register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL7_REG CTRL7_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL8_REG

PDC control register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL8_REG CTRL8_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL9_REG

PDC control register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL9_REG CTRL9_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL10_REG

PDC control register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL10_REG CTRL10_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL11_REG

PDC control register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL11_REG CTRL11_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL12_REG

PDC control register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL12_REG CTRL12_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL13_REG

PDC control register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL13_REG CTRL13_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL14_REG

PDC control register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL14_REG CTRL14_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL15_REG

PDC control register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL15_REG CTRL15_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL1_REG

PDC control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL1_REG CTRL1_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


CTRL2_REG

PDC control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL2_REG CTRL2_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : IIf set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write


ACKNOWLEDGE_REG

Clear a pending PDC bit
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACKNOWLEDGE_REG ACKNOWLEDGE_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_ACKNOWLEDGE

PDC_ACKNOWLEDGE : Writing to this field acknowledges the PDC IRQ request. The data controls which request is acknowledged
bits : 0 - 4 (5 bit)
access : write-only


PENDING_REG

Shows any pending wakup event
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PENDING_REG PENDING_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_PENDING

PDC_PENDING : Indicates which IRQ ids are pending
bits : 0 - 15 (16 bit)
access : read-only


PENDING_SNC_REG

Shows any pending IRQ to SNC
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PENDING_SNC_REG PENDING_SNC_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_PENDING

PDC_PENDING : Indicates which IRQ ids are pending towards the SensorNodeController
bits : 0 - 15 (16 bit)
access : read-only


PENDING_CM33_REG

Shows any pending IRQ to CM33
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PENDING_CM33_REG PENDING_CM33_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_PENDING

PDC_PENDING : Indicates which IRQ ids are pending towards the CM33
bits : 0 - 15 (16 bit)
access : read-only


PENDING_CMAC_REG

Shows any pending IRQ to CM33
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PENDING_CMAC_REG PENDING_CMAC_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_PENDING

PDC_PENDING : Indicates which IRQ ids are pending towards the CMAC
bits : 0 - 15 (16 bit)
access : read-only


SET_PENDING_REG

Set a pending PDC bit
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SET_PENDING_REG SET_PENDING_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PDC_SET_PENDING

PDC_SET_PENDING : Writing to this field sets the PDC wakeup request and IRQ. The data controls which request is acknowledged
bits : 0 - 4 (5 bit)
access : write-only


CTRL3_REG

PDC control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL3_REG CTRL3_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRIG_SELECT TRIG_ID EN_XTAL EN_TMR EN_PER EN_COM PDC_MASTER

TRIG_SELECT : For description, see PDC_CTRL0_REG.TRIG_SELECT
bits : 0 - 1 (2 bit)
access : read-write

TRIG_ID : For description, see PDC_CTRL0_REG.TRIG_ID
bits : 2 - 8 (7 bit)
access : read-write

EN_XTAL : If set, the XTAL32M will be started
bits : 7 - 14 (8 bit)
access : read-write

EN_TMR : If set, enables PD_TMR
bits : 8 - 16 (9 bit)
access : read-write

EN_PER : If set, enables PD_PER
bits : 9 - 18 (10 bit)
access : read-write

EN_COM : If set, enables PD_COM for GPIO access. This bit is implied when PDC_MASTER=SNC
bits : 10 - 20 (11 bit)
access : read-write

PDC_MASTER : Chooses which master is triggered when waking up 0x0: entry is disabled. 0x1: PD_SYS is woken up and CM33 is triggered 0x2: PD_RAD is woken up and CMAC is triggered 0x3: PD_COM is woken up and SNC is triggered
bits : 11 - 23 (13 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.