CTRLBUS_REG

BURSTCMDB_REG

STATUS_REG

WRITEDATA_REG

READDATA_REG

DUMMYDATA_REG

ERASECTRL_REG

ERASECMDA_REG

ERASECMDB_REG

BURSTBRK_REG

STATUSCMD_REG

CHCKERASE_REG

GP_REG

CTRLMODE_REG

UCODE_START

RECVDATA_REG

CTR_CTRL_REG

CTR_SADDR_REG

CTR_EADDR_REG

CTR_NONCE_0_3_REG

CTR_NONCE_4_7_REG

CTR_KEY_0_3_REG

CTR_KEY_4_7_REG

CTR_KEY_8_11_REG

CTR_KEY_12_15_REG

CTR_KEY_16_19_REG

CTR_KEY_20_23_REG

CTR_KEY_24_27_REG

CTR_KEY_28_31_REG

BURSTCMDA_REG

QSPIC_SET_SINGLE : Write 1 to set the bus mode in Single SPI mode when the controller is in Manual mode.
bits : 0 - 0 (1 bit)
access : write-only

QSPIC_SET_DUAL : Write 1 to set the bus mode in Dual mode when the controller is in Manual mode.
bits : 1 - 2 (2 bit)
access : write-only

QSPIC_SET_QUAD : Write 1 to set the bus mode in Quad mode when the controller is in Manual mode.
bits : 2 - 4 (3 bit)
access : write-only

QSPIC_EN_CS : Write 1 to enable the chip select (active low) when the controller is in Manual mode.
bits : 3 - 6 (4 bit)
access : write-only

QSPIC_DIS_CS : Write 1 to disable the chip select (active low) when the controller is in Manual mode.
bits : 4 - 8 (5 bit)
access : write-only

QSPIC_DAT_RX_MD : It describes the mode of the SPI bus during the data phase. 0x0: Single SPI 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 0 - 1 (2 bit)
access : read-write

QSPIC_EXT_BYTE_EN : Extra Byte Enable 0: Don't Send QSPIC_EXT_BYTE 1: Send QSPIC_EXT_BYTE
bits : 2 - 4 (3 bit)
access : read-write

QSPIC_EXT_HF_DS : Extra Half Disable Output 0: if QSPIC_EXT_BYTE_EN=1, is transmitted the complete QSPIC_EXT_BYTE 1: if QSPIC_EXT_BYTE_EN=1, the output is disabled (hi-z) during the transmission of bits [3:0] of QSPIC_EXT_BYTE
bits : 3 - 6 (4 bit)
access : read-write

QSPIC_DMY_NUM : Number of Dummy Bytes 0x0: Zero Dummy Bytes (Don't Send Dummy Bytes) 0x1: Send 1 Dummy Byte 0x2: Send 2 Dummy Bytes 0x3: Send 4 Dummy Bytes When QSPIC_DMY_FORCE is enabled, the QSPIC_DMY_NUM is overruled. In this case the number of dummy bytes is defined by the QSPIC_DMY_FORCE and is equal to 3, independent of the value of the QSPIC_DMY_NUM.
bits : 4 - 9 (6 bit)
access : read-write

QSPIC_INST_MD : Instruction mode 0: Transmit instruction at any burst access. 1: Transmit instruction only in the first access after the selection of Auto Mode.
bits : 6 - 12 (7 bit)
access : read-write

QSPIC_WRAP_MD : Wrap mode 0: The QSPIC_INST is the selected instruction at any access. 1: The QSPIC_INST_WB is the selected instruction at any wrapping burst access of length and size described by the registers QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively. In all other cases the QSPIC_INST is the selected instruction. Use this feature only when the serial FLASH memory supports a special instruction for wrapping burst access.
bits : 7 - 14 (8 bit)
access : read-write

QSPIC_WRAP_LEN : It describes the selected length of a wrapping burst (QSPIC_WRAP_MD). 0x0: 4 beat wrapping burst 0x1: 8 beat wrapping burst 0x2: 16 beat wrapping burst 0x3: Reserved
bits : 8 - 17 (10 bit)
access : read-write

QSPIC_WRAP_SIZE : It describes the selected data size of a wrapping burst (QSPIC_WRAP_MD). 0x0: byte access (8-bits) 0x1: half word access (16 bits) 0x2: word access (32-bits) 0x3: Reserved
bits : 10 - 21 (12 bit)
access : read-write

QSPIC_CS_HIGH_MIN : Between the transmissions of two different instructions to the flash memory, the SPI bus stays in idle state (QSPI_CS high) for at least this number of QSPI_SCK clock cycles. See the QSPIC_ERS_CS_HI register for some exceptions.
bits : 12 - 26 (15 bit)
access : read-write

QSPIC_DMY_FORCE : By setting this bit, the number of dummy bytes is forced to be equal to 3. In this case the QSPIC_DMY_NUM field is overruled and has no function. 0: The number of dummy bytes is controlled by the QSPIC_DMY_NUM field 1: Three dummy bytes are used. The QSPIC_DMY_NUM is overruled.
bits : 15 - 30 (16 bit)
access : read-write

QSPIC_BUSY : The status of the SPI Bus. 0: The SPI Bus is idle 1: The SPI Bus is active. Read data, write data or dummy data activity is in progress. Has meaning only in Manual mode and only when QSPIC_HRDY_MD = 1.
bits : 0 - 0 (1 bit)
access : read-only

QSPIC_WRITEDATA : Writing to this register is generating a data transfer from the controller to the external memory device. The data written in this register, is then transferred to the memory using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits/ 8-bits and is equal to the number of the transferred bits. This register has meaning only when the controller is in Manual mode.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_READDATA : A read access at this register generates a data transfer from the external memory device to the QSPIC controller. The data is transferred using the selected mode of the SPI bus (SPI, Dual SPI, Quad SPI). The data size of the access to this register can be 32-bits / 16-bits / 8-bits and is equal to the number of the transferred bits. This register has meaning only when the controller is in Manual mode.
bits : 0 - 31 (32 bit)
access : read-only

QSPIC_DUMMYDATA : Writing to this register generates a number of clock pulses to the SPI bus. During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The data size of the access to this register can be 32-bits / 16-bits/ 8-bits. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus is equal to 1, 2 or 4 for Single, Dual or Quad SPI mode respectively. This register has meaning only when the controller is in Manual mode.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_ERS_ADDR : Defines the address of the block/sector that is requested to be erased. If QSPIC_USE_32BA = 0 (24 bits addressing), bits QSPIC_ERASECTRL_REG[23-12] determine the block/ sector address bits [23-12]. QSPIC_ERASECTRL_REG[11-4] are ignored by the controller. If QSPIC_USE_32BA = 1 (32 bits addressing) bits QSPIC_ERASECTRL_REG[23-4] determine the block / sectors address bits [31:12]
bits : 4 - 27 (24 bit)
access : read-write

QSPIC_ERASE_EN : During Manual mode (QSPIC_AUTO_MD = 0). This bit is in read only mode. During Auto mode (QSPIC_AUTO_MD = 1). To request the erasing of the block/sector (QSPIC_ERS_ADDR, 12'b0) write 1 to this bit. This bit is cleared automatically with the end of the erasing. Until the end of erasing the QSPIC_ERASE_EN remains in read only mode. During the same period of time the controller remains in Auto Mode (QSPIC_AUTO_MD goes in read only mode).
bits : 24 - 48 (25 bit)
access : read-write

QSPIC_ERS_STATE : It shows the progress of sector/block erasing (read only). 0x0: No Erase. 0x1: Pending erase request 0x2: Erase procedure is running 0x3: Suspended Erase procedure 0x4: Finishing the Erase procedure 0x5..0x7: Reserved
bits : 25 - 52 (28 bit)
access : read-only

QSPIC_ERS_INST : The code value of the erase instruction.
bits : 0 - 7 (8 bit)
access : read-write

QSPIC_WEN_INST : The code value of the write enable instruction.
bits : 8 - 23 (16 bit)
access : read-write

QSPIC_SUS_INST : The code value of the erase suspend instruction.
bits : 16 - 39 (24 bit)
access : read-write

QSPIC_RES_INST : The code value of the erase resume instruction
bits : 24 - 55 (32 bit)
access : read-write

QSPIC_ERS_TX_MD : The mode of the QSPI Bus during the instruction phase of the erase instruction 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 0 - 1 (2 bit)
access : read-write

QSPIC_WEN_TX_MD : The mode of the QSPI Bus during the transmission of the write enable instruction. 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 2 - 5 (4 bit)
access : read-write

QSPIC_SUS_TX_MD : The mode of the QSPI Bus during the transmission of the suspend instruction. 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 4 - 9 (6 bit)
access : read-write

QSPIC_RES_TX_MD : The mode of the QSPI Bus during the transmission of the resume instruction 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 6 - 13 (8 bit)
access : read-write

QSPIC_EAD_TX_MD : The mode of the QSPI Bus during the address phase of the erase instruction 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 8 - 17 (10 bit)
access : read-write

QSPIC_ERS_CS_HI : After the execution of instructions: write enable, erase, erase suspend and erase resume, the QSPI_CS remains high for at least this number of qspi bus clock cycles.
bits : 10 - 24 (15 bit)
access : read-write

QSPIC_ERSRES_HLD : The controller must stay without flash memory reading requests for this number of AMBA hclk clock cycles, before to perform the command of erase or erase resume 15 - 0
bits : 16 - 35 (20 bit)
access : read-write

QSPIC_RESSUS_DLY : Defines a timer that counts the minimum allowed delay between an erase suspend command and the previous erase resume command (or the initial erase command). 0: Dont wait. The controller starts immediately to suspend the erase procedure. 1..63: The controller waits for at least this number of 222kHz clock cycles before the suspension of erasing. Time starts counting after the end of the previous erase resume command (or the initial erase command)
bits : 24 - 53 (30 bit)
access : read-write

QSPIC_BRK_WRD : This is the value of a special command (read burst break sequence) that is applied by the controller to the external memory device, in order to force the memory device to abandon the continuous read mode.
bits : 0 - 15 (16 bit)
access : read-write

QSPIC_BRK_EN : Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode. 0: The special command is not applied 1: The special command is applied This special command is applied by the controller to the external device under the following conditions: - the controller is in Auto mode - the QSPIC_INST_MD = 1 - the previous command that has been applied in the external device was read - the controller want to apply to the external device a command different than the read.
bits : 16 - 32 (17 bit)
access : read-write

QSPIC_BRK_SZ : The size of Burst Break Sequence 0: One byte (Send QSPIC_BRK_WRD[15:8]) 1: Two bytes (Send QSPIC_BRK_WRD[15:0])
bits : 17 - 34 (18 bit)
access : read-write

QSPIC_BRK_TX_MD : The mode of the QSPI Bus during the transmission of the burst break sequence. 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 18 - 37 (20 bit)
access : read-write

QSPIC_SEC_HF_DS : Disable output during the transmission of the second half (QSPIC_BRK_WRD[3:0]). Setting this bit is only useful if QSPIC_BRK_EN =1 and QSPIC_BRK_SZ= 1. 0: The controller drives the QSPI bus during the transmission of the QSPIC_BRK_WRD[3:0]. 1: The controller leaves the QSPI bus in Hi-Z during the transmission of the QSPIC_BRK_WORD[3:0].
bits : 20 - 40 (21 bit)
access : read-write

QSPIC_RSTAT_INST : The code value of the read status instruction. It is transmitted during the instruction phase of the read status instruction.
bits : 0 - 7 (8 bit)
access : read-write

QSPIC_RSTAT_TX_MD : The mode of the QSPI Bus during the instruction phase of the read status instruction. 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 8 - 17 (10 bit)
access : read-write

QSPIC_RSTAT_RX_MD : The mode of the QSPI Bus during the receive status phase of the read status instruction 0x0: Single 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 10 - 21 (12 bit)
access : read-write

QSPIC_BUSY_POS : It describes who from the bits of status represents the Busy bit (7 - 0).
bits : 12 - 26 (15 bit)
access : read-write

QSPIC_BUSY_VAL : Defines the value of the Busy bit which means that the flash is busy. 0: The flash is busy when the Busy bit is equal to 0. 1: The flash is busy when the Busy bit is equal to 1.
bits : 15 - 30 (16 bit)
access : read-write

QSPIC_RESSTS_DLY : Defines a timer that counts the minimum required delay between the reading of the status register and of the previous erase or erase resume instruction. 0: Dont wait. The controller starts to reading the Flash memory status register immediately. 1..63: The controller waits for at least this number of QSPI_CLK cycles and afterwards it starts to reading the Flash memory status register. The timer starts to count after the end of the previous erase or erase resume command. The actual timer that will be used by the controller before the reading of the Flash memory status register is defined by the QSPIC_STSDLY_SEL.
bits : 16 - 37 (22 bit)
access : read-write

QSPIC_STSDLY_SEL : Defines the timer which is used to count the delay that it has to wait before to read the FLASH Status Register, after an erase or an erase resume command. 0: The delay is controlled by the QSPIC_RESSTS_DLY which counts on the qspi clock. 1: The delay is controlled by the QSPIC_RESSUS_DLY which counts on the 222 kHz clock.
bits : 22 - 44 (23 bit)
access : read-write

QSPIC_CHCKERASE : Writing any value to this register during erasing, forces the controller to read the flash memory status register. Depending on the value of the Busy bit, it updates the QSPIC_ERASE_EN.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_PADS_DRV : QSPI pads drive current 0: 4 mA 1: 8 mA 2: 12 mA 3: 16 mA
bits : 1 - 3 (3 bit)
access : read-write

QSPIC_PADS_SLEW : QSPI pads slew rate control. Indicative values under certain conditions: 0: Rise=1.7 V/ns, Fall=1.9 V/ns (weak) 1: Rise=2.0 V/ns, Fall=2.3 V/ns 2: Rise=2.3 V/ns, Fall=2.6 V/ns 3: Rise=2.4 V/ns, Fall=2.7 V/ns (strong) Conditions: FLASH pin capacitance 6 pF, Vcc=1.8V, T=25C and Idrive=16mA.
bits : 3 - 7 (5 bit)
access : read-write

QSPIC_AUTO_MD : Mode of operation 0: The Manual Mode is selected. 1: The Auto Mode is selected. During an erasing the QSPIC_AUTO_MD goes in read only mode (see QSPIC_ERASE_EN)
bits : 0 - 0 (1 bit)
access : read-write

QSPIC_CLK_MD : Mode of the generated QSPI_SCK clock 0: Use Mode 0 for the QSPI_CLK. The QSPI_SCK is low when QSPI_CS is high. 1: Use Mode 3 for the QSPI_CLK. The QSPI_SCK is high when QSPI_CS is high.
bits : 1 - 2 (2 bit)
access : read-write

QSPIC_IO2_OEN : QSPI_IO2 output enable. Use this only in SPI or Dual SPI mode to control /WP signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero. 0: The QSPI_IO2 pad is input. 1: The QSPI_IO2 pad is output.
bits : 2 - 4 (3 bit)
access : read-write

QSPIC_IO3_OEN : QSPI_IO3 output enable. Use this only in SPI or Dual SPI mode to control /HOLD signal. When the Auto Mode is selected (QSPIC_AUTO_MD = 1) and the QUAD SPI is used, set this bit to zero. 0: The QSPI_IO3 pad is input. 1: The QSPI_IO3 pad is output.
bits : 3 - 6 (4 bit)
access : read-write

QSPIC_IO2_DAT : The value of QSPI_IO2 pad if QSPI_IO2_OEN is 1
bits : 4 - 8 (5 bit)
access : read-write

QSPIC_IO3_DAT : The value of QSPI_IO3 pad if QSPI_IO3_OEN is 1
bits : 5 - 10 (6 bit)
access : read-write

QSPIC_HRDY_MD : This configuration bit is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus, in order to not locks the AMBA bus for a long time. 0: Adds wait states via hready signal when an access is performed on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. It is not needed to checked the QSPIC_BUSY of the QSPIC_STATUS_REG. 1: The controller don't adds wait states via the hready signal, when is performed access on the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers. The QSPIC_BUSY bit of the QSPIC_STATUS_REG must be checked in order to be detected the completion of the requested access. It is applicable only when the controller is in Manual mode. In the case of the Auto mode, the controller always adds wait states via the hready signal.
bits : 6 - 12 (7 bit)
access : read-write

QSPIC_RXD_NEG : Defines the clock edge that is used for the capturing of the received data, when the read pipe is not active (QSPIC_RPIPE_EN = 0). 0: Sampling of the received data with the positive edge of the QSPI_SCK 1: Sampling of the received data with the negative edge of the QSPI_SCK The internal QSPI_SCK clock that is used by the controller for the capturing of the received data has a skew in respect of the QSPI_SCK that is received by the external memory device. In order to be improved the timing requirements of the read path, the controller supports a read pipe register with programmable clock delay. See also the QSPIC_RPIPE_EN register.
bits : 7 - 14 (8 bit)
access : read-write

QSPIC_RPIPE_EN : Controls the use of the data read pipe. 0: The read pipe is disabled the sampling clock is defined according to the QSPIC_RXD_NEG setting. 1: The read pipe is enabled. The delay of the sampling clock is defined according to the QSPI_PCLK_MD setting. (Recommended)
bits : 8 - 16 (9 bit)
access : read-write

QSPIC_PCLK_MD : Read pipe clock delay relative to the falling edge of QSPI_SCK. Refer to QSPI Timing for timing parameters and recommended values: 0 to 7
bits : 9 - 20 (12 bit)
access : read-write

QSPIC_BUF_LIM_EN : This bit has meaning only for the read in auto mode. Defines the behavior of the controller when the internal buffer is full and there are more data to be retrieved for the current burst. 0: The access in the flash device is not terminated when the internal buffer has no empty space. In this case the QSPI_SCK clock is blocked until to free space in the internal buffer. 1: The access in the flash device is terminated when the internal buffer has no empty space. A new access in the flash device will be initiated when will be requested addresses that are not present in the internal buffer. In both cases the access in the flash device is terminated when there is no any read request.
bits : 12 - 24 (13 bit)
access : read-write

QSPIC_USE_32BA : Controls the length of the address that the external memory device uses. 0: The external memory device uses 24 bits address. 1: The external memory device uses 32 bits address. The controller uses this bit in order to decide the number of the address bytes that has to transfer to the external device during Auto mode.
bits : 13 - 26 (14 bit)
access : read-write

QSPIC_UCODE_X : The controller has a dedicated memory cell of 16 words x 32 bits that is used for the storing of the microcode that describes the initialization process of the external flash device. The first word (word 0) of this memory can be accessed by accessing the QSPIC_UCODE_START register. The next words can be accessed by accessing the QSPIC_UCODE_START + 4*X (X=1 .. 15).
bits : 0 - 31 (32 bit)
access : read-write

QSPIC_RECVDATA : This register contains the received data when the QSPIC_READDATA_REG register is used in Manual mode, in order to be retrieved data from the external memory device and QSPIC_HRDY_MD=1 and and QSPIC_BUSY=0.
bits : 0 - 31 (32 bit)
access : read-only

QSPIC_CTR_EN : Controls the AES-CTR decryption feature of the QSPIC, which enables the decryption (on-the-fly) of the data that are retrieved from the flash memory device. 0: The AES-CTR decryption is disabled. 1: The controller will decrypt the content of the flash memory device that is placed in the address space that is defined by the QSPIC_CTR_SADDR_REG and QSPIC_CTR_EADDR_REG registers. The data that are placed outside the previous space are not decrypted by the QSPIC. The decryption is performed by using the AES-CTR algorithm. The AES key is defined by the QSPIC_CTR_KEY_x_y_REG registers and the nonce value by the QSPIC_CTR_NONCE_x_y_REG registers. This configuration bit has meaning only while the controller is in Auto mode. The on-the-fly decryption is not provided in Manual mode.
bits : 0 - 0 (1 bit)
access : read-write

QSPIC_CTR_SADDR : Defines the bits [31:10] of the start address in the flash memory, where an encrypted image is placed. The bits [9:0] are considered always as zero. This has meaning only when the decryption is active. See also the register QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN].
bits : 10 - 41 (32 bit)
access : read-write

QSPIC_CTR_EADDR : Defines the bits [31:10] of the end address in the flash memory, where an encrypted image is placed. The bits [9:0] are considered always as 0x3ff. This has meaning only when the decryption is active. See also the register QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN].
bits : 10 - 41 (32 bit)
access : read-write

QSPIC_CTR_NONCE_0_3 : Defines the 8 bytes of the nonce value (N0 - N7) that is used by the AES-CTR algorithm in order to be constructed the counter block (CTRB). The total size of the counter block is 128 bits or 16 bytes : CTRB0 CTRB1 CTRB2 CTRB3...CTRB14 CTRB15. The first 8 bytes (CTRB0 - CTRB7) of the counter block consisted by the nonce value. The next 8 bytes of the counter block (CTRB8-CTRB15), are produced automatically by the hardware based on the address offset inside the encrypted image, from where are retrieved the requested data. The mapping of the nonce bytes to the corresponding QSPIC_NONCE_X_Y_REG registers is the following : {CTRB0, CTRB1, CTRB2, CTRB3} = {N0, N1, N2, N3} = QSPIC_NONCE_0_3_REG[31:0] {CTRB4, CTRB5, CTRB6, CTRB7} = {N4, N5, N6, N7} = QSPIC_NONCE_4_7_REG[31:0] All these registers make sense only when QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1.Do not perform access to an encrypted address range while the updating process of the nonce value is in progress.
bits : 0 - 31 (32 bit)
access : read-write

QSPIC_CTR_NONCE_4_7 : See the description in the QSPIC_NONCE_0_3.
bits : 0 - 31 (32 bit)
access : read-write

QSPIC_CTR_KEY_0_3 : Defines the key that is used by the AES-CTR algorithm, when the on-the-fly decryption is enabled ( QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1 ). The size of the decryption key is 256bits or 32 bytes : K0 K1 K2 K3...K30 K31. The mapping of the bytes to the corresponding QSPIC_CTR_KEY_X_Y_REG regisers is the following : {K0, K1, K2, K3} = QSPIC_CTR_KEY_0_3_REG[31:0] {K4, K5, K6, K7} = QSPIC_CTR_KEY_4_7_REG[31:0] {K8, K9, K10, K11} = QSPIC_CTR_KEY_8_11_REG[31:0] {K12, K13, K14, K15} = QSPIC_CTR_KEY_12_15_REG[31:0] {K16, K17, K18, K19} = QSPIC_CTR_KEY_16_19_REG[31:0] {K20, K21, K22, K23} = QSPIC_CTR_KEY_20_23_REG[31:0] {K24, K25, K26, K27} = QSPIC_CTR_KEY_24_27_REG[31:0] {K28, K29, K30, K31} = QSPIC_CTR_KEY_28_31_REG[31:0] All these registers make sense only when QSPIC_CTR_CTRL_REG[QSPIC_CTR_EN] = 1. Do not perform access to an encrypted address range while the updating process of the decryption key is in progress.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_4_7 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_8_11 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_12_15 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_16_19 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_20_23 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_24_27 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_CTR_KEY_28_31 : See the description in the QSPIC_CTR_KEY_0_3.
bits : 0 - 31 (32 bit)
access : write-only

QSPIC_INST : Instruction Value for Incremental Burst or Single read access. This value is the selected instruction at the cases of incremental burst or single read access. Also this value is used when a wrapping burst is not supported (QSPIC_WRAP_MD)
bits : 0 - 7 (8 bit)
access : read-write

QSPIC_INST_WB : IInstruction Value for Wrapping Burst. This value is the selected instruction when QSPIC_WRAP_MD is equal to 1 and the access is a wrapping burst of length and size described by the bit fields QSPIC_WRAP_LEN and QSPIC_WRAP_SIZE respectively.
bits : 8 - 23 (16 bit)
access : read-write

QSPIC_EXT_BYTE : The value of an extra byte which will be transferred after address (only if QSPIC_EXT_BYTE_EN= 1). Usually this is the Mode Bits in Dual/Quad SPI I/O instructions.
bits : 16 - 39 (24 bit)
access : read-write

QSPIC_INST_TX_MD : It describes the mode of the SPI bus during the instruction phase. 0x0: Single SPI 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 24 - 49 (26 bit)
access : read-write

QSPIC_ADR_TX_MD : It describes the mode of the SPI bus during the address phase. 0x0: Single SPI 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 26 - 53 (28 bit)
access : read-write

QSPIC_EXT_TX_MD : It describes the mode of the SPI bus during the Extra Byte phase. 0x0: Single SPI 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 28 - 57 (30 bit)
access : read-write

QSPIC_DMY_TX_MD : It describes the mode of the SPI bus during the Dummy bytes phase. 0x0: Single SPI 0x1: Dual 0x2: Quad 0x3: Reserved
bits : 30 - 61 (32 bit)
access : read-write