CTRL_REG

CRV_ADDR_REG

CRV_LEN_REG

ADDR_REG

LEN_REG

STAT_REG

RFMON_PACK_EN : Starts capturing data from the test bus 0 : No data captured. 1 : Data captured. Should be written with 1 to start data acquisition. When the controller is not in circular mode (RFMON_CIRC_EN = 0) and after capturing a predefined number of words (RFMON_LEN), this bit will be auto cleared. In circular mode (RFMON_CIRC_EN = 1) the RFMON_PACK_EN remains 1 to be cleared by software.
bits : 0 - 0 (1 bit)
access : read-write

RFMON_CIRC_EN : Write with 1 to enable the circular mode. In circular mode the controller continuously writes data in to the memory until being disabled by software. Data are transferred in the circular buffer in the memory, as defined by RFMON_ADDR_REG and RFMON_LEN_REG registers. Disabling of the controller is realized by writing RFMON_PACK_EN with 0.
bits : 1 - 2 (2 bit)
access : read-write

RFMON_BREQ_FORCE : Write this bit with 1, when the required throughput for the transferring of the captured data is close to the capacity of the system bus/memory. The controller will be aggressive in the usage of the bus. The availability of the bus will be affected for the remaining masters.
bits : 2 - 4 (3 bit)
access : read-write

RFMON_CRV_ADDR : Bits [31:2] of AHB address that will be used by the controller in the next memory access. The bits [1:0] are always 0.
bits : 2 - 33 (32 bit)
access : read-only

RFMON_CRV_LEN : Indicates the number of words (minus 1) that remain to be transfered.
bits : 0 - 16 (17 bit)
access : read-only

RFMON_ADDR : It is the bits [31:2] of base address that is used by the AHB master interface of the controller. Defines the AHB address where the controller will start storing data at. Bits [1:0] of the address are always considered to be 0.
bits : 2 - 33 (32 bit)
access : read-write

RFMON_LEN : The number of words (minus one) that should be captured.
bits : 0 - 16 (17 bit)
access : read-write

RFMON_ACTIVE : Indicates the state of the controller. 0 : The controller is idle. 1 : The controller is active. The capturing process and/or the dma activity is in progress. The controller will be activated (RFMON_ACTIVE == 1), when RFMON_PACK_EN will be written with 1. Will return to inactive state, after the end of the capturing process (RFMON_PACK_EN==0) and the completion of the transfer of all data to memory.
bits : 0 - 0 (1 bit)
access : read-only

RFMON_OFLOW_STK : Indicates that during transfer of data, at least one overflow has been detected. 0 : The transfer completed without overflows. 1 : At least one overflow occured in the fifo. Write 1 to clear this bit.
bits : 1 - 2 (2 bit)
access : read-write