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Peripheral_Registers

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1C byte (0x0)
mem_usage : registers
protection :

Registers

CTRL_REG

OFFS_CORR_REG

CLEAR_INT_REG

RESULT_REG

GAIN_CORR_REG


CTRL_REG

Sigma Delta ADC Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_REG CTRL_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADC_EN SDADC_START SDADC_INP_SEL SDADC_INN_SEL SDADC_SE SDADC_OSR SDADC_CONT SDADC_VREF_SEL SDADC_LDO_OK SDADC_INT SDADC_MINT SDADC_DMA_EN

SDADC_EN : 0: LDO is off and ADC is disabled. 1: LDO, bias currents and modulator are enabled.
bits : 0 - 0 (1 bit)
access : read-write

SDADC_START : 0: ADC conversion ready. 1: If a 1 is written, the ADC starts a conversion. After the conversion this bit will be set to 0 and the SDADC_INT bit will be set. It is not allowed to write this bit while it is not (yet) zero.
bits : 1 - 2 (2 bit)
access : read-write

SDADC_INP_SEL : Input selection of positive side. 0: ADC0 / P1[09] 1: ADC1 / P0[25] 2: ADC2 / P0[08] 3: ADC3 / P0[09] 4: ADC4 / P1[14] 5: ADC5 / P1[20] 6: ADC6 / P1[21] 7: ADC7 / P1[22] 8: VBAT (via 4x attenuator, INN connected to ground)
bits : 2 - 7 (6 bit)
access : read-write

SDADC_INN_SEL : Input selection of negative side. 0: ADC0 / P1[09] 1: ADC1 / P0[25] 2: ADC2 / P0[08] 3: ADC3 / P0[09] 4: ADC4 / P1[14] 5: ADC5 / P1[20] 6: ADC6 / P1[21] 7: ADC7 / P1[22]
bits : 6 - 14 (9 bit)
access : read-write

SDADC_SE : 0: Differential mode 1: Single ended mode (Input selection negative side is ignored)
bits : 9 - 18 (10 bit)
access : read-write

SDADC_OSR : Oversample Rate 0: 128x 1: 256x 2: 512x 3: 1024x
bits : 10 - 21 (12 bit)
access : read-write

SDADC_CONT : 0: Manual ADC mode, a single result will be generated after setting the SDADC_START bit. 1: Continuous ADC mode, new ADC results will be constantly stored in SDADC_RESULT_REG. Still SDADC_START has to be set to start the execution. Wait for SDADC_START to become zero after clearing the SDADC_CONT bit to stop the continuous mode.
bits : 12 - 24 (13 bit)
access : read-write

SDADC_VREF_SEL : 0: Internal bandgap reference. 1: External reference.
bits : 13 - 26 (14 bit)
access : read-write

SDADC_LDO_OK : 1: Internal LDO is ready for use
bits : 14 - 28 (15 bit)
access : read-only

SDADC_INT : 1: AD conversion ready and has generated an interrupt. Must be cleared by writing any value to SDADC_CLEAR_INT_REG.
bits : 15 - 30 (16 bit)
access : read-only

SDADC_MINT : 0: Disable (mask) SDADC_ADC_INT. 1: Enable SDADC_ADC_INT to ICU.
bits : 16 - 32 (17 bit)
access : read-write

SDADC_DMA_EN : 0: DMA functionality disabled 1: DMA functionality enabled
bits : 17 - 34 (18 bit)
access : read-write


OFFS_CORR_REG

Sigma Delta ADC Offset Correction Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFS_CORR_REG OFFS_CORR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADC_OFFS_CORR

SDADC_OFFS_CORR : Offset adjust
bits : 0 - 9 (10 bit)
access : read-write


CLEAR_INT_REG

Sigma Delta ADC Clear Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEAR_INT_REG CLEAR_INT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADC_CLR_INT

SDADC_CLR_INT : Writing any value to this register will clear the ADC_INT interrupt. Reading returns 0.
bits : 0 - 15 (16 bit)
access : write-only


RESULT_REG

Sigma Delta ADC Result Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESULT_REG RESULT_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADC_VAL

SDADC_VAL : Returns up to 16 bits linear value of the last AD conversion. The effective resolution depends on the OSR used.
bits : 0 - 15 (16 bit)
access : read-only


GAIN_CORR_REG

Sigma Delta ADC Gain Correction Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAIN_CORR_REG GAIN_CORR_REG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDADC_GAIN_CORR

SDADC_GAIN_CORR : Gain adjust
bits : 0 - 9 (10 bit)
access : read-write



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