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address_offset : 0x0 Bytes (0x0)
size : 0x84 byte (0x0)
mem_usage : registers
protection :
Motor control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CYCLIC_MODE : Determines operation mode of command FIFO: 0 = Normal FIFO mode 1 = Cyclic buffer mode, CYCLIC_SIZE determines buffer depth
bits : 0 - 0 (1 bit)
access : read-write
CYCLIC_SIZE : Depth of the cyclic buffer, only valid if CYCLIC_MODE is 1.
bits : 1 - 7 (7 bit)
access : read-write
SMOTOR_MOI : Idle time of a PG after generating a waveform. A PG will remain busy for the last signal's MOI to finish.
bits : 7 - 23 (17 bit)
access : read-write
SMOTOR_GENSTART_IRQ_EN : IRQ in the event a pattern generator (configured to do so through its corresponding GENSTART_IRQ_EN bit) has just started generating a pattern: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 17 - 34 (18 bit)
access : read-write
SMOTOR_GENEND_IRQ_EN : IRQ in the event a pattern generator (configured to do so through its corresponding GENEND_IRQ_EN bit) has ended generating a pattern: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 18 - 36 (19 bit)
access : read-write
SMOTOR_FIFO_OVF_IRQ_EN : IRQ in the event of FIFO overflow: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 19 - 38 (20 bit)
access : read-write
SMOTOR_FIFO_UNR_IRQ_EN : IRQ in the event of FIFO underrun: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 20 - 40 (21 bit)
access : read-write
SMOTOR_THRESHOLD : Determines the FIFO level (write pointer - read pointer) at or below which and IRQ can be triggered using SMOTOR_THRESHOLD_IRQ_EN.
bits : 21 - 46 (26 bit)
access : read-write
SMOTOR_THRESHOLD_IRQ_EN : IRQ in the event of the FIFO level (write pointer - read pointer) reaching, or is below the threshold determined by SMOTOR_THRESHOLD. 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 26 - 52 (27 bit)
access : read-write
MC_LP_CLK_TRIG_EN : 0 = Divided sleep clock does not trigger command pop 1 = Divided sleep clock triggers command pop
bits : 27 - 54 (28 bit)
access : read-write
TRIG_RTC_EVENT_EN : 0 = RTC event does not trigger command pop 1 = RTC event triggers command pop
bits : 28 - 56 (29 bit)
access : read-write
Pattern generator 3 control register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0_SIG : Selects which signal is routed to the output.
bits : 0 - 1 (2 bit)
access : read-write
OUT1_SIG : Selects which signal is routed to the output.
bits : 2 - 5 (4 bit)
access : read-write
OUT2_SIG : Selects which signal is routed to the output.
bits : 4 - 9 (6 bit)
access : read-write
OUT3_SIG : Selects which signal is routed to the output.
bits : 6 - 13 (8 bit)
access : read-write
SIG0_EN : 0 = Signal disabled 1 = Signal enabled
bits : 8 - 16 (9 bit)
access : read-write
SIG1_EN : 0 = Signal disabled 1 = Signal enabled
bits : 9 - 18 (10 bit)
access : read-write
SIG2_EN : 0 = Signal disabled 1 = Signal enabled
bits : 10 - 20 (11 bit)
access : read-write
SIG3_EN : 0 = Signal disabled 1 = Signal enabled
bits : 11 - 22 (12 bit)
access : read-write
PG_MODE : 0 = Flex mode 1 = Pair mode
bits : 12 - 24 (13 bit)
access : read-write
PG_START_MODE : 0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command 1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command
bits : 13 - 26 (14 bit)
access : read-write
GENSTART_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 14 - 28 (15 bit)
access : read-write
GENEND_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 15 - 30 (16 bit)
access : read-write
Pattern generator 4 control register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0_SIG : Selects which signal is routed to the output.
bits : 0 - 1 (2 bit)
access : read-write
OUT1_SIG : Selects which signal is routed to the output.
bits : 2 - 5 (4 bit)
access : read-write
OUT2_SIG : Selects which signal is routed to the output.
bits : 4 - 9 (6 bit)
access : read-write
OUT3_SIG : Selects which signal is routed to the output.
bits : 6 - 13 (8 bit)
access : read-write
SIG0_EN : 0 = Signal disabled 1 = Signal enabled
bits : 8 - 16 (9 bit)
access : read-write
SIG1_EN : 0 = Signal disabled 1 = Signal enabled
bits : 9 - 18 (10 bit)
access : read-write
SIG2_EN : 0 = Signal disabled 1 = Signal enabled
bits : 10 - 20 (11 bit)
access : read-write
SIG3_EN : 0 = Signal disabled 1 = Signal enabled
bits : 11 - 22 (12 bit)
access : read-write
PG_MODE : 0 = Flex mode 1 = Pair mode
bits : 12 - 24 (13 bit)
access : read-write
PG_START_MODE : 0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command 1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command
bits : 13 - 26 (14 bit)
access : read-write
GENSTART_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 14 - 28 (15 bit)
access : read-write
GENEND_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 15 - 30 (16 bit)
access : read-write
Motor controller trigger register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
POP_CMD : Writing 1 will pop one (or more, depending on the N_CMDs field of the first) command(s) from the command buffer into its corresponding pattern generator.
bits : 0 - 0 (1 bit)
access : write-only
PG0_START : Writing 1 to this bit will start PG0, only effective in manual mode.
bits : 1 - 2 (2 bit)
access : write-only
PG1_START : Writing 1 to this bit will start PG1, only effective in manual mode.
bits : 2 - 4 (3 bit)
access : write-only
PG2_START : Writing 1 to this bit will start PG2, only effective in manual mode.
bits : 3 - 6 (4 bit)
access : write-only
PG3_START : Writing 1 to this bit will start PG3, only effective in manual mode.
bits : 4 - 8 (5 bit)
access : write-only
PG4_START : Writing 1 to this bit will start PG4, only effective in manual mode.
bits : 5 - 10 (6 bit)
access : write-only
Motor control command FIFO register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOTOR_CMD_FIFO : Writing to this address will push a command into the command FIFO.
bits : 0 - 15 (16 bit)
access : write-only
Command read pointer register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOTOR_CMD_READ_PTR : Pointer to the next command to be popped from the FIFO. The command at SMOTOR_CMD_READ_PTR-1 is the last command that has been popped from the FIFO into its corresponding PG.
bits : 0 - 5 (6 bit)
access : read-only
Command write pointer register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SMOTOR_CMD_WRITE_PTR : Pointer to the location in the FIFO where the next command will be pushed at. The last command pushed to the FIFO is at SMOTOR_CMD_WRITE_PTR - 1. Can only be changed in cyclic mode
bits : 0 - 5 (6 bit)
access : read-write
Motor control IRQ clear register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GENSTART_IRQ_CLEAR : Clears the GENSTART_IRQ_STATUS bit.
bits : 0 - 0 (1 bit)
access : write-only
GENEND_IRQ_CLEAR : Clears the GENEND_IRQ_STATUS bit.
bits : 1 - 2 (2 bit)
access : write-only
FIFO_OVF_IRQ_CLEAR : Clears the FIFO_OVF_IRQ_STATUS bit.
bits : 2 - 4 (3 bit)
access : write-only
FIFO_UNR_IRQ_CLEAR : Clears the FIFO_UNR_IRQ_STATUS bit.
bits : 3 - 6 (4 bit)
access : write-only
THRESHOLD_IRQ_CLEAR : Clears the THRESHOLD_IRQ_STATUS bit.
bits : 4 - 8 (5 bit)
access : write-only
Pattern generator 0 control register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0_SIG : Selects which signal is routed to the output.
bits : 0 - 1 (2 bit)
access : read-write
OUT1_SIG : Selects which signal is routed to the output.
bits : 2 - 5 (4 bit)
access : read-write
OUT2_SIG : Selects which signal is routed to the output.
bits : 4 - 9 (6 bit)
access : read-write
OUT3_SIG : Selects which signal is routed to the output.
bits : 6 - 13 (8 bit)
access : read-write
SIG0_EN : 0 = Signal disabled 1 = Signal enabled
bits : 8 - 16 (9 bit)
access : read-write
SIG1_EN : 0 = Signal disabled 1 = Signal enabled
bits : 9 - 18 (10 bit)
access : read-write
SIG2_EN : 0 = Signal disabled 1 = Signal enabled
bits : 10 - 20 (11 bit)
access : read-write
SIG3_EN : 0 = Signal disabled 1 = Signal enabled
bits : 11 - 22 (12 bit)
access : read-write
PG_MODE : 0 = Flex mode 1 = Pair mode
bits : 12 - 24 (13 bit)
access : read-write
PG_START_MODE : 0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command 1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command
bits : 13 - 26 (14 bit)
access : read-write
GENSTART_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 14 - 28 (15 bit)
access : read-write
GENEND_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 15 - 30 (16 bit)
access : read-write
Base address of the wavetable
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAVETABLE_BASE_X_B0 : Dummy bitfield for register test generation.
bits : 0 - 4 (5 bit)
access : read-write
WAVETABLE_BASE_X_B1 : Dummy bitfield for register test generation.
bits : 8 - 20 (13 bit)
access : read-write
WAVETABLE_BASE_X_B2 : Dummy bitfield for register test generation.
bits : 16 - 36 (21 bit)
access : read-write
WAVETABLE_BASE_X_B3 : Dummy bitfield for register test generation.
bits : 24 - 52 (29 bit)
access : read-write
Pattern generator 1 control register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0_SIG : Selects which signal is routed to the output.
bits : 0 - 1 (2 bit)
access : read-write
OUT1_SIG : Selects which signal is routed to the output.
bits : 2 - 5 (4 bit)
access : read-write
OUT2_SIG : Selects which signal is routed to the output.
bits : 4 - 9 (6 bit)
access : read-write
OUT3_SIG : Selects which signal is routed to the output.
bits : 6 - 13 (8 bit)
access : read-write
SIG0_EN : 0 = Signal disabled 1 = Signal enabled
bits : 8 - 16 (9 bit)
access : read-write
SIG1_EN : 0 = Signal disabled 1 = Signal enabled
bits : 9 - 18 (10 bit)
access : read-write
SIG2_EN : 0 = Signal disabled 1 = Signal enabled
bits : 10 - 20 (11 bit)
access : read-write
SIG3_EN : 0 = Signal disabled 1 = Signal enabled
bits : 11 - 22 (12 bit)
access : read-write
PG_MODE : 0 = Flex mode 1 = Pair mode
bits : 12 - 24 (13 bit)
access : read-write
PG_START_MODE : 0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command 1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command
bits : 13 - 26 (14 bit)
access : read-write
GENSTART_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 14 - 28 (15 bit)
access : read-write
GENEND_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 15 - 30 (16 bit)
access : read-write
Base address of the command table
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMD_TABLE_BASE_X : Dummy field for register test generation.
bits : 0 - 31 (32 bit)
access : read-only
Pattern generator 2 control register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OUT0_SIG : Selects which signal is routed to the output.
bits : 0 - 1 (2 bit)
access : read-write
OUT1_SIG : Selects which signal is routed to the output.
bits : 2 - 5 (4 bit)
access : read-write
OUT2_SIG : Selects which signal is routed to the output.
bits : 4 - 9 (6 bit)
access : read-write
OUT3_SIG : Selects which signal is routed to the output.
bits : 6 - 13 (8 bit)
access : read-write
SIG0_EN : 0 = Signal disabled 1 = Signal enabled
bits : 8 - 16 (9 bit)
access : read-write
SIG1_EN : 0 = Signal disabled 1 = Signal enabled
bits : 9 - 18 (10 bit)
access : read-write
SIG2_EN : 0 = Signal disabled 1 = Signal enabled
bits : 10 - 20 (11 bit)
access : read-write
SIG3_EN : 0 = Signal disabled 1 = Signal enabled
bits : 11 - 22 (12 bit)
access : read-write
PG_MODE : 0 = Flex mode 1 = Pair mode
bits : 12 - 24 (13 bit)
access : read-write
PG_START_MODE : 0 = Auto start mode: pattern generator will start whenever all enabled signals have received a command 1 = Manual start mode: pattern generator will only start if it has been given a PG_START, and all enabled signals have received a command
bits : 13 - 26 (14 bit)
access : read-write
GENSTART_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it starts generating a pattern. It is only valid if SMOTOR_GENSTART_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 14 - 28 (15 bit)
access : read-write
GENEND_IRQ_EN : Determines if the corresponding pattern generator will contribute to the generation of the IRQ when it is done generating a pattern. It is only valid if SMOTOR_GENEND_IRQ_EN is enabled: 0 = Interrupt requests disabled 1 = Interrupt requests enabled
bits : 15 - 30 (16 bit)
access : read-write
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