CTRL_REG

R1_REG

R2_REG

TMP1_REG

TMP2_REG

STATUS_REG

LP_TIMER_REG

PC_REG

SNC_EN : Sensor Node Controller's enable bit-field. When set, it may activate the Sensor Node, provided that the SNC_SW_CTRL bit-field is also set. If not, then the specific bit-field is not effective and Sensor Node's actual enable is controller by the Power Domains Controller (PDC). Note: When SNC_SW_CTRL bit-field is set, the Sensor Node is controlled by the user. Thus, in that mode, it can be started and stopped by setting and resetting the SNC_EN field. When SNC_EN is reset, the Sensor Node will first complete the last on-going command before being halted.
bits : 0 - 0 (1 bit)
access : read-write

SNC_SW_CTRL : When set, this bit-field bypasses the enable of Sensor Node that comes from the PDC. In this mode, the Sensor Node can be started and stopped via the SNC_EN bit-field of SNC_CTRL_REG. Note: This mode is suggested to be used for debugging purposes. Älso, the base address of the Sensor Node should have been programmed to the target value, before this bit-field is set.
bits : 1 - 2 (2 bit)
access : read-write

BUS_ERROR_DETECT_EN : When set, it enables the detection of system bus errors that may occur in case a non-mapped address is used by the Sensor Node controller, when performing a register access. Note: In case of a bus error detection, the Sensor Node will set to '1' the BUS_ERROR_STATUS bit-field of SNC_STATUS_REG and will continue normally to the next command.
bits : 2 - 4 (3 bit)
access : read-write

SNC_RESET : This is the Sensor Node Controller's synchronous clear bit-field. When set, it resets the state of the Sensor Node Controller and sets back its program counter (SNC_PC_REG) to the programmed base address, as determined by SNC_BASE_REG register (located in memory controller). This bit-field is auto-cleared with the next SNC clock. Note: Setting this bit-field may interrupt the Sensor Node's regular execution and any command currently being exeucuted may be abnormally terminated.
bits : 3 - 6 (4 bit)
access : read-write

SNC_BRANCH_LOOP_INIT : When set, it clears the value of the counter used in the Sensor Node's branch command (COBR), when performing an iterative branch of up to 128 times. This bit-field is auto-cleared with the next SNC clock.
bits : 4 - 8 (5 bit)
access : read-write

SNC_IRQ_EN : When set, the specific bit-field may generate a (level-sensitive) IRQ to trigger either the host processor (CM33) or the Power Domains Controller (PDC) or both, depending on the configuration set in the SNC_IRQ_CONFIG bit-field of SNC_CTRL_REG. As soon as the SNC_IRQ_EN is set, it can be cleared only by setting the SNC_IRQ_ACK bit-field.
bits : 5 - 10 (6 bit)
access : read-write

SNC_IRQ_CONFIG : The specific bit-field determines if the IRQ line of the Sensor Node will be routed towards either the host processor (CM33) or the Power Domains Controller (PDC), or to both of them, according to the following configuration: 0x0 = Neither the CM33 nor the PDC are triggered, both IRQ lines are low regardless of the value of SNC_IRQ_EN bit-field. 0x1 = CM33 should be triggered, provided that SNC_IRQ_EN is set 0x2 = PDC should be triggered, provided that SNC_IRQ_EN is set 0x3 = Both CM33 and PDC should be triggered, provided that SNC_IRQ_EN is set Note: It must be noted that the specific bit-field is locked after set the SNC_IRQ_EN field of the same register. Hence, the SNC IRQ configuration cannot be changed after the IRQ bit-field is set and before the IRQ is acknowledged (by CM33). It is also noted that after having set SNC_IRQ_EN via SW, the specific bit-field can be de-asserted only by setting the SNC_IRQ_ACK bit-field (see also the description of this bit-field, also residing in SNC_CTRL_REG).
bits : 6 - 13 (8 bit)
access : read-write

SNC_IRQ_ACK : When set, the specific bit-field auto-clears the SNC_IRQ_EN field, if the latter is already set. By this way, the IRQ line towards either the CM33 and/or the PDC is cleared. Hence, the CM33 should set this bit-field as soon as it captures the interrupt from the Sensor Node. Note: Any SW writes to this bit-field will be discarded if the SNC_IRQ_EN bit-field is not set. It is finally noted that the SNC_IRQ_ACK bit-field is also auto-clear and it is de-asserted together with SNC_IRQ_EN.
bits : 8 - 16 (9 bit)
access : read-write

R1_REG : Returns the current value of the first 32-bit of the last SNC command executed.
bits : 0 - 31 (32 bit)
access : read-only

R2_REG : Returns the current value of the second 32-bit word of the last SNC command executed. This is useful for the SNC commands composed by two 32-bit words.
bits : 0 - 31 (32 bit)
access : read-only

TMP1_REG : Returns the current value of the Sensor Node's first temporary register. To be used for debugging purposes.
bits : 0 - 31 (32 bit)
access : read-only

TMP2_REG : Returns the current value of the Sensor Node's second temporary register. To be used for debugging purposes.
bits : 0 - 31 (32 bit)
access : read-only

EQ_FLAG : Sensor Node's 'EQ' (equalhigh) flag. It can be modified either by the Sensor Node's core (by executing an RDCBI command) or by the Sensor Node's microcode, when the latter directly modifies the specific bit-field of SNC_STATUS_REG. When the Sensor Node's FSM is in its initial state (which may happen either by switching-on the PD_COM power domain or by resetting the Sensor Node via SNC_CTRL_REG.SNC_RESET), the specific bit-field is kept to '0', for initialization purposes. When the Sensor Node is stopped and then reset, the Sensor Node's FSM is not in its initial state and in that case, the EQ_FLAG bit-field should be reset by the user (if the application needs this to be initialized to '0'). Otherwise, it can be left as it is, until being updated by the Sensor Node itself (upon executing an RDCBI command). In general, however, this bit-field should not be modified by either the host processor (CM33) or the CMAC processor (CM0+), and especially when the Sensor Node is enabled and operational.
bits : 0 - 0 (1 bit)
access : read-write

GR_FLAG : Sensor Node's 'GR' (greater) flag. It can be modified either by the Sensor Node's core (by executing an RDCGR command) or by the Sensor Node's microcode, when the latter directly modifies the specific bit-field of SNC_STATUS_REG. When the Sensor Node's FSM is in its initial state (which may happen either by switching-on the PD_COM power domain or by resetting the Sensor Node via SNC_CTRL_REG.SNC_RESET), the specific bit-field is kept to '0', for initialization purposes. When the Sensor Node is stopped and then reset, the Sensor Node's FSM is not in its initial state and in that case, the GR_FLAG bit-field should be reset by the user (if the application needs this to be initialized to '0'). Otherwise, it can be left as it is, until being updated by the Sensor Node itself (upon executing an RDCGR command). In general, however, this bit-field should not be modified by either the host processor (CM33) or the CMAC processor (CM0+), and especially when the Sensor Node is enabled and operational.
bits : 1 - 2 (2 bit)
access : read-write

SNC_DONE_STATUS : 0 : Sensor Node has not yet completed the target program's execution. 1 : Sensor Node has completed the targer program's execution. Together with the update of the status bit, a pulse is also generated to notify the PDC that the Sensor Node is done. Note: This bit-field is set only when the SLP (sleep) command is executed, which should be issued after the completion of all pending tasks of the Sensor Node. It will be reset to '0' only when the Sensor Node re-starts, by executing from the base address. This can be done by either toggling (de-asserting and re-asserting again) the SNC_EN bit-field of SNC_CTRL_REG, if the SNC is controlled by SW, or by just re-setting the SNC state via the SNC_RESET bit-field of the same register.
bits : 2 - 4 (3 bit)
access : read-only

BUS_ERROR_STATUS : 0 : No system bus error detected, Sensor Node continues normally 1 : Bus error occurred. Sensor Node will continue, but it will also set the specific flag, which can be used for debugging purposes. Note: This bit-field will be reset to '0' only when the Sensor Node is re-initialized, by starting again from its base address.
bits : 3 - 6 (4 bit)
access : read-only

HARD_FAULT_STATUS : 0 : No opcode error has occurred, Sensor Node continues normally. 1 : An opcode error has occurred. Sensor Node will continue its execution, but will set also the specific bit-field to '1', for debugging purposes. Note: After being set, this bit-field will be cleared only when the Sensor Node is re-initialized, by starting again from its base address. The latter can happen either by activating the SNC_RESET bit-field of SNC_CTRL_REG or by stopping and starting again the Sensor Node. This is possible only when the PDC is bypassed, so when the Sensor Node is controlled by SNC_EN and SNC_SW_CTRL bit-fields of SNC_CTRL_REG.
bits : 4 - 8 (5 bit)
access : read-only

SNC_IS_STOPPED : 0 : Sensor Node is operational and its FSM is running. 1 : Sensor Node is stopped and its FSM is halted.To leave this state, the SNC_EN bit-field of SNC_CTRL_REG must be set, provided that the SNC_SW_CTRL bit-field of the same register is also set. This mode is used for debugging purposes, bypassing the enable of SNC coming from the Power Domains Controller. Note: The SNC_PC_REG register can be modified by SW if and only if the SNC_IS_STOPPED bit is set. Otherwise, the writes to SNC_PC_REG are discarded.
bits : 5 - 10 (6 bit)
access : read-only

SNC_PC_LOADED : 0 : Sensor node's program counter is controlled by the Sensor Node's FSM, incemented by 4 after the fetching of each 32-bit command word. 1 : Sensor node's program counter is loaded with a new value. The assertion of this signal requires the Sensor Node to have been first stopped, so the user must first check that the SNC_IS_STOPPED bit-field of this register is asserted, before writing the program counter. The SNC_PC_LOADED bit-field is auto-clear and it is reset to '0' as soon as the user has re-started the Sensor Node. Note: To start and stop the Sensor Node manually, the SNC_SW_CTRL and SNC_EN bit-fields of SNC_CTRL_REG must have been set by the user. This mode of operation is bypassing the Power Domains Controller and it is to be used for debugging purposes.
bits : 6 - 12 (7 bit)
access : read-only

LP_TIMER : This bit-field returns the current value of the Sensor Node's 8-bit timer, running with the low-power clock and may be used for debugging purposes. The specific timer is used to implement a delay of up to 256 ticks of the low-power clock.
bits : 0 - 7 (8 bit)
access : read-only

PC_REG : This bit-field returns the Sensor Node's program counter bits [18:2], which at the same time is the program counter's offset from the starting address of SYSRAM (0x20.000.000), and it is can be set by the user, as soon as Sensor Node has been stopped. The 13 MSBs of the program counter are tied to '0x400', since the Sensor Node always executes from SYSRAM, while its 2 LSBs are always tied to '0', since memory accesses are always of 32-bit. NOTE: The Sensor Node can be stopped by clearing the SNC_EN bit-field of SNC_CTRL_REG and provided that the Power Domains Controller (PDC) is bypassed. The latter can be done by setting to '1' the SNC_SW_CTRL bit-field of SNC_CTRL_REG.
bits : 2 - 20 (19 bit)
access : read-write