CTRL_REG

RX_TX_REG

CLEAR_INT_REG

SPI_ON : 0 = SPI Module switched off (power saving). Everything is reset except SPI_CTRL_REG. When this bit is cleared the SPI will remain active in master mode until the shift register and holding register are both empty. 1 = SPI Module switched on. Should only be set after all control bits have their desired values. So two writes are needed!
bits : 0 - 0 (1 bit)
access : read-write

SPI_PHA : Select SPI_CLK phase. See functional timing diagrams in SPI chapter
bits : 1 - 2 (2 bit)
access : read-write

SPI_POL : Select SPI_CLK polarity. 0 = SPI_CLK is initially low. 1 = SPI_CLK is initially high.
bits : 2 - 4 (3 bit)
access : read-write

SPI_CLK : Select SPI_CLK clock output frequency in master mode: 00 = SPI_CLK / 8 01 = SPI_CLK / 4 10 = SPI_CLK / 2 11 = SPI_CLK / 14
bits : 3 - 7 (5 bit)
access : read-write

SPI_DO : Pin SPI_DO output level when SPI is idle or when SPI_FORCE_DO=1
bits : 5 - 10 (6 bit)
access : read-write

SPI_SMN : Master/slave mode 0 = Master 1 = Slave
bits : 6 - 12 (7 bit)
access : read-write

SPI_RST : 0 = normal operation 1 = Reset SPI. Same function as SPI_ON except that internal clock remain active.
bits : 7 - 14 (8 bit)
access : read-write

SPI_WORD : 00 = 8 bits mode 01 = 16 bit mode 10 = 32 bits mode 11 = 9 bits mode. Only valid in master mode.
bits : 8 - 17 (10 bit)
access : read-write

SPI_FORCE_DO : 0 = normal operation 1 = Force SPIDO output level to value of SPI_DO.
bits : 10 - 20 (11 bit)
access : read-write

SPI_TXH : 0 = TX-FIFO is not full, data can be written. 1 = TX-FIFO is full, data can not be written.
bits : 11 - 22 (12 bit)
access : read-only

SPI_DI : Returns the actual value of pin SPI_DIN (delayed with two internal SPI clock cycles)
bits : 12 - 24 (13 bit)
access : read-only

SPI_INT_BIT : 0 = RX Register or FIFO is empty. 1 = SPI interrupt. Data has been transmitted and receivedMust be reset by SW by writing to SPI_CLEAR_INT_REG.
bits : 13 - 26 (14 bit)
access : read-only

SPI_MINT : 0 = Disable SPI_INT_BIT to ICU 1 = Enable SPI_INT_BIT to ICU.
bits : 14 - 28 (15 bit)
access : read-write

SPI_EN_CTRL : 0 = SPI_EN pin disabled in slave mode. Pin SPI_EN is don't care. 1 = SPI_EN pin enabled in slave mode.
bits : 15 - 30 (16 bit)
access : read-write

SPI_FIFO_MODE : 0 = TX-FIFO and RX-FIFO used (Bidirectional mode). 1 = RX-FIFO used (Read Only Mode) TX-FIFO single depth, no flow control 2 = TX-FIFO used (Write Only Mode), RX-FIFO single depth, no flow control 3 = No FIFOs used (backwards compatible mode)
bits : 16 - 33 (18 bit)
access : read-write

SPI_PRIORITY : 0 = The SPI has low priority, the DMA request signals are reset after the corresponding acknowledge. 1 = The SPI has high priority, DMA request signals remain active until the FIFOS are filled/emptied, so the DMA holds the AHB bus.
bits : 18 - 36 (19 bit)
access : read-write

SPI_BUSY : 0 = The SPI is not busy with a transfer. This means that either no TX-data is available or that the transfers have been suspended due to a full RX-FIFO. The SPI_CTRL_REG[SPI_INT_BIT] can be used to distinguish between these situations. 1 = The SPI is busy with a transfer.
bits : 19 - 38 (20 bit)
access : read-only

SPI_9BIT_VAL : Determines the value of the first bit in 9 bits SPI mode.
bits : 20 - 40 (21 bit)
access : read-write

SPI_RX_FIFO_EMPTY : 0 = Receive fifo is not empty 1 = Receive fifo is empty
bits : 21 - 42 (22 bit)
access : read-only

SPI_RX_FIFO_FULL : 0 = Receive fifo is not full 1 = Receive fifo is full
bits : 22 - 44 (23 bit)
access : read-only

SPI_TX_FIFO_EMPTY : 0 = Trasmit fifo is not empty 1 = Trasmit fifo is empty
bits : 23 - 46 (24 bit)
access : read-only

SPI_DMA_TXREQ_MODE : In case SPI_FIFO_MODE=3 0 = DMA TX request is generated when transaction is finished 1 = DMA TX request is generated when tx buffer is free
bits : 24 - 48 (25 bit)
access : read-write

SPI_TX_FIFO_NOTFULL_MASK : When 1, SPI Interrupt is generated when TX fifo is not full
bits : 25 - 50 (26 bit)
access : read-write

SPI_DATA : Write: SPI_TX_REG output register 0 (TX-FIFO) Read: SPI_RX_REG input register 0 (RX-FIFO) In 8 or 9 bits mode bits 31 to 8 are not used, they contain old data. In 16 bits mode bits 31 to 16 are not used, they contain old data.
bits : 0 - 31 (32 bit)
access : write-only

SPI_CLEAR_INT : Writing any value to this register will clear the SPI_CTRL_REG[SPI_INT_BIT] Reading returns 0.
bits : 0 - 31 (32 bit)
access : write-only