MCTRL_REG

FAR_REG

NFSR_REG

MAEV_REG

DMA_CTRL_REG

CHARGER_CTRL_REG

CHARGER_STAT_REG

MAMSK_REG

ALTEV_REG

ALTMSK_REG

TXEV_REG

TXMSK_REG

RXEV_REG

RXMSK_REG

NAKEV_REG

NAKMSK_REG

XCVDIAG_REG

FWEV_REG

FWMSK_REG

FNH_REG

FNL_REG

UX20CDR_REG

TCR_REG

EPC0_REG

TXD0_REG

TXS0_REG

TXC0_REG

EP0_NAK_REG

RXD0_REG

RXS0_REG

RXC0_REG

EPC1_REG

TXD1_REG

TXS1_REG

TXC1_REG

EPC2_REG

RXD1_REG

RXS1_REG

RXC1_REG

UTR_REG

EPC3_REG

TXD2_REG

TXS2_REG

TXC2_REG

EPC4_REG

RXD2_REG

RXS2_REG

RXC2_REG

EPC5_REG

TXD3_REG

TXS3_REG

TXC3_REG

EPC6_REG

RXD3_REG

RXS3_REG

RXC3_REG

USBEN : USB EnableSetting this bit to 1 enables the Full/Low Speed USB node. If the USBEN bit is cleared to 0, the USB is disabled and the 48 MHz clock within the USB node is stopped. In addition, all USB registers are set to their reset state. Note that the transceiver forces SE0 on the bus to prevent the hub to detected the USB node, when it is disabled (not attached). The USBEN bit is cleared to 0 after reset
bits : 0 - 0 (1 bit)
access : read-write

USB_DBG : Debug Mode. When this bit is set, the following registers are writable: Main Event (MAEV), Alternate Event (ALTEV), NAK Event (NAKEV), Transmit Status and Receive Status. Setting the DBG bit forces the node into a locked state. The node states can be read out of the transceiver diagnostic register (XCVDIAG) at location 0xFF6802 by setting the DIAG bit in the Test Control register (UTR). Note: The operation of CoR bits is not effected by entering Debug mode) Note: This bit can only be set is USBEN is '1'
bits : 1 - 2 (2 bit)
access : read-write

USB_NAT : Node Attached This bit indicates that this node is ready to be detected as attached to USB. When cleared to 0 the transceiver forces SE0 on the USB port to prevent the hub (to which this node is connected to) from detecting an attach event. After reset or when the USB node is disabled, this bit is cleared to 0 to give the device time before it must respond to commands. After this bit has been set to 1, the device no longer drives the USB and should be ready to receive Reset signalling from the hub. Note: This bit can only be set is USBEN is '1'
bits : 3 - 6 (4 bit)
access : read-write

LSMODE : Low Speed Mode This bit enables USB 1.5 Mbit/s low speed and swaps D+ and D- pull-up resistors. Changing speed may only be done if USBEN is set to 0. Also D+ and D- rise and fall times are adjusted according to the USB specification.
bits : 4 - 8 (5 bit)
access : read-write

USB_AD : Address This field holds the 7-bit function address used to transmit and receive all tokens addressed to this device.
bits : 0 - 6 (7 bit)
access : read-write

USB_AD_EN : Address Enable When set to 1, USB address field bits 6-0 are used in address comparison When cleared to 0, the device does not respond to any token on the USB bus. Note: If the DEF bit in the Endpoint Control 0 register is set, Endpoint 0 responds to the default address.
bits : 7 - 14 (8 bit)
access : read-write

USB_NFS : The Node Functional State Register reports and controls the current functional state of the USB node. 00: NodeReset. This is the USB Reset state. This is entered upon a module reset or by software upon detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be cleared by software on entry to this state. On exit, DEF should be reset so the device responds to the default address. 01: NodeResume In this state, resume signalling is generated. This state should be entered by firmware to initiate a remote wake-up sequence by the device. The node must remain in this state for at least 1 ms and no more than 15 ms. 10: NodeOperational This is the normal operational state. In this state the node is configured for operation on the USB bus. 11: NodeSuspend Suspend state should be entered by firmware on detection of a Suspend event while in Operational state. While in Suspend state, the transceivers operate in their low-power suspend mode. All endpoint controllers and the bits TX_EN, LAST and RX_EN are reset, while all other internal states are frozen. On detection of bus activity, the RESUME bit in the ALTEV register is set. In response, software can cause entry to NodeOperational state.
bits : 0 - 1 (2 bit)
access : read-write

USB_WARN : Warning Event This bit indicates that one of the unmasked bits in the FIFO Warning Event (FWEV) register has been set to 1. This bit is cleared to 0 by reading the FWEV register.
bits : 0 - 0 (1 bit)
access : read-write

USB_ALT : Alternate Event This bit indicates that one of the unmasked ALTEV register bits has been set to 1. This bit is cleared to 0 by reading the ALTEV register.
bits : 1 - 2 (2 bit)
access : read-write

USB_TX_EV : Transmit Event This bit is set to 1, if any of the unmasked bits in the Transmit Event (TXEV) register (TXFIFOn or TXUNDRNn) is set to 1. Therefore, it indicates that an IN transaction has been completed. This bit is cleared to 0 when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSn) register are cleared to 0.
bits : 2 - 4 (3 bit)
access : read-write

USB_FRAME : Frame Event This bit is set to 1, if the frame counter is updated with a new value. This can be due to the receipt of a valid SOF packet on the USB or to an artificial update if the frame counter was unlocked or a frame was missed. This bit is cleared to 0 when the register is read.
bits : 3 - 6 (4 bit)
access : read-write

USB_NAK : Negative Acknowledge Event This bit indicates that one of the unmasked NAK Event (NAKEV) register bits has been set to 1. This bit is cleared to 0 when the NAKEV register is read.
bits : 4 - 8 (5 bit)
access : read-write

USB_ULD : Unlocked/Locked Detected This bit is set to 1, when the frame timer has either entered unlocked condition from a locked condition, or has re-entered a locked condition from an unlocked condition as determined by the UL bit in the Frame Number (FNH or FNL) register. This bit is cleared to 0 when the register is read.
bits : 5 - 10 (6 bit)
access : read-write

USB_RX_EV : Receive Event This bit is set to 1 if any of the unmasked bits in the Receive Event (RXEV) register is set to 1. It indicates that a SETUP or OUT transaction has been completed. This bit is cleared to 0 when all of the RX_LAST bits in each Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared to 0.
bits : 6 - 12 (7 bit)
access : read-write

USB_INTR : Master Interrupt Enable This bit is hardwired to 0 in the Main Event (MAEV) register bit 7 in the Main Mask (MAMSK) register is the Master Interrupt Enable.
bits : 7 - 14 (8 bit)
access : read-write

USB_EP0_TX : Endpoint 0 Transmit Event This bit is a copy of the TXS0[TX_DONE] bit and is cleared to 0 when the TXS0 register is read. Note: Since Endpoint 0 implements a store and forward principle, an underrun condition for FIFO0 cannot occur.
bits : 8 - 16 (9 bit)
access : read-write

USB_EP0_RX : Endpoint 0 Receive Event This bit is a copy of the RXS0[RX_LAST] and is cleared to 0 when this RXS0 register is read. Note: Since Endpoint 0 implements a store and forward principle, an overrun condition for FIFO0 cannot occur
bits : 9 - 18 (10 bit)
access : read-write

USB_EP0_NAK : Endpoint 0 NAK Event This bit is an OR of EP0_NAK_REG[EP0_OUTNAK] and EP0_NAK_REG[EP0_INNAK] bits. USB_EP0_NAK is cleared to 0 when EP0_NAK_REG is read.
bits : 10 - 20 (11 bit)
access : read-write

USB_CH_EV : USB Charger event This bit is set if one of the bits in USB_CHARGER_STAT_REG[2-0] change. This bit is cleared to 0 when if USB_CHARGER_STAT_REG is read.
bits : 11 - 22 (12 bit)
access : read-write

USB_DMA_RX : 000 = DMA channels 0 is connected Rx USB Endpoint 2 001 = DMA channels 0 is connected Rx USB Endpoint 4 010 = DMA channels 0 is connected Rx USB Endpoint 6 100, 1xx = Reserved
bits : 0 - 2 (3 bit)
access : read-write

USB_DMA_TX : 000 = DMA channels 1 is connected Tx USB Endpoint 1 001 = DMA channels 1 is connected Tx USB Endpoint 3 010 = DMA channels 1 is connected Tx USB Endpoint 5 100, 1xx = Reserved
bits : 3 - 8 (6 bit)
access : read-write

USB_DMA_EN : 0 = USB DMA control off. (Normal operation) 1 = USB_DMA on. DMA channels 0 and 1 are connected by USB Endpoint according bits USB_DMA_TX and USB_DMA_RX
bits : 6 - 12 (7 bit)
access : read-write

USB_CHARGE_ON : 0 = Disable USB charger detect circuit. 1 = Enable USB charger detect circuit.
bits : 0 - 0 (1 bit)
access : read-write

IDP_SRC_ON : 0 = Disable 1 = Enable the Idp_src and Rdm_dwn.
bits : 1 - 2 (2 bit)
access : read-write

VDP_SRC_ON : 0 = Disable 1 = Enable the Vdp_src to USB_CHG_DET status bit.
bits : 2 - 4 (3 bit)
access : read-write

VDM_SRC_ON : 0 = Disable 1 = Enable Vdm_src to USBm and USB_DCP_DET status bit.
bits : 3 - 6 (4 bit)
access : read-write

IDP_SINK_ON : 0 = Disable 1 = Enable the Idp_sink to USBp
bits : 4 - 8 (5 bit)
access : read-write

IDM_SINK_ON : 0 = Disable 1 = Enable the Idm_sink to USBm
bits : 5 - 10 (6 bit)
access : read-write

USB_DCP_DET : 0 = Charging downstream port is detected. 1 = Dedicated charger is detected. Control bit VDM_SRC_ON must be set to validate this status bit. Note: This register shows the actual status.
bits : 0 - 0 (1 bit)
access : read-only

USB_CHG_DET : 0 = Standard downstream or nothing connected. 1 = Charging Downstream Port (CDP) or Dedicated Charging.
bits : 1 - 2 (2 bit)
access : read-only

USB_DP_VAL : 0 = USBp < 0.8V 1 = USBp > 1.5V
bits : 2 - 4 (3 bit)
access : read-only

USB_DM_VAL : 0 = USBm < 0.8V 1 = USBm > 1.5V (PS2 or Proprietary Charger)
bits : 3 - 6 (4 bit)
access : read-only

USB_DP_VAL2 : 0: USBp < 2.3V 1: USBp > 2.5V
bits : 4 - 8 (5 bit)
access : read-only

USB_DM_VAL2 : 0 = USBm <2.3V 1 = USBm >2.5V
bits : 5 - 10 (6 bit)
access : read-only

USB_M_WARN : Same Bit Definition as MAEV Register
bits : 0 - 0 (1 bit)
access : read-write

USB_M_ALT : Same Bit Definition as MAEV Register
bits : 1 - 2 (2 bit)
access : read-write

USB_M_TX_EV : Same Bit Definition as MAEV Register
bits : 2 - 4 (3 bit)
access : read-write

USB_M_FRAME : Same Bit Definition as MAEV Register
bits : 3 - 6 (4 bit)
access : read-write

USB_M_NAK : Same Bit Definition as MAEV Register
bits : 4 - 8 (5 bit)
access : read-write

USB_M_ULD : Same Bit Definition as MAEV Register
bits : 5 - 10 (6 bit)
access : read-write

USB_M_RX_EV : Same Bit Definition as MAEV Register
bits : 6 - 12 (7 bit)
access : read-write

USB_M_INTR : Same Bit Definition as MAEV Register
bits : 7 - 14 (8 bit)
access : read-write

USB_M_EP0_TX : Same Bit Definition as MAEV Register
bits : 8 - 16 (9 bit)
access : read-write

USB_M_EP0_RX : Same Bit Definition as MAEV Register
bits : 9 - 18 (10 bit)
access : read-write

USB_M_EP0_NAK : Same Bit Definition as MAEV Register
bits : 10 - 20 (11 bit)
access : read-write

USB_M_CH_EV : The Main Mask Register masks out events reported in the MAEV registers. A bit set to 1, enables the interrupts for the respective event in the MAEV register. If the corresponding bit is cleared to 0, interrupt generation for this event is disabled. Same Bit Definition as MAEV Register
bits : 11 - 22 (12 bit)
access : read-write

USB_EOP : End of Packet A valid EOP sequence was been detected on the USB. It is used when this device has initiated a Remote wake-up sequence to indicate that the Resume sequence has been acknowledged and completed by the host. This bit is cleared when the register is read.
bits : 3 - 6 (4 bit)
access : read-write

USB_SD3 : Suspend Detect 3 ms This bit is set to 1 after 3 ms of IDLE have been detected on the upstream port, indicating that the device should be suspended. The suspend occurs under firmware control by writing the suspend value to the Node Functional State (NFSR) register. This bit is cleared when the register is read.
bits : 4 - 8 (5 bit)
access : read-write

USB_SD5 : Suspend Detect 5 ms This bit is set to 1 after 5 ms of IDLE have been detected on the upstream port, indicating that this device is permitted to perform a remote wake-up operation. The resume may be initiated under firmware control by writing the resume value to the NFSR register. This bit is cleared when the register is read.
bits : 5 - 10 (6 bit)
access : read-write

USB_RESET : Reset This bit is set to 1, when 2.5 us of SEO have been detected on the upstream port. In response, the functional state should be reset (NFS in the NFSR register is set to RESET), where it must remain for at least 100 us. The functional state can then return to Operational state. This bit is cleared when the register is read
bits : 6 - 12 (7 bit)
access : read-write

USB_RESUME : Resume Resume signalling is detected on the USB when the device is in Suspend state (NFS in the NFSR register is set to SUSPEND), and a non IDLE signal is present on the USB, indicating that this device should begin it's wake-up sequence and enter Operational state. This bit is cleared when the register is read.
bits : 7 - 14 (8 bit)
access : read-write

USB_M_EOP : Same Bit Definition as ALTEV Register
bits : 3 - 6 (4 bit)
access : read-write

USB_M_SD3 : Same Bit Definition as ALTEV Register
bits : 4 - 8 (5 bit)
access : read-write

USB_M_SD5 : Same Bit Definition as ALTEV Register
bits : 5 - 10 (6 bit)
access : read-write

USB_M_RESET : Same Bit Definition as ALTEV Register
bits : 6 - 12 (7 bit)
access : read-write

USB_M_RESUME : A bit set to 1 in this register enables automatic setting of the ALT bit in the MAEV register when the respective event in the ALTEV register occurs. Otherwise, setting MAEV.ALT bit is disabled. Same Bit Definition as ALTEV Register
bits : 7 - 14 (8 bit)
access : read-write

USB_TXFIFO31 : Transmit FIFO n: 3:1 The bit n is a copy of the TX_DONE bit from the corresponding Transmit Status register (TXSn). A bit is set to 1 when the IN transaction for the corresponding transmit endpoint n has been completed. These bits are cleared to 0 when the corresponding TXSn register is read.
bits : 0 - 2 (3 bit)
access : read-only

USB_TXUDRRN31 : Transmit Underrun n: 3:1 The bit n is a copy of the respective TX_URUN bit from the corresponding Transmit Status register (TXSn). Whenever any of the Transmit FIFOs underflows, the respective TXUDRRN bit is set to 1. These bits are cleared to 0 when the corresponding Transmit Status register is read
bits : 4 - 10 (7 bit)
access : read-only

USB_M_TXFIFO31 : Same Bit Definition as TXEV Register
bits : 0 - 2 (3 bit)
access : read-write

USB_M_TXUDRRN31 : The Transmit Mask Register is used to select the bits of the TXEV registers, which causes the TX_EV bit in the MAEV register to be set to 1. When a bit is set to 1 and the corresponding bit in the TXEV register is set to 1, the TX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the TXEV register does not cause TX_EV to be set to 1. Same Bit Definition as TXEV Register
bits : 4 - 10 (7 bit)
access : read-write

USB_RXFIFO31 : Receive FIFO n: 3:1 The bit n is set to 1 whenever either RX_ERR or RX_LAST in the respective Receive Status register (RXSn) is set to 1. Reading the corresponding RXSn register automatically clears these bits.The CoR function is disabled, when the Freeze signal is asserted.The USB node discards all packets for Endpoint 0 received with errors. This is necessary in case of retransmission due to media errors, ensuring that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be tied up, holding corrupted data and unable to receive a retransmission of the same packet. If data streaming is used for the receive endpoints (EP2, EP4 and EP6, EP8) the firmware must check the respective RX_ERR bits to ensure the packets received are not corrupted by errors.
bits : 0 - 2 (3 bit)
access : read-only

USB_RXOVRRN31 : Receive Overrun n: 3:1 The bit n is set to 1 in the event of an overrun condition in the corresponding receive FIFO n. They are cleared to 0 when the register is read. The firmware must check the respective RX_ERR bits that packets received for the other receive endpoints (EP2, EP4 and EP6, ) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual FIFO depth).
bits : 4 - 10 (7 bit)
access : read-only

USB_M_RXFIFO31 : Same Bit Definition as RXEV Register
bits : 0 - 2 (3 bit)
access : read-write

USB_M_RXOVRRN31 : The Receive Mask Register is used to select the bits of the RXEV registers, which causes the RX_EV bit in the MAEV register to be set to 1. When set to 1 and the corresponding bit in the RXEV register is set to 1, RX_EV bit in the MAEV register is set to1. When cleared to 0, the corresponding bit in the RXEV register does not cause RX_EV to be set to1. Same Bit Definition as RXEV Register
bits : 4 - 10 (7 bit)
access : read-write

USB_IN31 : IN n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the Function Address, FAR, register is set to 1 and EP_EN in the Endpoint Control, EPCx, register is set to 1) in response to an IN token. This bit is cleared when the register is read.
bits : 0 - 2 (3 bit)
access : read-only

USB_OUT31 : OUT n: 3:1 The bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1 and EP_EN in the EPCx register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read.
bits : 4 - 10 (7 bit)
access : read-only

USB_M_IN31 : Same Bit Definition as NAKEV Register
bits : 0 - 2 (3 bit)
access : read-write

USB_M_OUT31 : When set and the corresponding bit in the NAKEV register is set, the NAK bit in the MAEV register is set. When cleared, the corresponding bit in the NAKEV register does not cause NAK to be set. Same Bit Definition as NAKEV Register
bits : 4 - 10 (7 bit)
access : read-write

USB_XCV_TEST : Enable USB_XCVDIAG_REG 0: Normal operation, test bits disabled 1: Enable test bits 7,6,5,3,2,1
bits : 0 - 0 (1 bit)
access : read-write

USB_XCV_TXp : With Bit3,0 = 1, this bit sets USB_Dp to a high level, independent of LSMODE selection
bits : 1 - 2 (2 bit)
access : read-write

USB_XCV_TXn : With Bit3,0 = 1, this bit sets USB_Dm to a high level, independent of LSMODE selection
bits : 2 - 4 (3 bit)
access : read-write

USB_XCV_TXEN : With Bit0 = 1, this bit enables test Bits 2,1. Must be kept to '0' for normal operation
bits : 3 - 6 (4 bit)
access : read-write

USB_RCV : With Bit0 = 1 this bit shows the differential level of the receive comparator.
bits : 5 - 10 (6 bit)
access : read-only

USB_VMIN : With Bit0 = 1 this bit shows the level USB_Dm receive data from transceiver i.e. D- <= VSE.
bits : 6 - 12 (7 bit)
access : read-only

USB_VPIN : With Bit0 = 1 this bit shows the level of the USB_Dp receive data from transceiver i.e. D+ <= VSE.
bits : 7 - 14 (8 bit)
access : read-only

USB_TXWARN31 : Transmit Warning n: 3:1 The bit n is set to 1 when the respective transmit endpoint FIFO reaches the warning limit, as specified by the TFWL bits of the respective TXCn register, and transmission from the respective endpoint is enabled. This bit is cleared when the warning condition is cleared by either writing new data to the FIFO when the FIFO is flushed, or when transmission is done, as indicated by the TX_DONE bit in the TXSn register.
bits : 0 - 2 (3 bit)
access : read-only

USB_RXWARN31 : Receive Warning n: 3:1 The bit n is set to 1 when the respective receive endpoint FIFO reaches the warning limit, as specified by the RFWL bits of the respective EPCx register. This bit is cleared when the warning condition is cleared by either reading data from the FIFO or when the FIFO is flushed.
bits : 4 - 10 (7 bit)
access : read-only

USB_M_TXWARN31 : The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register
bits : 0 - 2 (3 bit)
access : read-write

USB_M_RXWARN31 : The FIFO Warning Mask Register selects, which FWEV bits are reported in the MAEV register. A bit set to 1 and the corresponding bit in the FWEV register is set 1, causes the WARN bit in the MAEV register to be set to 1. When cleared to 0, the corresponding bit in the FWEV register does not cause WARN to be set to 1. Same Bit Definition as FWEV Register
bits : 4 - 10 (7 bit)
access : read-write

USB_FN_10_8 : Frame Number This 3-bit field contains the three most significant bits (MSB) of the current frame number, received in the last SOF packet. If a valid frame number is not received within 12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change, the frame number is incremented artificially. If two successive frames are missed or are incorrect, the current FN is frozen and loaded with the next frame number from a valid SOF packet. If the frame number low byte was read by firmware before reading the FNH register, the user actually reads the contents of a buffer register which holds the value of the three frame number bits of this register when the low byte was read. Therefore, the correct sequence to read the frame number is: FNL, FNH. Read operations to the FNH register, without first reading the Frame Number Low Byte (FNL) register directly, read the actual value of the three MSBs of the frame number.
bits : 0 - 2 (3 bit)
access : read-only

USB_RFC : Reset Frame Count Writing a 1 to this bit resets the frame number to 00016, after which this bit clears itself to 0 again. This bit always reads 0.
bits : 5 - 10 (6 bit)
access : read-only

USB_UL : Unlock Flag This bit indicates that at least two frames were received without an expected frame number, or that no valid SOF was received within 12060 bit times. If this bit is set, the frame number from the next valid SOF packet is loaded in FN. This bit is set by the hardware and is cleared by reading the FNH register.
bits : 6 - 12 (7 bit)
access : read-only

USB_MF : Missed SOF Flag This flag is set to 1, when the frame number in a valid received SOF does not match the expected next value, or when an SOF is not received within 12060 bit times. This bit is set by the hardware and is cleared by reading the FNH register.
bits : 7 - 14 (8 bit)
access : read-only

USB_FN : The Frame Number Low Byte Register holds the low byte of the frame number. To ensure consistency, reading this low byte causes the three frame number bits in the FNH register to be locked until this register is read. The correct sequence to read the frame number is: FNL, FNH.
bits : 0 - 7 (8 bit)
access : read-only

RPU_SSPROTEN : Test bit, must be kept 0
bits : 0 - 0 (1 bit)
access : read-write

RPU_RCDELAY : Test bit, must be kept 0
bits : 1 - 2 (2 bit)
access : read-write

RPU_TEST_SW1DM : 0: Enable the pull-up resistor on USB_Dm (SW1DM closed) 1: Disable the pull-up resistor on USB_Dm (SW1DM open) (Independent of the VBus state).
bits : 2 - 4 (3 bit)
access : read-write

RPU_TEST_EN : Pull-Up Resistor Test Enable 0: Normal operation 1: Enables the test features controlled by RPU_TEST_SW1, RPU_TEST_SW1DM and RPU_TEST_SW2
bits : 4 - 8 (5 bit)
access : read-write

RPU_TEST_SW1 : 0: Enable the pull-up resistor on USB_Dp (SW1 closed) 1: Disable the pull-up resistor on USB_Dp (SW1 open) (Independent of the VBus state).
bits : 5 - 10 (6 bit)
access : read-write

RPU_TEST_SW2 : 0: Closes SW2 switch to reduced pull-up resistor connected to the USB_Dp and USB_Dm. 1: Opens SW2 switch resistor connected to the USB_Dp and USB_Dm (independent of the VBus state).
bits : 6 - 12 (7 bit)
access : read-write

RPU_TEST7 : Test bit
bits : 7 - 14 (8 bit)
access : read-only

USB_CADJ : Transmitter Current Adjust Controls the driver edge rate control current. Shall not be modified unless instructed by Dialog Semiconductor Only enabled if USB_UTR_REG[7] = 1
bits : 0 - 4 (5 bit)
access : read-write

USB_VADJ : Reference Voltage/ Threshold voltage AdjustControls the single-ended receiver threshold. Shall not be modified unless instructed by Dialog Semiconductor Only enabled if USB_UTR_REG[7] = 1
bits : 5 - 12 (8 bit)
access : read-write

USB_EP : Endpoint Address This field holds the 4-bit Endpoint address. For Endpoint 0, these bits are hardwired to 0000b. Writing a 1 to any of the EP bits is ignored.
bits : 0 - 3 (4 bit)
access : read-only

USB_DEF : Default Address When set to 1, the device responds to the default address regardless of the contents of FAR6-0/EP03-0 fields. When an IN packet is transmitted for the endpoint, the DEF bit is automatically cleared to 0. This bit aids in the transition from default address to assigned address. The transition from the default address 00000000000b to an address assigned during bus enumeration may not occur in the middle of the SET_ADDRESS control sequence. This is necessary to complete the control sequence. However, the address must change immediately after this sequence finishes in order to avoid errors when another control sequence immediately follows the SET_ADDRESS command. On USB reset, the firmware has 10 ms for set-up, and should write 8016 to the FAR register and 0016 to the EPC0 register. On receipt of a SET_ADDRESS command, the firmware must write 4016 to the EPC0 register and (8016 or ) to the FAR register. It must then queue a zero length IN packet to complete the status phase of the SET_ADDRESS control sequence.
bits : 6 - 12 (7 bit)
access : read-write

USB_STALL : Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: - The transmit FIFO is enabled and an IN token is received. - The receive FIFO is enabled and an OUT token is received. Note: A SETUP token does not cause a STALL handshake to be generated when this bit is set. Upon transmitting the STALL handshake, the RX_LAST and the TX_DONE bits in the respective Receive/Transmit Status registers are set to 1.
bits : 7 - 14 (8 bit)
access : read-write

USB_TXFD : Transmit FIFO Data Byte The firmware is expected to write only the packet payload data. The PID and CRC16 are created automatically.
bits : 0 - 7 (8 bit)
access : write-only

USB_TCOUNT : Transmission Count This 5-bit field indicates the number of empty bytes available in the FIFO. This field is never larger than 8 for Endpoint 0.
bits : 0 - 4 (5 bit)
access : read-only

USB_TX_DONE : Transmission Done When set to 1, this bit indicates that a packet has completed transmission. It is cleared to 0, when this register is read.
bits : 5 - 10 (6 bit)
access : read-only

USB_ACK_STAT : Acknowledge Status This bit indicates the status, as received from the host, of the ACK for the packet previously sent. This bit is to be interpreted when TX_DONE is set to 1. It is set to 1, when an ACK is received otherwise, it remains cleared. This bit is also cleared to 0, when this register is read.
bits : 6 - 12 (7 bit)
access : read-only

USB_TX_EN : Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet, or a STALL handshake, in response to an IN token. It must be set to 1 by firmware to start packet transmission. The RX_EN bit in the Receive Command 0 (RXC0) register takes precedence over this bit i.e. if RX_EN is set, TX_EN bit is ignored until RX_EN is reset. Zero length packets are indicated by setting this bit without writing any data to the FIFO.
bits : 0 - 0 (1 bit)
access : read-write

USB_TOGGLE_TX0 : Toggle This bit specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. This bit is not altered by the hardware.
bits : 2 - 4 (3 bit)
access : read-write

USB_FLUSH : Flush FIFO Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using the FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. It is equivalent to the FLUSH bit in the RXC0 register.
bits : 3 - 6 (4 bit)
access : read-write

USB_IGN_IN : Ignore IN Tokens When this bit is set to 1, the endpoint will ignore any IN tokens directed to its configured address.
bits : 4 - 8 (5 bit)
access : read-write

USB_EP0_INNAK : End point 0 IN NAK This bit is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an IN token. This bit is cleared when the register is read.
bits : 0 - 0 (1 bit)
access : read-only

USB_EP0_OUTNAK : End point 0 OUT NAK This bit n is set to 1 when a NAK handshake is generated for an enabled address/endpoint combination (AD_EN in the FAR register is set to 1) in response to an OUT token. This bit is not set if NAK is generated as result of an overrun condition. It is cleared when the register is read.
bits : 1 - 2 (2 bit)
access : read-only

USB_RXFD : Receive FIFO Data Byte The firmware should expect to read only the packet payload data. The PID and CRC16 are removed from the incoming data stream automatically. In TEST mode this register allow read/write access.
bits : 0 - 7 (8 bit)
access : read-only

USB_RCOUNT : Receive Count This 4-bit field contains the number of bytes presently in the RX FIFO. This number is never larger than 8 for Endpoint 0.
bits : 0 - 3 (4 bit)
access : read-only

USB_RX_LAST : Receive Last Bytes This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read.
bits : 4 - 8 (5 bit)
access : read-only

USB_TOGGLE_RX0 : Toggle This bit specified the PID used when receiving the packet. A value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read.
bits : 5 - 10 (6 bit)
access : read-only

USB_SETUP : Setup This bit indicates that the setup packet has been received. This bit is unchanged for zero length packets. It is cleared to 0 when this register is read.
bits : 6 - 12 (7 bit)
access : read-only

USB_RX_EN : Receive Enable OUT packet reception is disabled after every data packet is received, or when a STALL handshake is returned in response to an OUT token. A 1 must be written to this bit to re-enable data reception. Reception of SETUP packets is always enabled. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet is received with no other intervening non-SETUP tokens, the Endpoint Controller discards the new SETUP packet and returns an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP packet, it must not generate a handshake. This allows recovery from a condition where the ACK of the first SETUP token was lost by the host.
bits : 0 - 0 (1 bit)
access : read-write

USB_IGN_OUT : Ignore OUT Tokens When this bit is set to 1, the endpoint ignores any OUT tokens directed to its configured address.
bits : 1 - 2 (2 bit)
access : read-write

USB_IGN_SETUP : Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address.
bits : 2 - 4 (3 bit)
access : read-write

USB_FLUSH : Flush Writing a 1 to this bit flushes all data from the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data on USB, flushing is delayed until after the transfer is done. This bit is cleared to 0 on reset. This bit is equivalent to FLUSH in the TXC0 register.
bits : 3 - 6 (4 bit)
access : read-write

USB_EP : Endpoint Address This 4-bit field holds the endpoint address.
bits : 0 - 3 (4 bit)
access : read-write

USB_EP_EN : Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus.
bits : 4 - 8 (5 bit)
access : read-write

USB_ISO : Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers.
bits : 5 - 10 (6 bit)
access : read-write

USB_STALL : Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token
bits : 7 - 14 (8 bit)
access : read-write

USB_TXFD : Transmit FIFO Data Byte The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream. In TEST mode this register allow read/write access via the core bus.
bits : 0 - 7 (8 bit)
access : write-only

USB_TCOUNT : Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported.
bits : 0 - 4 (5 bit)
access : read-only

USB_TX_DONE : Transmission Done When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: A data packet completed transmission in response to an IN token with non-ISO operation. The endpoint sent a STALL handshake in response to an IN token A scheduled ISO frame was transmitted or discarded. This bit is cleared to 0 when this register is read.
bits : 5 - 10 (6 bit)
access : read-only

USB_ACK_STAT : Acknowledge Status This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received otherwise, it is cleared to 0. For ISO operation, this bit is set if a frame number LSB match (see IGN_ISOMSK bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set. This bit is also cleared to 0, when this register is read.
bits : 6 - 12 (7 bit)
access : read-only

USB_TX_URUN : Transmit FIFO Underrun This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read.
bits : 7 - 14 (8 bit)
access : read-only

USB_TX_EN : Transmission Enable This bit enables data transmission from the FIFO. It is cleared to 0 by hardware after transmitting a single packet or after a STALL handshake in response to an IN token. It must be set to 1 by firmware to start packet transmission.
bits : 0 - 0 (1 bit)
access : read-write

USB_LAST : Last Byte Setting this bit to 1 indicates that the entire packet has been written into the FIFO. This is used especially for streaming data to the FIFO while the actual transmission occurs. If the LAST bit is not set to 1 and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus. Zero length packets are indicated by setting this bit without writing any data to the FIFO. The transmit state machine transmits the payload data, CRC16 and the EOP signal before clearing this bit.
bits : 1 - 2 (2 bit)
access : read-write

USB_TOGGLE_TX : Toggle The function of this bit differs depending on whether ISO (ISO bit in the EPCn register is set to 1) or non-ISO operation (ISO bit is cleared to 0) is used. For non-ISO operation, it specifies the PID used when transmitting the packet. A value of 0 causes a DATA0 PID to be generated, while a value of 1 causes a DATA1 PID to be generated. For ISO operation, this bit and the LSB of the frame counter (FNL0) act as a mask for the TX_EN bit to allow pre-queuing of packets to specific frame numbers I.e. transmission is enabled only if bit 0 in the FNL register is set to TOGGLE. If an IN token is not received while this condition is true, the contents of the FIFO are flushed with the next SOF. If the endpoint is set to ISO, data is always transferred with a DATA0 PID.
bits : 2 - 4 (3 bit)
access : read-write

USB_FLUSH : Flush FIFO Writing a 1 to this bit flushes all data from the corresponding transmit FIFO, resets the endpoint to Idle state, and clears both the FIFO read and write pointers. If the MAC is currently using the FIFO to transmit, data is flushed after the transmission is complete. After data flushing, this bit is cleared to 0 by hardware.
bits : 3 - 6 (4 bit)
access : read-write

USB_RFF : Refill FIFO Setting the LAST bit to 1 automatically saves the Transmit Read Pointer (TXRP) to a buffer. When the RFF bit is set to 1, the buffered TXRP is reloaded into the TXRP. This allows the user to repeat the last transaction if no ACK was received from the host. If the MAC is currently using the FIFO to transmit, TXRP is reloaded only after the transmission is complete. After reload, this bit is cleared to 0 by hardware.
bits : 4 - 8 (5 bit)
access : read-write

USB_TFWL : Transmit FIFO Warning Limit These bits specify how many more bytes can be transmitted from the respective FIFO before an underrun condition occurs. If the number of bytes remaining in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the FWEV register is set. To avoid interrupts caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the endpoint is enabled (TX_ENn in the TXCn register is set). TFWL[1:0] : 00: TFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO
bits : 5 - 11 (7 bit)
access : read-write

USB_IGN_ISOMSK : Ignore ISO Mask This bit has an effect only if the endpoint is set to be isochronous. If set to 1, this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Thus data is transmitted upon reception of the next IN token. If cleared to 0, data is only transmitted when FNL0 matches TOGGLE. This bit is cleared to 0 after reset.
bits : 7 - 14 (8 bit)
access : read-write

USB_EP : Endpoint Address This 4-bit field holds the endpoint address.
bits : 0 - 3 (4 bit)
access : read-write

USB_EP_EN : Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus.
bits : 4 - 8 (5 bit)
access : read-write

USB_ISO : Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers.
bits : 5 - 10 (6 bit)
access : read-write

USB_STALL : Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token
bits : 7 - 14 (8 bit)
access : read-write

USB_RXFD : Receive FIFO Data Byte The firmware should expect to read only the packet payload data. The PID and CRC16 are terminated by the receive state machine. In TEST mode this register allow read/write access via the core bus.
bits : 0 - 7 (8 bit)
access : read-only

USB_RCOUNT : Receive Counter This 4-bit field contains the number of bytes presently in the endpoint receive FIFO. If this number is greater than 15, a value of 15 is actually reported.
bits : 0 - 3 (4 bit)
access : read-only

USB_RX_LAST : Receive Last This bit indicates that an ACK was sent upon completion of a successful receive operation. This bit is cleared to 0 when this register is read.
bits : 4 - 8 (5 bit)
access : read-only

USB_TOGGLE_RX : Toggle The function of this bit differs depending on whether ISO (ISO in the EPCn register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, a value of 0 indicates that the last successfully received packet had a DATA0 PID, while a value of 1 indicates that this packet had a DATA1 PID. For ISO operation, this bit reflects the LSB of the frame number (FNL0) after a packet was successfully received for this endpoint. This bit is reset to 0 by reading the RXSn register.
bits : 5 - 10 (6 bit)
access : read-only

USB_SETUP : Setup This bit indicates that the setup packet has been received. It is cleared when this register is read.
bits : 6 - 12 (7 bit)
access : read-only

USB_RX_ERR : Receive Error When set to 1, this bit indicates a media error, such as bit-stuffing or CRC. If this bit is set to 1, the firmware must flush the respective FIFO.
bits : 7 - 14 (8 bit)
access : read-only

USB_RXCOUNT : it contains the number of bytes presently in the endpoint receive FIFO (range 0..64)
bits : 8 - 22 (15 bit)
access : read-only

USB_RX_EN : Receive Enable OUT packet cannot be received after every data packet is received, or when a STALL handshake is returned in response to an OUT token. This bit must be written with a 1 to re-enable data reception. SETUP packets can always be received. In the case of back-to-back SETUP packets (for a given endpoint) where a valid SETUP packet has been received with no other intervening non-SETUP tokens, the receive state machine discards the new SETUP packet and returns an ACK handshake. If, for any other reason, the receive state machine cannot accept the SETUP packet, no HANDSHAKE should be generated.
bits : 0 - 0 (1 bit)
access : read-write

USB_IGN_SETUP : Ignore SETUP Tokens When this bit is set to 1, the endpoint ignores any SETUP tokens directed to its configured address.
bits : 2 - 4 (3 bit)
access : read-write

USB_FLUSH : Flush FIFO Writing a 1 to this bit flushes all data from the corresponding receive FIFO, resets the endpoint to Idle state, and resets both the FIFO read and write pointers. If the MAC is currently using the FIFO to receive data, flushing is delayed until after receiving is completed.
bits : 3 - 6 (4 bit)
access : read-write

USB_RFWL : Receive FIFO Warning Limit These bits specify how many more bytes can be received to the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than the selected warning limit, the RXWARN bit in the FWEV register is set to 1.RFWL[1:0] : 00: RFWL disabled 01: Less than 5 bytes remaining in FIFO 10: Less than 9 bytes remaining in FIFO 11: Less than 17 bytes remaining in FIFO
bits : 5 - 11 (7 bit)
access : read-write

USB_UTR_RES : Reserved. Must be kept to '0'
bits : 0 - 4 (5 bit)
access : read-write

USB_SF : Short Frame Enables the Frame timer to lock and track, short, non-compliant USB frame sizes. The Short Frame bit should not be set during normal operation. For test purposes only
bits : 5 - 10 (6 bit)
access : read-write

USB_NCRC : No CRC16 When this bit is set to 1, all packets transmitted by the Full/Low Speed USB node are sent without a trailing CRC16. Receive operations are unaffected. This mode is used to check that CRC errors can be detected by other nodes. For diagnostic purposes only
bits : 6 - 12 (7 bit)
access : read-write

USB_DIAG : Diagnostic enable '0': Normal operational. '1': Access to the USB_XCVDIAG_REG and USB_TCR_REG enabled. For diagnostic purposes only
bits : 7 - 14 (8 bit)
access : read-write

USB_EP : Endpoint Address This 4-bit field holds the endpoint address.
bits : 0 - 3 (4 bit)
access : read-write

USB_EP_EN : Endpoint Enable When this bit is set to 1, the EP[3:0] field is used in address comparison, together with the AD[6:0] field in the FAR register. When cleared to 0, the endpoint does not respond to any token on the USB bus.
bits : 4 - 8 (5 bit)
access : read-write

USB_ISO : Isochronous When this bit is set to 1, the endpoint is isochronous. This implies that no NAK is sent if the endpoint is not ready but enabled i.e. If an IN token is received and no data is available in the FIFO to transmit, or if an OUT token is received and the FIFO is full since there is no USB handshake for isochronous transfers.
bits : 5 - 10 (6 bit)
access : read-write

USB_STALL : Stall Setting this bit to 1 causes the chip to generate STALL handshakes under the following conditions: The transmit FIFO is enabled and an IN token is received. The receive FIFO is enabled and an OUT token is received. Setting this bit to 1 does not generate a STALL handshake in response to a SETUP token
bits : 7 - 14 (8 bit)
access : read-write

USB_TXFD : Transmit FIFO Data Byte The firmware is expected to write only the packet payload data. PID and CRC16 are inserted automatically in the transmit data stream. In TEST mode this register allow read/write access via the core bus.
bits : 0 - 7 (8 bit)
access : write-only

USB_TCOUNT : Transmission Count This 5-bit field holds the number of empty bytes available in the FIFO. If this number is greater than 31, a value of 31 is actually reported.
bits : 0 - 4 (5 bit)
access : read-only

USB_TX_DONE : Transmission Done When set to 1, this bit indicates that the endpoint responded to a USB packet. Three conditions can cause this bit to be set: A data packet completed transmission in response to an IN token with non-ISO operation. The endpoint sent a STALL handshake in response to an IN token A scheduled ISO frame was transmitted or discarded. This bit is cleared to 0 when this register is read.
bits : 5 - 10 (6 bit)
access : read-only

USB_ACK_STAT : Acknowledge Status This bit is interpreted when TX_DONE is set. It's function differs depending on whether ISO (ISO in the EPCx register is set) or non-ISO operation (ISO is reset) is used. For non-ISO operation, this bit indicates the acknowledge status (from the host) about the ACK for the previously sent packet. This bit itself is set to 1, when an ACK is received otherwise, it is cleared to 0. For ISO operation, this bit is set if a frame number LSB match (see IGN_ISOMSK bit in the USB_TXCx_REG) occurs, and data was sent in response to an IN token. Otherwise, this bit is cleared to 0, the FIFO is flushed and TX_DONE is set. This bit is also cleared to 0, when this register is read.
bits : 6 - 12 (7 bit)
access : read-only

USB_TX_URUN : Transmit FIFO Underrun This bit is set to 1, if the transmit FIFO becomes empty during a transmission, and no new data is written to the FIFO. If so, the Media Access Controller (MAC) forces a bit stuff error followed by an EOP. This bit is cleared to 0, when this register is read.
bits : 7 - 14 (8 bit)
access : read-only